Freescale Semiconductor Data Sheet: Technical Data Document Number: MC9S08LG32 Rev. 7, 8/2009 MC9S08LG32 Series Covers: MC9S08LG32 and MC9S08LG16 MC9S08LG32 80-LQFP Case 917A 14 mm × 14 mm 64-LQFP Case 840F 10 mm × 10 mm Features 48-LQFP • 8-bit HCS08 Central Processor Unit (CPU) Case 932 7 mm × 7mm – Up to 40 MHz CPU at 5.5 V to 2.7 V across temperature – On-chip in-circuit emulator (ICE) debug module containing range of –40 °C to 85 °C and –40 °C to 105 °C three comparators and nine trigger modes; eight deep FIFO – HCS08 instruction set with added BGND instruction for storing change-of-flow addresses and event-only data; – Support for up to 32 interrupt/reset sources debug module supports both tag and force breakpoints • On-Chip Memory • Peripherals – 32 KB or 18 KB dual array flash; read/program/erase – LCD — Up to 4 × 41 or 8 × 37 LCD driver with internal over full operating voltage and temperature charge pump. – 1984 byte random access memory (RAM) – ADC — Up to 16-channel, 12-bit resolution; 2.5 μs – Security circuitry to prevent unauthorized access to conversion time; automatic compare function; temperature RAM and flash contents sensor; internal bandgap reference channel; runs in stop3 and • Power-Saving Modes can wake up the system; fully functional from 5.5 V to 2.7 V – Two low-power stop modes (stop2 and stop3) – SCI — Full duplex non-return to zero (NRZ); LIN master – Reduced-power wait mode extended break generation; LIN slave extended break – Peripheral clock gating register can disable clocks to detection; wakeup on active edge unused modules, thereby reducing currents – SPI — Full-duplex or single-wire bidirectional; – Low power on-chip crystal oscillator (XOSC) that can double-buffered transmit and receive; master or slave mode; be used in low-power modes to provide accurate clock MSB-first or LSB-first shifting source to real time counter and LCD controller – IIC — With up to 100 kbps with maximum bus loading; – 100 μs typical wakeup time from stop3 mode multi-master operation; programmable slave address; • Clock Source Options interrupt driven byte-by-byte data transfer; supports – Oscillator (XOSC) — Loop-control Pierce oscillator; broadcast mode and 10-bit addressing crystal or ceramic resonator range of 31.25 kHz to – TPMx — One 6 channel and one 2 channel; selectable input 38.4 kHz or 1 MHz to 16 MHz capture, output compare, or buffered edge or center-aligned – Internal Clock Source (ICS) — Internal clock source PWM on each channel module containing a frequency-locked-loop (FLL) – MTIM — 8-bit counter with match register; four clock controlled by internal or external reference; precision sources with prescaler dividers; can be used for periodic trimming of internal reference allows 0.2% resolution wakeup and 2% deviation over temperature and voltage; supports – RTC — 8-bit modulus counter with binary or decimal based bus frequencies from 1 MHz to 20 MHz. prescaler; three clock sources including one external source; • System Protection can be used for time base, calendar, or task scheduling – COP reset with option to run from dedicated 1 kHz functions internal clock or bus clock – KBI — One keyboard control module capable of supporting – Low-voltage warning with interrupt 8 × 8 keyboard matrix – Low-voltage detection with reset – IRQ — External pin for wakeup from low-power modes – Illegal opcode detection with reset • Input/Output – Illegal address detection with reset – 39, 53, or 69 GPIOs – Flash and RAM protection – 8 KBI and 1 IRQ interrupt with selectable polarity • Development Support – Hysteresis and configurable pullup device on all input pins; – Single-wire background debug interface configurable slew rate and drive strength on all output pins. – Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints • Package Options – 48-pin LQFP, 64-pin LQFP, and 80-pin LQFP in on-chip debug module) Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2009. All rights reserved. Table of Contents 1 2 3 4 5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 2.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .10 2.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .10 2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .11 2.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .12 2.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .17 2.8 External Oscillator (XOSC) Characteristics . . . . . . . . .22 2.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .24 2.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.11.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.11.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . .30 2.11.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.12 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.13 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.14 EMC Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.14.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . .35 2.14.2 Conducted Transient Susceptibility . . . . . . . . . .35 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.1 Device Numbering System . . . . . . . . . . . . . . . . . . . . . .39 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.1 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.1.1 80-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.1.2 64-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . .43 4.1.3 48-pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 List of Figures Figure 1. MC9S08LG32 Series Block Diagram . . . . . . . . . . . . . . 3 Figure 2. 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. 64-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. 48-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. Typical Low-side Drive (sink) characteristics – High Drive (PTxDSn = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 6. Typical Low-side Drive (sink) characteristics – Low Drive (PTxDSn = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Typical High-side Drive (source) characteristics – High Drive (PTxDSn = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. Typical High-side Drive (source) characteristics – Low Drive (PTxDSn = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 9. Typical Run IDD for FBE Mode at 1 MHz. . . . . . . . . . . 19 Figure 10.Typical Run IDD for FBE Mode at 20 MHz . . . . . . . . . 20 Figure 11.Typical Run IDD for FEE Mode at 1 MHz . . . . . . . . . . 20 Figure 12.Typical Run IDD for FEE Mode at 20 MHz . . . . . . . . . 21 Figure 13.Typical Stop2 IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 14.Typical Stop3 IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 15.Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 16.Typical Crystal or Resonator Circuit: Low Range/Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 17.Internal Oscillator Deviation from Trimmed Frequency 25 Figure 18.ADC Input Impedance Equivalency Diagram. . . . . . . 26 Figure 19.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 20.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 21.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 22.Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . . 30 Figure 23.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . 32 Figure 24.SPI Master Timing (CPHA =1) . . . . . . . . . . . . . . . . . . 32 Figure 25.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . 33 Figure 26.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . . 33 Figure 27.4 MHz, Positive Polarity Pins 1 – 41 . . . . . . . . . . . . . 36 Figure 28.4 MHz, Positive Polarity Pins 42 – 80 . . . . . . . . . . . . 36 Figure 29.4 MHz, Negative Polarity Pins 1 – 41. . . . . . . . . . . . . 37 Figure 30.4 MHz, Negative Polarity Pins 42 – 80. . . . . . . . . . . . 37 Figure 31.Device Number Example for Auto Parts. . . . . . . . . . . 39 Figure 32.Device Number Example for IMM Parts. . . . . . . . . . . 39 Figure 33.80-pin LQFP Package Drawing (Case 917A, Doc #98ASS23237W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 34.64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 35.48-pin LQFP Package Drawing (Case 932, Doc #98ASH00962A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 List of Tables Table 1. MC9S08LG32 Series Features by MCU and Package . 4 Table 2. Pin Availability by Package Pin-Count . . . . . . . . . . . . . . 8 Table 3. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 11 Table 5. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 11 Table 6. ESD and Latch-Up Test Conditions . . . . . . . . . . . . . . . 12 Table 7. ESD and Latch-Up Protection Characteristics. . . . . . . 13 Table 8. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 9. Supply Current Characteristics. . . . . . . . . . . . . . . . . . 17 Table 10.Oscillator Electrical Specifications (Temperature Range = –40 °C to 105 °C Ambient) . . . . . . . . . . . . . . . . . . . . . 22 Table 11.ICS Frequency Specifications (Temperature Range = –40 °C to 105 °C Ambient) . . . . . . . . . . . . . . . . . . . . . 24 Table 12.12-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 25 Table 13.12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 14.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 15.TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 16.SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 17.LCD Electricals, 3 V Glass . . . . . . . . . . . . . . . . . . . . . 34 Table 18.Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 19.Radiated Emissions, Electric Field . . . . . . . . . . . . . . . 35 Table 20.Conducted Susceptibility, EFT/B . . . . . . . . . . . . . . . . . 35 Table 21.Susceptibility Performance Classification . . . . . . . . . . 38 Table 22.Device Numbering System . . . . . . . . . . . . . . . . . . . . . 38 Table 23.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 24.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 MC9S08LG32 Series Data Sheet, Rev. 7 2 Freescale Semiconductor PORT A Real Time Counter LCD[40:37]/PTB[7:4] LCD[32:29]/PTB[3:0] RESET/PTC6 BKGD/MS/PTC5 LCD[20:16]/PTC[4:0] (RTC) RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT 8-BIT KEYBOARD INTERRUPT (KBI) RESET COP IRQ LVD SERIAL PERIPHERAL INTERFACE (SPI) KBI[7:0] SS SPSCK MISO MOSI SCL IIC MODULE (IIC) USER FLASH A (LG32 = 16K BYTES) (LG16 = 2K BYTES) 6-CHANNEL TIMER/PWM (TPM2) USER FLASH B (LG32 = 16K BYTES) (LG16 = 16K BYTES) 2-CHANNEL TIMER/PWM (TPM1) SERIAL COMMUNICATIONS INTERFACE (SCI1) USER RAM SDA TPM2CH[5:0] TPMCLK PORT D TMRCLK (MTIM) LCD[7:0]/PTD[7:0] PORT E Modulo Timer HCS08 SYSTEM CONTROL IRQ PORT B BKGD/MS LCD[15:8]/PTE[7:0] TPM1CH[1:0] PORT F BKP EXTAL/PTF7 XTAL/PTF6 TPM2CH3/KBI2/MOSI/PTF5 TPM2CH4/KBI1/MISO/PTF4 TPM2CH5/KBI0/SS/PTF3 ADC14/IRQ/TPM1CH1/SPSCK/PTF2 ADC13/TPM1CH0/RX1/PTF1 ADC12/TPM2CH2/KBI3/TX1/PTF0 PORT G BKGD LCD[44:41]/PTG[7:4] LCD[36:33]/PTG[3:0] PORT H INT ON-CHIP ICE (ICE) and DEBUG MODULE (DBG) TPM2CH4/KBI1/PTH7 ADC15/KBI0/TPM2CH5/PTH6 ADC11/TPM1CH0/KBI3/TX1/PTH5 ADC10/TPM1CH1/KBI2/RX1/PTH4 ADC[9:6]/KBI[7:4]/PTH[3:0] PORT I CPU LCD28/ADC5/TPMCLK/PTA7 LCD27/ADC4/TPM2CH1/KBI7/PTA6 LCD26/ADC3/TPM2CH0/KBI6/PTA5 LCD25/ADC2/RX2/KBI5/PTA4 LCD24/ADC1/TX2/KBI4/PTA3 LCD23/ADC0/SDA/PTA2 LCD22/SCL/PTA1 LCD21/PTA0 PORT C HCS08 CORE SS/SCL/TPM2CH0/PTI5 SPSCK/SDA/TPM2CH1/PTI4 MOSI/TPM2CH2/PTI3 MISO/TPM2CH3/PTI2 TX2/TMRCLK/PTI1 RX2/PTI0 TPMCLK TxD1 RxD1 1984 BYTES SERIAL COMMUNICATIONS INTERFACE (SCI2) INTERNAL CLOCK Source (ICS) TxD2 RxD2 XTAL LOW-POWER OSCILLATOR 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) VLL3_2 VLL3 VLL1 VLL2 VCAP1 EXTAL AD[15:0] LIQUID CRYSTAL DISPLAY DRIVER (LCD) VCAP2 LCD[44:0] VDD VSS VSS2 VOLTAGE REGULATOR VDDA/VREFH VSSA/VREFL Available only on 80-pin package Available only on 64-pin and 80-pin package */Default function out of reset/* Figure 1. MC9S08LG32 Series Block Diagram MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 3 Pin Assignments Table 1. MC9S08LG32 Series Features by MCU and Package Feature Flash size (bytes) MC9S08LG32 MC9S08LG16 32,768 18,432 RAM size (bytes) Pin quantity 1984 80 64 48 64 48 ADC 16 ch 12 ch 9 ch 12 ch 9 ch LCD 8 x 37 4 x 41 8 x 29 4 x 33 8 x 21 4 x 25 8 x 29 4 x 33 8 x 21 4 x 25 53 39 ICE + DBG yes ICS yes IIC yes IRQ yes KBI 8 pin GPIOs 69 39 RTC yes MTIM yes SCI1 yes SCI2 yes SPI yes TPM1 channels 2 TPM2 channels 6 XOSC 1 53 yes Pin Assignments This section shows the pin assignments for the MC9S08LG32 series devices. The priority of functions on a pin is in ascending order from left to right and bottom to top. Another view of pinouts and function priority is given in Table 2. MC9S08LG32 Series Data Sheet, Rev. 7 4 Freescale Semiconductor 80-Pin LQFP 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PTC4/LCD20 PTA0/LCD21 PTG2/LCD35 PTG3/LCD36 PTA1/SCL/LCD22 PTA2/SDA/ADC0/LCD23 PTA3/KBI4/TX2/ADC1/LCD24 PTA4/KBI5/RX2/ADC2/LCD25 PTA5/KBI6/TPM2CH0/ADC3/LCD26 PTA6/KBI7/TPM2CH1/ADC4/LCD27 PTA7/TPMCLK/ADC5/LCD28 PTC5/BKGD/MS PTC6/RESET PTH0/KBI4/ADC6 PTH1/KBI5/ADC7 PTH2KBI6/ADC8 PTH3/KBI7/ADC9 PTH4/RX1/KBI2/TPM1CH1/ADC10 PTH5/TX1/KBI3/TPM1CH0/ADC11 PTF3/SS/KBI0/TPM2CH5 VLL3 PTF5/MOSI/KBI2/TPM2CH3 PTF4/MISO/KBI1/TPM2CH4 PTI5/TPM2CH0/SCL/SS PTI4/TPM2CH1/SDA/SPSCK PTI3/TPM2CH2/MOSI PTI2/TPM2CH3/MISO PTI1/TMRCLK/TX2 PTI0/RX2 PTH7/KBI1/TPM2CH4 VSS VDD PTF7/EXTAL PTF6/XTAL VDDA/VREFH VSSA/VREFL PTH6/TPM2CH5/KBI0/ADC15 PTF2/SPSCK/TPM1CH1/IRQ/ADC14 PTF1/RX1/TPM1CH0/ADC13 PTF0/TX1/KBI3/TPM2CH2/ADC12 PTD7/LCD7 PTD6/LCD6 PTD5/LCD5 PTD4/LCD4 PTD3/LCD3 PTD2/LCD2 PTB3/LCD32 PTB2/LCD31 PTB7/LCD40 PTB6/LCD39 PTB5/LCD38 PTB4/LCD37 PTB1/LCD30 PTB0/LCD29 PTD1/LCD1 PTD0/LCD0 VCAP1 VCAP2 VLL1 VLL2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PTE0/LCD8 PTE1/LCD9 PTE2/LCD10 PTE3/LCD11 PTE4/LCD12 PTE5/LCD13 PTG0/LCD33 PTG1/LCD34 PTG4/LCD41 PTG5/LCD42 PTG6/LCD43 PTG7/LCD44 VLL3_2 VSS2 PTE6/LCD14 PTE7/LCD15 PTC0/LCD16 PTC1/LCD17 PTC2/LCD18 PTC3/LCD19 Pin Assignments Figure 2. 80-Pin LQFP NOTE VREFH/VREFL are internally connected to VDDA/VSSA. MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 5 64-Pin LQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PTC4/LCD20 PTA0/LCD21 PTG2/LCD35 PTG3/LCD36 PTA1/SCL/LCD22 PTA2/SDA/ADC0/LCD23 PTA3/KBI4/TX2/ADC1/LCD24 PTA4/KBI5/RX2/ADC2/LCD25 PTA5/KBI6/TPM2CH0/ADC3/LCD26 PTA6/KBI7/TPM2CH1/ADC4/LCD27 PTA7/TPMCLK/ADC5/LCD28 PTC5/BKGD/MS PTC6/RESET PTH4/RX1/KBI2/TPM1CH1/ADC10 PTH5/TX1/KBI3/TPM1CH0/ADC11 PTF3/SS/KBI0/TPM2CH5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VLL3 PTF5/MOSI/KBI2/TPM2CH3 PTF4/MISO/KBI1/TPM2CH4 PTI5/TPM2CH0/SCL/SS PTI4/TPM2CH1/SDA/SPSCK PTH7/KBI1/TPM2CH4 VSS VDD PTF7/EXTAL PTF6/XTAL VDDA/VREFH VSSA/VREFL PTH6/TPM2CH5/KBI0/ADC15 PTF2/SPSCK/TPM1CH1/IRQ/ADC14 PTF1/RX1/TPM1CH0/ADC13 PTF0/TX1/KBI3/TPM2CH2/ADC12 PTD7/LCD7 PTD6/LCD6 PTD5/LCD5 PTD4/LCD4 PTD3/LCD3 PTD2/LCD2 PTB3/LCD32 PTB2/LCD31 PTB1/LCD30 PTB0/LCD29 PTD1/LCD1 PTD0/LCD0 VCAP1 VCAP2 VLL1 VLL2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PTE0/LCD8 PTE1/LCD9 PTE2/LCD10 PTE3/LCD11 PTE4/LCD12 PTE5/LCD13 PTG0/LCD33 PTG1/LCD34 VLL3_2 VSS2 PTE6/LCD14 PTE7/LCD15 PTC0/LCD16 PTC1/LCD17 PTC2/LCD18 PTC3/LCD19 Pin Assignments Figure 3. 64-Pin LQFP NOTE VREFH/VREFL are internally connected to VDDA/VSSA. MC9S08LG32 Series Data Sheet, Rev. 7 6 Freescale Semiconductor 37 48 PTD7/LCD7 47 1 PTC3/LCD19 PTC2/LCD18 PTC1/LCD17 PTC0/LCD16 PTE7/LCD15 PTE6/LCD14 PTE5/LCD13 PTE4/LCD12 PTE3/LCD11 PTE2/LCD10 PTE1/LCD9 PTE0/LCD8 Pin Assignments 46 45 44 43 42 41 40 39 38 36 PTC4/LCD20 PTD6/LCD6 2 35 PTA0/LCD21 PTD5/LCD5 3 34 PTA1/SCL/LCD22 PTD4/LCD4 4 33 PTA2/SDA/ADC0/LCD23 PTD3/LCD3 5 32 PTA3/KBI4/TX2/ADC1/LCD24 PTD2/LCD2 6 31 PTA4/KBI5/RX2/ADC2/LCD25 PTD1/LCD1 7 30 PTA5/KBI6/TPM2CH0/ADC3/LCD26 PTD0/LCD0 8 29 PTA6/KBI7/TPM2CH1/ADC4/LCD27 9 28 PTA7/TPMCLK/ADC5/LCD28 VCAP2 10 27 PTC5/BKGD/MS VLL1 11 26 PTC6/RESET VCAP1 48-Pin LQFP 25 PTF3/SS/KBI0/TPM2CH5 VLL2 12 14 15 16 17 18 19 20 21 22 23 PTF1/RX1/TPM1CH0/ADC13 PTF2/SPSCKS/TPM1CH1/IRQ/ADC14 VSSA/VREFL VDDA/VREFH PTF6/XTAL PTF7/EXTAL VDD VSS PTF4/MISO/KBI1/TPM2CH4 PTF5/MOSI/KBI2/TPM2CH3 VLL3 PTF0/TX1/KBI3/TPM2CH2/ADC12 24 13 Figure 4. 48-Pin LQFP NOTE VREFH/VREFL are internally connected to VDDA/VSSA. MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 7 Pin Assignments Table 2. Pin Availability by Package Pin-Count Packages <-- Lowest Priority --> Highest 80 64 48 Port Pin Alt 1 Alt 2 Alt 3 Alt 4 1 1 1 PTD7 LCD7 — — — 2 2 2 PTD6 LCD6 — — — 3 3 3 PTD5 LCD5 — — — 4 4 4 PTD4 LCD4 — — — 5 5 5 PTD3 LCD3 — — — 6 6 6 PTD2 LCD2 — — — 7 7 — PTB3 LCD32 — — — 8 8 — PTB2 LCD31 — — — 9 — — PTB7 LCD40 — — — 10 — — PTB6 LCD39 — — — 11 — — PTB5 LCD38 — — — 12 — — PTB4 LCD37 — — — 13 9 — PTB1 LCD30 — — — 14 10 — PTB0 LCD29 — — — 15 11 7 PTD1 LCD1 — — — 16 12 8 PTD0 LCD0 — — — 17 13 9 VCAP1 — — — — 18 14 10 VCAP2 — — — — 19 15 11 VLL1 — — — — 20 16 12 VLL2 — — — — 21 17 13 VLL3 — — — — 22 18 14 PTF5 MOSI KBI2 TPM2CH3 — 23 19 15 PTF4 MISO KBI1 TPM2CH4 — 24 20 — PTI5 TPM2CH0 SCL SS — 25 21 — PTI4 TPM2CH1 SDA SPSCK — 26 — — PTI3 TPM2CH2 MOSI — — 27 — — PTI2 TPM2CH3 MISO — — 28 — — PTI1 TMRCLK TX2 — — 29 — — PTI0 RX2 — — — 30 22 — PTH7 KBI1 TPM2CH4 — — 31 23 16 VSS — — — — 32 24 17 VDD — — — — 33 25 18 PTF7 EXTAL — — — 34 26 19 PTF6 XTAL — — — 35 27 20 VDDA VREFH — — — 36 28 21 VSSA VREFL — — — 37 29 — PTH6 TPM2CH5 KBI0 ADC15 — 38 30 22 PTF2 SPSCK TPM1CH1 IRQ ADC14 MC9S08LG32 Series Data Sheet, Rev. 7 8 Freescale Semiconductor Pin Assignments Table 2. Pin Availability by Package Pin-Count (continued) Packages <-- Lowest Priority --> Highest 80 64 48 Port Pin Alt 1 Alt 2 Alt 3 Alt 4 39 31 23 PTF1 RX1 TPM1CH0 ADC13 — 40 32 24 PTF0 TX1 KBI3 TPM2CH2 ADC12 41 33 25 PTF3 SS KBI0 TPM2CH5 — 42 34 — PTH5 TX1 KBI3 TPM1CH0 ADC11 43 35 — PTH4 RX1 KBI2 TPM1CH1 ADC10 44 — — PTH3 KBI7 ADC9 — — 45 — — PTH2 KBI6 ADC8 — — 46 — — PTH1 KBI5 ADC7 — — 47 — — PTH0 KBI4 ADC6 — — 48 36 26 PTC6 RESET — — — 49 37 27 PTC5 BKGD/MS — — — 50 38 28 PTA7 TPMCLK ADC5 LCD28 — 51 39 29 PTA6 KBI7 TPM2CH1 ADC4 LCD27 52 40 30 PTA5 KBI6 TPM2CH0 ADC3 LCD26 53 41 31 PTA4 KBI5 RX2 ADC2 LCD25 54 42 32 PTA3 KBI4 TX2 ADC1 LCD24 55 43 33 PTA2 SDA ADC0 LCD23 — 56 44 34 PTA1 SCL LCD22 — — 57 45 — PTG3 LCD36 — — — 58 46 — PTG2 LCD35 — — — 59 47 35 PTA0 LCD21 — — — 60 48 36 PTC4 LCD20 — — — 61 49 37 PTC3 LCD19 — — — 62 50 38 PTC2 LCD18 — — — 63 51 39 PTC1 LCD17 — — — 64 52 40 PTC0 LCD16 — — — 65 53 41 PTE7 LCD15 — — — 66 54 42 PTE6 LCD14 — — — 67 55 — VSS2 — — — — 68 56 — VLL3_2 — — — — 69 — — PTG7 LCD44 — — — 70 — — PTG6 LCD43 — — — 71 — — PTG5 LCD42 — — — 72 — — PTG4 LCD41 — — — 73 57 — PTG1 LCD34 — — — 74 58 — PTG0 LCD33 — — — 75 59 43 PTE5 LCD13 — — — 76 60 44 PTE4 LCD12 — — — MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 9 Electrical Characteristics Table 2. Pin Availability by Package Pin-Count (continued) Packages <-- Lowest Priority --> Highest 80 64 48 Port Pin Alt 1 Alt 2 Alt 3 Alt 4 77 61 45 PTE3 LCD11 — — — 78 62 46 PTE2 LCD10 — — — 79 63 47 PTE1 LCD9 — — — 80 64 48 PTE0 LCD8 — — — 2 Electrical Characteristics 2.1 Introduction This section contains electrical and timing specifications for the MC9S08LG32 series of microcontrollers available at the time of publication. 2.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 3. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 2.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry that protects against damage due to high static voltage or electrical fields. However, it is advised that normal precautions should be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. MC9S08LG32 Series Data Sheet, Rev. 7 10 Freescale Semiconductor Electrical Characteristics Table 4. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to +5.8 V Maximum current into VDD IDD 120 mA Digital input voltage VIn –0.3 to VDD + 0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID ±25 ±2 mA Tstg –55 to 150 °C Storage temperature range 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages and use the largest of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in an external power supply going out of regulation. Ensure that the external VDD load will shunt current greater than maximum injection current, this will be of greater risk when the MCU is not consuming power. For instance, If no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). 2.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 5. Thermal Characteristics Rating Symbol Value Unit Operating temperature range (packaged) TA TL to TH –40 to +105 °C Maximum junction temperature TJ 125 °C Thermal resistance Single-layer board 80-pin LQFP 64-pin LQFP 48-pin LQFP θJA 61 71 80 °C/W Thermal resistance Four-layer board 80-pin LQFP 64-pin LQFP 48-pin LQFP θJA 48 52 56 °C/W The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Eqn. 1 MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 11 Electrical Characteristics where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K ÷ (TJ + 273 °C) Eqn. 2 Solving Equation 1 and Equation 2 for K gives: K = PD × (TA + 273 °C) + θJA × (PD)2 Eqn. 3 where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. 2.5 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for automotive grade integrated circuits. During the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless instructed otherwise in the device specification. Table 6. ESD and Latch-Up Test Conditions Model Symbol Value Unit R1 1500 Ω C 100 pF Number of pulses per pin — 3 — Minimum input voltage limit — –2.5 V Maximum input voltage limit — 7.5 V Description Human Body Series resistance Model Storage capacitance Latch-up MC9S08LG32 Series Data Sheet, Rev. 7 12 Freescale Semiconductor Electrical Characteristics Table 7. ESD and Latch-Up Protection Characteristics Rating1 No. 1 2.6 Symbol Min Max Unit 1 Human body model (HBM) VHBM 2500 — V 2 Charge device model (CDM) VCDM 750 — V 3 Latch-up current at TA = 85 °C ILAT ±100 — mA Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. Table 8. DC Characteristics Num C Characteristic 1 — Operating Voltage 2 P Output high voltage — Low Drive (PTxDSn = 0) 5 V, ILoad = –2 mA 3 V, ILoad = –0.6 mA Symbol Min Typ1 Max Unit — 2.7 — 5.5 V VDD – 0.8 VDD – 0.8 — — — — VDD – 0.8 VDD – 0.8 — — — — — — 0.8 0.8 — — 0.8 0.8 VOH Output high voltage — High Drive (PTxDSn = 1) V 5 V, ILoad = –10 mA 3 V, ILoad = –3 mA 3 P Output low voltage — Low Drive (PTxDSn = 0) 5 V, ILoad = 2 mA 3 V, ILoad = 0.6 mA VOL V — Output low voltage — High Drive (PTxDSn = 1) 5 V, ILoad = 10 mA 3 V, ILoad = 3 mA 4 P Output high current — Max total IOH for all ports IOHT — V — 5V 3V 5 C Output high current — Max total IOL for all ports mA 100 60 IOLT — — 5V 3V mA 100 60 6 P Bandgap voltage reference VBG — 1.225 — V 7 P Input high voltage; all digital inputs VIH 0.65 x VDD — — V 8 P Input low voltage; all digital inputs VIL — — 0.35 x VDD V 9 P Input hysteresis; all digital inputs Vhys 0.06 x VDD — — mV |IIn| — 0.1 1 μA |IOZ| — 0.1 1 μA RPU 20 45 65 kΩ RPD 20 45 65 kΩ 10 2 P Input leakage current; input only pins VIn = VDD or VSS 11 P High impedence (off-state) leakage current VIn = VDD or VSS 12 13 P Internal pullup resistors3 P Internal pulldown resistors 4 MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 13 Electrical Characteristics Table 8. DC Characteristics (continued) Num C 14 D DC injection current 5, 6, 7 VIN < VSS, VIN > VDD Characteristic Single pin limit Symbol Min Typ1 Max Unit IIC — — 2 mA — — 25 mA CIn — — 8 pF V Total MCU limit, includes sum of all stressed pins 15 C Input Capacitance, all non-supply pins 16 C RAM retention voltage VRAM 2 — — 17 P POR rearm voltage VPOR 0.9 1.4 2.0 V 18 D POR rearm time tPOR 10 — — μs 19 P Low-voltage detection threshold — high range 3.9 4.0 4.0 4.1 4.1 4.2 2.48 2.54 2.56 2.62 2.64 2.70 4.5 4.6 4.6 4.7 4.7 4.8 4.2 4.3 4.3 4.4 4.4 4.5 2.84 2.90 2.92 2.98 3.00 3.06 2.66 2.72 2.74 2.80 2.82 2.88 VLVD1 VDD falling VDD rising 20 P Low-voltage detection threshold — low range VLVD0 VDD falling VDD rising 21 P Low-voltage warning threshold — high range 1 P Low-voltage warning threshold — low range 1 P Low-voltage warning threshold — low range 0 P Low-voltage inhibit reset/recover hysteresis Vhys 5V 3V 1 2 3 4 5 6 7 V V VLVW0 VDD falling VDD rising 25 V VLVW1 VDD falling VDD rising 24 V VLVW2 P Low-voltage warning threshold — high range 0 VDD falling VDD rising 23 V VLVW3 VDD falling VDD rising 22 V — — mV 100 60 Typical values are measured at 25 °C. Characterized, not tested Measured with VIn = VDD or VSS. Measured with VIn = VSS. Measured with VIn = VDD. All functional non-supply pins, except for PTC6 are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. For instance, if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). MC9S08LG32 Series Data Sheet, Rev. 7 14 Freescale Semiconductor Electrical Characteristics Typical VOL vs. IOL AT VDD = 5V 1.40 Hot (105°C) 0.70 Room (25°C) 0.60 Cold (-40°C) 0.50 VOL (v) VOL (v) 0.80 Typical V OL vs. IOL AT V DD = 3V 0.40 0.30 Hot (105°C) 1.20 Room (25°C) 1.00 Cold (-40°C) 0.80 0.60 0.40 0.20 0.20 0.10 0.00 0.00 0 1 2 3 4 5 6 7 8 9 0 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 IOL (mA) IOL (mA) Figure 5. Typical Low-side Drive (sink) characteristics – High Drive (PTxDSn = 1) Typical VOL vs. IOL AT VDD = 5V 0.90 Typical VOL vs. IOL AT VDD = 3V 0.90 Hot (105°C) 0.80 0.70 Room (25°C) 0.70 Cold (-40°C) Cold (-40°C) 0.60 VOL (v) 0.60 VOL (v) Hot (105°C) 0.80 Room (25°C) 0.50 0.40 0.50 0.40 0.30 0.30 0.20 0.20 0.10 0.10 0.00 0.00 0 1 2 3 4 0 5 1 2 3 IOL (mA) IOL (mA) Figure 6. Typical Low-side Drive (sink) characteristics – Low Drive (PTxDSn = 0) Typical VDD - VOH vs. IOH AT VDD = 5V 0.6 1.2 Hot (105°C) Hot (105°C) 1.0 Room (25°C) VDD - VOH (v) V DD - VOH (v) 0.8 Typical VDD - VOH vs. IOH AT VDD=3V Cold (-40°C) 0.4 0.2 Room (25°C) Cold (-40°C) 0.8 0.6 0.4 0.2 0.0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 IOH (mA) 0.0 0 -1 -2 -3 -4 -5 -6 -7 IOH (mA) -8 -9 -10 -11 -12 -13 Figure 7. Typical High-side Drive (source) characteristics – High Drive (PTxDSn = 1) MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 15 Electrical Characteristics Typical VDD - VOH vs. IOH AT VDD=3V Typical VDD - VOH vs. IOH AT VDD = 5V 1.2 1.2 VDD - VOH (v) Cold (-40°C) 0.8 Room (25°C) 1.0 Room (25°C) 1.0 V DD - VOH (v) Hot (105°C) Hot (105°C) 0.6 0.4 Cold (-40°C) 0.8 0.6 0.4 0.2 0.2 0.0 0.0 0 -1 -2 -3 -4 -5 0 IOH (mA) -1 IOH (mA) -2 -3 Figure 8. Typical High-side Drive (source) characteristics – Low Drive (PTxDSn = 0) MC9S08LG32 Series Data Sheet, Rev. 7 16 Freescale Semiconductor Electrical Characteristics 2.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. Table 9. Supply Current Characteristics Num C 1 C C Parameter Run supply current FEI mode, all modules on Symbol Bus Freq VDD (V) Typ1 Max Unit Temp (°C) RIDD 20 MHz 3 16.38 27.85 mA –40 °C to 85 °C C 1 MHz 1.67 C P 20 MHz 5 16.55 P C 1 MHz 1.77 C 2 T T Run supply current FEI mode, all modules off RIDD T 20 MHz 3 1 MHz 11.9 1.16 T T 20 MHz 5 12.68 T T 1 MHz 1.4 T 3 T T Wait mode supply current FEI mode, all modules off WIDD T 20 MHz 3 1 MHz 7.9 0.88 T P 20 MHz 5 8.13 P T 1 MHz 1.12 T 4 C Stop2 mode supply current S2IDD n/a 3 1.1 C 5 1.2 P C C –40 °C to105 °C 2.84 –40 °C to 85 °C 2.87 –40 °C to105 °C 28.14 mA –40 °C to105 °C 3.01 –40 °C to 85 °C 3.05 –40 °C to105 °C 20.25 mA P S3IDD n/a 3 1.2 –40 °C to105 °C 1.95 –40 °C to 85 °C 1.98 –40 °C to105 °C 21.56 mA 1.32 P –40 °C to 85 °C 23.12 –40 °C to105 °C 2.39 –40 °C to 85 °C 2.41 –40 °C to105 °C 13.42 mA –40 °C to 85 °C 13.59 –40 °C to105 °C 1.49 –40 °C to 85 °C 1.51 –40 °C to105 °C 13.81 mA –40 °C to 85 °C 13.98 –40 °C to105 °C 1.91 –40 °C to 85 °C 1.94 –40 °C to105 °C 16.0 μA 18.7 22.4 25.5 63.9 –40 °C to 85 °C –40 °C to105 °C μA –40 °C to 85 °C –40 °C to105 °C μA –40 °C to 85 °C –40 °C to105 °C 56.2 5 –40 °C to 85 °C 21.72 46.1 Stop3 mode supply current No clocks active –40 °C to 85 °C 28.35 39.0 P 5 28.05 μA –40 °C to 85 °C –40 °C to105 °C MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 17 Electrical Characteristics Table 9. Supply Current Characteristics (continued) Num C 6 T Symbol Bus Freq VDD (V) Typ1 Max Unit Temp (°C) — n/a 3 210 — nA –40 °C to 105 °C RTC using low power crystal oscillator 4.25 — μA LCD2 with rbias (Low Gain) 1.23 — LCD2 with rbias (High Gain) 184 — 4.053 — 210 — nA RTC using low power crystal oscillator 4.22 — μA LCD2 with rbias (Low Gain) 1.53 — LCD2 with rbias (High Gain) 324 — 7.123 — 210 — nA RTC using low power crystal oscillator 4.75 — μA LCD2 with rbias (Low Gain) 1.23 — LCD2 with rbias (High Gain) 184 — 4.353 — 230 — nA RTC using low power crystal oscillator 4.74 — μA LCD2 with rbias (Low Gain) 1.53 — LCD2 with rbias (High Gain) 324 — 7.493 — Parameter Stop2 adders: RTC using LPO LCD2 with Cpump RTC using LPO 5 LCD2 with Cpump 7 T Stop3 adders: RTC using LPO — n/a 3 LCD2 with Cpump RTC using LPO LCD2 with Cpump 5 –40 °C to 85 °C –40 °C to 105 °C –40 °C to 85 °C –40 °C to 105 °C –40 °C to 85 °C –40 °C to 105 °C –40 °C to 85 °C MC9S08LG32 Series Data Sheet, Rev. 7 18 Freescale Semiconductor Electrical Characteristics Table 9. Supply Current Characteristics (continued) Num C 8 T Symbol Bus Freq VDD (V) Typ1 Max Unit Temp (°C) — n/a 3 4.58 — μA –40 °C to 105 °C IREFSTEN = 1 71.7 — LVD 94.35 — 4.61 — IREFSTEN = 1 71.69 — LVD 107.34 — Parameter Stop3 adders: EREFSTEN = 1 EREFSTEN = 1 5 μA Typical values are measured at 25 °C. Characterized, not tested. LCD configured for Charge Pump Enabled VLL3 connected to VDD.. 3 This does not include current required for 32 kHz oscillator. 4 This is the maximum current when all LCD inputs/outputs are used. 1 2 IDD VDD Figure 9. Typical Run IDD for FBE Mode at 1 MHz MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 19 Electrical Characteristics IDD VDD Figure 10. Typical Run IDD for FBE Mode at 20 MHz IDD VDD Figure 11. Typical Run IDD for FEE Mode at 1 MHz MC9S08LG32 Series Data Sheet, Rev. 7 20 Freescale Semiconductor Electrical Characteristics IDD VDD Figure 12. Typical Run IDD for FEE Mode at 20 MHz IDD VDD Figure 13. Typical Stop2 IDD MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 21 Electrical Characteristics IDD VDD Figure 14. Typical Stop3 IDD 2.8 External Oscillator (XOSC) Characteristics Table 10. Oscillator Electrical Specifications (Temperature Range = –40 °C to 105 °C Ambient) Num C 1 D 2 D Characteristic Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) • Low range (RANGE = 0) • High range (RANGE = 1) FEE or FBE mode2 • High range (RANGE = 1, HGO = 1) BLPE mode • High range (RANGE = 1, HGO = 0) BLPE mode Load capacitors Symbol Min Typ1 Max Unit flo fhi 32 1 1 1 — — — — 38.4 5 16 8 kHz MHz MHz MHz fhi-hgo fhi-lp C1 C2 See crystal or resonator manufacturer’s recommendation. MC9S08LG32 Series Data Sheet, Rev. 7 22 Freescale Semiconductor Electrical Characteristics Table 10. Oscillator Electrical Specifications (Temperature Range = –40 °C to 105 °C Ambient) (continued) Num C 3 D 4 5 D D Characteristic Symbol Feedback resistor • Low range (32 kHz to 100 kHz) • High range (1 MHz to 16 MHz) RF Series resistor • Low range, low gain (RANGE = 0, HGO = 0) • Low range, high gain (RANGE = 0, HGO = 1) RS Series resistor • High range, low gain (RANGE = 1, HGO = 0) • High range, high gain (RANGE = 1, HGO = 1) RS 7 T D Typ1 Max — — 10 1 — — Unit MΩ kΩ 0 100 ≥8 MHz 4 MHz 1 MHz 6 Min Crystal start-up time3, 4 • Low range (HGO = 0) • Low range (HGO = 1) • High range (HG0 = 0)5 • High range (HG0 = 1)5 kΩ — — — 0 0 0 0 10 20 — — — — 500 3570 4 4 — — — — 0.03125 0 — — 5 40 ms tCSTL-LP tCSTL-HGO tCSTH-LP tCSTH-HGO Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) • FEE or FBE mode2 • BLPE mode fextal MHz Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value. When ICS is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of 31.25 kHz to 39.0625 kHz. 3 This parameter is characterized and not tested on each device. 4 Proper PC board layout procedures must be followed to achieve specifications. 5 4 MHz crystal 1 2 XOSC EXTAL XTAL RF C1 RS Crystal or Resonator C2 Figure 15. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 23 Electrical Characteristics XOSC EXTAL XTAL Crystal or Resonator Figure 16. Typical Crystal or Resonator Circuit: Low Range/Low Power 2.9 Internal Clock Source (ICS) Characteristics Table 11. ICS Frequency Specifications (Temperature Range = –40 °C to 105 °C Ambient) Num C Characteristic Symbol Min Typ1 Max Unit 1 P Average internal reference frequency — factory trimmed at VDD = 5.0 V and temperature = 25 °C fint_ft — 32.768 — kHz 2 C Average internal reference frequency — user trimmed fint_t 31.25 — 39.0625 kHz 3 C Internal reference start-up time tIRST — 60 100 μs 4 P DCO output frequency range — Low range (DRS = 00) trimmed2 Mid range (DRS = 01) fdco_t 16 — 20 MHz 32 — 40 — 19.92 — — 39.85 — P 5 P P frequency2 DCO output Reference = 32768 Hz and DMX32 = 1 Low range (DRS = 00) fdco_DMX32 Mid range (DRS = 01) MHz 6 C Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM)3 Δfdco_res_t — ±0.1 ±0.2 %fdco 7 C Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM)3 Δfdco_res_t — ±0.2 ±0.4 %fdco 8 C Total deviation of trimmed DCO output frequency over voltage and temperature3 Δfdco_t — –1.0 to +0.5 ±2 %fdco 9 C Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0 °C to 70 °C3 Δfdco_t — ±0.5 ±1 %fdco 10 C FLL acquisition time3, 4 tAcquire — — 1 mS 11 C Long term jitter of DCO output clock (averaged over 2 ms interval)5 CJitter — 0.02 0.2 %fdco Data in Typical column was characterized at 5.0 V, 25 °C or is typical recommended value. The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 This parameter is characterized and not tested on each device. 4 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 5 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in the crystal oscillator frequency increase the CJitter percentage for a given interval. 1 2 MC9S08LG32 Series Data Sheet, Rev. 7 24 Freescale Semiconductor Electrical Characteristics 65.00 60.00 ICS Frequency (khz) 55.00 50.00 45.00 40.00 35.00 30.00 25.00 '0 00 0 '0 00 00 00 0 '0 11 00 01 1 '0 10 01 10 0 '0 01 01 11 1 '0 01 10 00 0 '0 00 10 01 0 '0 11 10 10 1 '0 10 11 11 0 '0 10 11 00 1 '1 01 00 01 0 '1 00 00 10 0 '1 11 00 11 1 '1 11 01 00 0 '1 10 01 01 1 '1 01 10 10 0 '1 00 10 11 1 '1 00 10 00 1 '1 11 11 01 0 '1 10 11 10 10 11 1 20.00 ICS Trim values -40°C 25°C 110°C Figure 17. Internal Oscillator Deviation from Trimmed Frequency 2.10 ADC Characteristics Table 12. 12-bit ADC Operating Conditions Symb Min Typ1 Max Unit Comment Absolute VDDAD 2.7 — 5.5 V — Delta to VDD (VDD – VDDAD)2 ΔVDDAD –100 0 +100 mV — Delta to VSS (VSS – VSSAD)2 ΔVSSAD –100 0 +100 mV — Ref Voltage High — VREFH — — — V VREFH shorted to VDDAD Ref Voltage Low — VREFL — — — V VREFLshorted to VSSAD Input Voltage — VADIN VREFL — VREFH V — Input Capacitance — CADIN — 4.5 5.5 pF — Characteristic Supply voltage Ground voltage Conditions MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 25 Electrical Characteristics Table 12. 12-bit ADC Operating Conditions (continued) Conditions Symb Min Typ1 Max Unit Comment — RADIN — 5 7 kΩ — kΩ External to MCU — — — — 2 5 10-bit mode fADCK > 4MHz fADCK < 4MHz — — — — 5 10 8-bit mode (all valid fADCK) — — 10 0.4 — 8.0 MHz — 0.4 — 4.0 Characteristic Input Resistance Analog Source Resistance ADC Conversion Clock Freq. 12-bit mode fADCK > 4MHz fADCK < 4MHz RAS High Speed (ADLPC = 0) fADCK Low Power (ADLPC = 1) Typical values assume VDDAD = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. 1 SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZAS RAS VAS + – CAS ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + VADIN – RADIN INPUT PIN INPUT PIN RADIN RADIN INPUT PIN CADIN Figure 18. ADC Input Impedance Equivalency Diagram MC9S08LG32 Series Data Sheet, Rev. 7 26 Freescale Semiconductor Electrical Characteristics Table 13. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) Num C Characteristic Conditions Symb Min Typ1 Max Unit Comment 1 T Supply Current ADLPC = 1 ADLSMP = 1 ADCO = 1 — IDDAD — 195 — μA — 2 T Supply Current ADLPC = 1 ADLSMP = 0 ADCO = 1 — IDDAD — 347 — μA — 3 T Supply Current ADLPC = 0 ADLSMP = 1 ADCO = 1 — IDDAD — 407 — μA — 4 P Supply Current ADLPC = 0 ADLSMP = 0 ADCO = 1 — IDDAD — 0.755 1 mA — 5 — Supply Current Stop, Reset, Module Off IDDAD 0.011 1 μA — 6 P ADC Asynchronous Clock Source High Speed (ADLPC=0) fADACK 2 3.3 5 MHz 1.25 2 3.3 tADACK = 1/fADACK — 20 — — 40 — ADCK cycles — 3.5 — — 23.5 — See ADC chapter in the LG32 Reference Manual for conversion time variances — ±3.0 — 10-bit mode — ±1 ±2.5 8-bit mode — ±0.5 ±1 — ±1.75 — 10-bit mode3 — ±0.5 ±1.0 8-bit mode3 — ±0.3 ±0.5 — ±1.5 — 10-bit mode — ±0.5 ±1 8-bit mode — ±0.3 ±0.5 — ±1.5 — 10-bit mode — ±0.5 ±1.5 8-bit mode — ±0.5 ±0.5 7 8 C C Low Power (ADLPC=1) Conversion Time (Including sample time) Short sample (ADLSMP=0) Long sample (ADLSMP=1) Sample Time Short sample (ADLSMP=0) tADC tADS Long sample (ADLSMP=1) 9 T P Total Unadjusted Error T 10 T P Differential Non-Linearity T 11 T P Integral Non-Linearity T 12 T P Zero-Scale Error T 12-bit mode 12-bit mode 12-bit mode 12-bit mode ETUE DNL INL EZS ADCK cycles LSB2 Includes quantization LSB2 LSB2 LSB2 VADIN = VSSAD MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 27 Electrical Characteristics Table 13. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued) Num C Characteristic 13 T Full-Scale Error P T 14 15 16 17 D D C C Quantization Error Input Leakage Error Temp Sensor Slope Temp Sensor Voltage Symb Min Typ1 Max Unit Comment EFS — ±1 — LSB2 VADIN = VDDAD 10-bit mode — ±0.5 ±1 8-bit mode — ±0.5 ±0.5 — –1 to 0 — LSB2 — 10-bit mode — — ±0.5 8-bit mode — — ±0.5 — ±1 — LSB2 10-bit mode — ±0.2 ±2.5 Pad leakage4 * RAS 8-bit mode — ±0.1 ±1 — 1.646 — mV/°C — — 1.769 — — 701.2 — mV — Conditions 12-bit mode 12-bit mode 12-bit mode –40 °C to 25 °C EQ EIL m 25 °C to 125°C 25 °C VTEMP25 Typical values assume VDDAD = 5.0 V, Temp = 25 °C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (V N REFH – VREFL)/2 3 Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes 4 Based on input pad leakage current. Refer to pad electricals. 1 MC9S08LG32 Series Data Sheet, Rev. 7 28 Freescale Semiconductor Electrical Characteristics 2.11 AC Characteristics This section describes timing characteristics for each peripheral system. 2.11.1 Control Timing Table 14. Control Timing Num C 1 D 2 D 3 4 5 6 Typ1 Max Unit Bus frequency (tcyc = 1/fBus) fBus dc — 20 MHz Internal low power oscillator period tLPO 700 — 1300 μs textrst 100 — — ns 2 D External reset pulse width 4 D Reset low drive trstdrv 66 x tcyc — — ns 5 D BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes tMSSU 500 — — ns 6 D BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 tMSH 100 — — μs 7 D IRQ pulse width Asynchronous path2 Synchronous path4 tILIH tIHIL 100 1.5 x tcyc — — — — Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 tILIH tIHIL 100 1.5 x tcyc — — — — Port rise and fall time — (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise tFall — — 3 30 — — 9 2 Min 3 8 1 Symbol Rating D C ns ns ns Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 105 °C. Except for LCD pins in Open Drain mode. textrst RESET PIN Figure 19. Reset Timing MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 29 Electrical Characteristics tIHIL IRQ/KBIPx IRQ/KBIPx tILIH Figure 20. IRQ/KBIPx Timing 2.11.2 TPM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 15. TPM Input Timing No. C 1 D 2 Function Symbol Min Max Unit External clock frequency fTCLK 0 fBus/4 Hz D External clock period tTCLK 4 — tcyc 3 D External clock high time tclkh 1.5 — tcyc 4 D External clock low time tclkl 1.5 — tcyc 5 D Input capture pulse width tICPW 1.5 — tcyc tTCLK tclkh TPMCLK tclkl Figure 21. Timer External Clock tICPW TPMCHn TPMCHn tICPW Figure 22. Timer Input Capture Pulse MC9S08LG32 Series Data Sheet, Rev. 7 30 Freescale Semiconductor Electrical Characteristics 2.11.3 SPI Timing Table 16 and Figure 23 through Figure 26 describe the timing requirements for the SPI system. Table 16. SPI Timing No. C — D 1 D 2 D 3 D 4 D 5 D 6 D 7 Function Operating frequency Master Slave Symbol Min Max fBus/2048 0 fBus/2 fBus/4 2 4 2048 — tcyc tcyc 1/2 1 — — tSPSCK tcyc 1/2 1 — — tSPSCK tcyc tcyc – 30 tcyc – 30 1024 tcyc — ns ns 15 15 — — ns ns 0 25 — — ns ns Hz fop SPSCK period Master Slave Unit tSPSCK Enable lead time Master Slave tLead Enable lag time Master Slave tLag Clock (SPSCK) high or low time Master Slave tWSPSCK Data setup time (inputs) Master Slave tSU Data hold time (inputs) Master Slave tHI D Slave access time ta — 1 tcyc 8 D Slave MISO disable time tdis — 1 tcyc 9 D Data valid (after SPSCK edge) Master Slave — — 25 25 ns ns 10 D 0 0 — — ns ns 11 D 12 D Data hold time (outputs) Master Slave tv tHO Rise time Input Output tRI tRO — — tcyc – 25 25 ns ns Fall time Input Output tFI tFO — — tcyc – 25 25 ns ns MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 31 Electrical Characteristics SS1 (OUTPUT) 1 2 11 3 4 SPSCK (CPOL = 0) (OUTPUT) 4 12 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MS BIN2 BIT 6 . . . 1 LSB IN 9 9 MOSI (OUTPUT) 10 BIT 6 . . . 1 MSB OUT2 LSB OUT NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 23. SPI Master Timing (CPHA = 0) SS1 (OUTPUT) 1 2 12 11 11 12 3 SPSCK (CPOL = 0) (OUTPUT) 4 4 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN2 9 MOSI (OUTPUT) PORT DATA BIT 6 . . . 1 LSB IN 10 MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 24. SPI Master Timing (CPHA =1) MC9S08LG32 Series Data Sheet, Rev. 7 32 Freescale Semiconductor Electrical Characteristics SS (INPUT) 1 12 11 11 12 3 SPSCK (CPOL = 0) (INPUT) 2 4 4 SPSCK (CPOL = 1) (INPUT) 8 7 MISO (OUTPUT) 9 SLAVE LSB OUT SEE NOTE 1 6 5 MOSI (INPUT) BIT 6 . . . 1 MSB OUT SLAVE 10 10 BIT 6 . . . 1 MSB IN LSB IN NOTE: 1. Not defined but normally MSB of character just received. Figure 25. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 3 2 12 11 11 12 SPSCK (CPOL = 0) (INPUT) 4 4 SPSCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) 10 SEE NOTE 1 SLAVE 7 MOSI (INPUT) MSB OUT BIT 6 . . . 1 c SLAVE LSB OUT 6 o MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received Figure 26. SPI Slave Timing (CPHA = 1) MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 33 Electrical Characteristics 2.12 LCD Specifications Table 17. LCD Electricals, 3 V Glass C Characteristic Symbol Min Typ Max Units D VLL3 Supply Voltage VLL3 2.7 — 5.5 V D LCD Frame Frequency fFrame 28 30 64 Hz D LCD Charge Pump Capacitance CLCD — 100 100 pF D LCD Bypass Capacitance CBYLCD — 100 100 D LCD Glass Capacitance Cglass — 2000 8000 2.13 Flash Specifications This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section. Table 18. Flash Characteristics C Characteristic Symbol Min Typical Max Unit D Supply voltage for program/erase –40 °C to 85 °C Vprog/erase 2.7 5.5 V D Supply voltage for read operation VRead 2.7 5.5 V fFCLK 150 200 kHz 5 6.67 μs frequency1 D Internal FCLK D Internal FCLK period (1/FCLK) tFcyc C Byte program time (random location)2 tprog 9 tFcyc tBurst 4 tFcyc mode)2 C Byte program time (burst C Page erase time2 tPage 4000 tFcyc C Mass erase time2 tMass 20,000 tFcyc D Byte program current3 3 D Page erase current C Program/erase endurance4 TL to TH = –40 °C to + 85 °C T = 25 °C C Data retention5 RIDDBP — 4 — mA RIDDPE — 6 — mA 10,000 — 100,000 — — cycles 15 100 — years tD_ret 1 The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with VDD = 5.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for flash was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25 °C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory. 2 MC9S08LG32 Series Data Sheet, Rev. 7 34 Freescale Semiconductor Electrical Characteristics 2.14 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 2.14.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. Table 19. Radiated Emissions, Electric Field Parameter Radiated emissions, electric field 1 Symbol Conditions Frequency fOSC/fBUS VRE_TEM VDD = 5.5 TA = +25 oC Package type = 80 LQFP 0.15 – 50 MHz 4 MHz crystal 16 MHz bus 50 – 150 MHz Level1 (Max) Unit 10 dBμV 14 150 – 500 MHz 8 500 – 1000 MHz 5 IEC Level L — SAE Level 2 — Data based on qualification test results. 2.14.2 Conducted Transient Susceptibility Microcontroller transient conducted susceptibility is measured in accordance with an internal Freescale test method. The measurement is performed with the microcontroller installed on a custom EMC evaluation board and running specialized EMC test software designed in compliance with the test method. The conducted susceptibility is determined by injecting the transient susceptibility signal on each pin of the microcontroller. The transient waveform and injection methodology is based on IEC 61000-4-4 (EFT/B). The transient voltage required to cause performance degradation on any pin in the tested configuration is greater than or equal to the reported levels unless otherwise indicated by footnotes below Table 20. Table 20. Conducted Susceptibility, EFT/B Parameter Conducted susceptibility, electrical fast transient/burst (EFT/B) 1 2 Symbol VCS_EFT Conditions fOSC/fBUS 4 kHz crystal VDD = 5.5 4 MHz bus TA = +25 oC Package type = 80-pin LQFP Result Amplitude1 (Min) A B C D >4.02 >4.03 >4.04 >4.0 Unit kV Data based on qualification test results. Not tested in production. Exceptions as covered in footnotes 3 and 4. MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 35 Electrical Characteristics 3 Except pins PHT1, PTH2, PTH3, PTH4, PTH5. See figures below for values. Except pins PTF3, PTH5, PTH4, PHT0, Reset, and BKGD. See figures below for values. 4 Individual performance of each pin is shown in Figure 27, Figure 28, Figure 29, and Figure 30. Figure 27. 4 MHz, Positive Polarity Pins 1 – 41 Note: RESET retested with 0.1 μF capacitor from pin to ground is Class A compliant as shown by 48*. Figure 28. 4 MHz, Positive Polarity Pins 42 – 80 MC9S08LG32 Series Data Sheet, Rev. 7 36 Freescale Semiconductor Electrical Characteristics Figure 29. 4 MHz, Negative Polarity Pins 1 – 41 Note: RESET retested with 0.1 μF capacitor from pin to ground is Class A compliant as shown by 48*. Figure 30. 4 MHz, Negative Polarity Pins 42 – 80 MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 37 Ordering Information The susceptibility performance classification is described in Table 21. Table 21. Susceptibility Performance Classification Result 3 Performance Criteria A No failure The MCU performs as designed during and after exposure. B Self-recovering failure C Soft failure The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the RESET pin is asserted. D Hard failure The MCU does not perform as designed during exposure. The MCU does not return to normal operation until exposure is removed and the power to the MCU is cycled. E Damage The MCU does not perform as designed during and after exposure. The MCU cannot be returned to proper operation due to physical damage or other permanent performance degradation. The MCU does not perform as designed during exposure. The MCU returns automatically to normal operation after exposure is removed. Ordering Information This section contains ordering information for MC9S08LG32 and MC9S08LG16 devices. Table 22. Device Numbering System Device Number1 Memory Temperature Range (°C) FLASH RAM LCD Mode Operation Available Packages2 Charge Pump 80-pin LQFP Auto S9S08LG32J0CLK 32 KB 1984 -40 °C to +85 °C S9S08LG32J0CLH 64-pin LQFP S9S08LG32J0CLF S9S08LG32J0VLK 48-pin LQFP 32 KB 1984 -40 °C to +105 °C Register Bias 80-pin LQFP S9S08LG32J0VLH 64-pin LQFP S9S08LG32J0VLF 48-pin LQFP S9S08LG16J0VLH 18 KB 1984 64-pin LQFP S9S08LG16J0VLF 48-pin LQFP IMM MC9S08LG32CLK 32 KB 1984 -40 °C to + 85 °C Charge Pump 80-pin LQFP MC9S08LG32CLH 64-pin LQFP MC9S08LG32CLF 48-pin LQFP MC9S08LG16CLH 18 KB 1984 MC9S08LG16CLF 64-pin LQFP 48-pin LQFP 1 See the MC9S08LG32 Reference Manual (document MC9S08LG32RM), for a complete description of modules included on each device. 2 See Table 23 for package information. MC9S08LG32 Series Data Sheet, Rev. 7 38 Freescale Semiconductor Package Information 3.1 Device Numbering System Example of the device numbering system: S 9 S08 LG 32 J0 X XX Package designator (see Table 23) Temperature range (C = –40 °C to 85 °C) (V = –40 °C to 105 °C) Maskset Identifier Suffix (First digit usually references wafer fab Second digit usually differentiates mask rev) Status/Partnumber Type (S = Maskset specific partnumber) Memory (9 = FLASH-based) Core Family Approximate Flash size in KB Figure 31. Device Number Example for Auto Parts MC 9 S08 LG 32 C XX Status (MC = Fully Qualified) Package designator (see Table 23) Temperature range (C = –40 °C to 85 °C) Memory (9 = FLASH-based) Core Approximate Flash size in KB Family Figure 32. Device Number Example for IMM Parts 4 Package Information Table 23. Package Descriptions Pin Count 4.1 Package Type Abbreviation Designator Case No. Document No. 80 Low Quad Flat Package LQFP LK 917A 98ASS23237W 64 Low Quad Flat Package LQFP LH 840F 98ASS23234W 48 Low Quad Flat Package LQFP LF 932 98ASH00962A Mechanical Drawings The following pages are mechanical drawings for the packages described in Table 23. For the latest available drawings please visit our web site (http://www.freescale.com) and enter the package’s document number into the keyword search box. MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 39 Package Information 4.1.1 80-pin LQFP MC9S08LG32 Series Data Sheet, Rev. 7 40 Freescale Semiconductor Package Information MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 41 Package Information Figure 33. 80-pin LQFP Package Drawing (Case 917A, Doc #98ASS23237W) MC9S08LG32 Series Data Sheet, Rev. 7 42 Freescale Semiconductor Package Information 4.1.2 64-pin LQFP MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 43 Package Information MC9S08LG32 Series Data Sheet, Rev. 7 44 Freescale Semiconductor Package Information Figure 34. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W) MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 45 Package Information 4.1.3 48-pin LQFP MC9S08LG32 Series Data Sheet, Rev. 7 46 Freescale Semiconductor Package Information Figure 35. 48-pin LQFP Package Drawing (Case 932, Doc #98ASH00962A) MC9S08LG32 Series Data Sheet, Rev. 7 Freescale Semiconductor 47 Revision History 5 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web are the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com The following revision history table summarizes changes contained in this document. Table 24. Revision History Revision Date Description of Changes 1 8/2008 First Initial release. 2 9/2008 Second Initial Release. 3 11/2008 Alpha Customer Release. 4 2/2009 Launch Release. 5 4/2009 Added EMC Radiated Emission and Transient Susceptibility data in Table 19 and Table 20. 6 4/2009 Updated EMC performance data. 7 8/2009 Updated auto part numbers, changed TCLK, T0CH0, T0CH1, T1CH0, T1CH1, T1CH2, T1CH3, T1CH3, T1CH4, and T1CH5 to TPMCLK, TPM0CH0, TPM0CH1,TPM1CH0, TPM1CH1, TPM1CH2, TPM1CH3, TPM1CH4, and TPM1CH5, and changed the maximum LCD frame frequency to 64 Hz. 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