Freescale Semiconductor Data Sheet: Technical Data Document Number: MC9S08LL16 Rev. 6, 10/2010 An Energy Efficient Solution by Freescale MC9S08LL16 Series Covers: MC9S08LL16 and MC9S08LL8 Features • 8-Bit HCS08 Central Processor Unit (CPU) – Up to 20-MHz CPU at 3.6V to 1.8V across temperature range of -40°C to 85°C – HC08 instruction set with added BGND instruction – Support for up to 32 interrupt/reset sources • On-Chip Memory – Dual Array FLASH read/program/erase over full operating voltage and temperature – Random-access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and FLASH contents • Power-Saving Modes – Two low power stop modes – Reduced power wait mode – Low power run and wait modes allow peripherals to run while voltage regulator is in standby – Peripheral clock gating register can disable clocks to unused modules, thereby reducing currents. – Very low power external oscillator that can be used in stop2 or stop3 modes to provide accurate clock source to real time counter – 6 usec typical wake up time from stop3 mode • Clock Source Options – Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz – Internal Clock Source (ICS) — Internal clock source module containing a frequency-locked-loop (FLL) controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation over temperature and voltage; supports bus frequencies from 1MHz to 10 MHz. • System Protection – Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock – Low-Voltage Warning with interrupt – Low-Voltage Detection with reset or interrupt – Illegal opcode and illegal address detection with reset – Flash block protection • Development Support – Single-wire background debug interface – Breakpoint capability to allow single breakpoint setting during in-circuit debugging (plus two more breakpoints in on-chip debug module) 64-LQFP Case 840F 48-LQFP Case 932 48-QFN 1314 – On-chip in-circuit emulator (ICE) debug module containing three comparators and nine trigger modes. Eight deep FIFO for storing change-of-flow addresses and event-only data. Debug module supports both tag and force breakpoints • Peripherals – LCD — 4x28 or 8x24 LCD driver with internal charge pump and option to provide an internally regulated LCD reference that can be trimmed for contrast control. – ADC — 8-channel, 12-bit resolution; 2.5 s conversion time; automatic compare function; temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6V to 1.8V – ACMP — Analog comparator with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to TPM module; operation in stop3 – SCI — Full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake up on active edge – SPI— Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MSB-first or LSB-first shifting – IIC — IIC with up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 10-bit addressing – TPMx — Two 2-channel (TPM1 and TPM2); Selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel; – TOD— (Time Of Day) 8-bit quarter second counter with match register; External clock source for precise time base, time-of-day, calendar or task scheduling functions; Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components. • Input/Output – 38 GPIOs, 2 output-only pins – 8 KBI interrupts with selectable polarity – Hysteresis and configurable pull up device on all input pins; Configurable slew rate and drive strength on all output pins. • Package Options – 64-LQFP, 48-LQFP and 48-QFN Table of Contents 1 2 3 Devices in the MC9S08LL16 Series . . . . . . . . . . . . . . 4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . 9 3.3 Absolute Maximum Ratings. . . . . . . . . . . . . . . . 10 3.4 Thermal Characteristics. . . . . . . . . . . . . . . . . . . 11 3.5 ESD Protection and Latch-Up Immunity . . . . . . 12 3.6 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . 13 3.7 Supply Current Characteristics . . . . . . . . . . . . . 25 3.8 External Oscillator (XOSCVLP) Characteristics 27 3.9 Internal Clock Source (ICS) Characteristics . . . 28 4 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . .30 3.10.1Control Timing. . . . . . . . . . . . . . . . . . . . . .30 3.10.2TPM Module Timing . . . . . . . . . . . . . . . . .31 3.10.3SPI Timing . . . . . . . . . . . . . . . . . . . . . . . .32 3.11 Analog Comparator (ACMP) Electricals . . . . . . .35 3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . .35 3.13 LCD Specifications . . . . . . . . . . . . . . . . . . . . . . .39 3.14 Flash Specifications . . . . . . . . . . . . . . . . . . . . . .39 3.15 EMC Performance . . . . . . . . . . . . . . . . . . . . . . .40 3.15.1Radiated Emissions . . . . . . . . . . . . . . . . .40 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .41 4.1 Device Numbering System . . . . . . . . . . . . . . . . .41 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com/ The following revision history table summarizes changes contained in this document. Rev Date 1 9/2008 Initial Release. 2 10/2008 Updated electrical characteristics. 01/2009 Corrected 48-Pin QFN/LQFP pinouts for pins 29, 30, 32, and 32 in Figure 3. Extracted Stop Mode Adders from the Supply Current table and created a Separate table for the data (See Table 10). Added missing power consumption parameters in Supply Current Characteristics (Table 9). 3 Description of Changes Completed all the TBDs. Changed VDDAD to VDDA, VSSAD to VSSA, IDDAD to IDDA. Corrected the data in the Table 8, and added |IInT|. Completed the Figure in the 4 07/21/2009 Section 3.6, “DC Characteristics.” Corrected RIDD in FEI mode with all modules on, WIDD at 8 MHz, FEI mode with all modules off, S2IDD, S3IDD; added ApS3IDD in the Table 9. Corrected ETUE, DNL, INL, EZS, EFS, EQ, and EIL in the Table 18. 5 10/13/2009 Updated RPU/RPD data in the Table 8. Added Figure 5. 6 10/27/2010 Changed the Max. of RPU/RPD at PTA[4:5], PTD[0:77] and PTE[0:7] to 69.5 kin the Table 8. MC9S08LL16 Series MCU Data Sheet, Rev. 6 2 Freescale Semiconductor Related Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual (MC9S08LL16RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 3 Devices in the MC9S08LL16 Series 1 Devices in the MC9S08LL16 Series Table 1 summarizes the feature set available in the MC9S08LL16 series of MCUs. t Table 1. MC9S08LL16 Series Features by MCU and Package Feature Package FLASH 1 MC9S08LL16 64-pin LQFP MC9S08LL8 48-pin QFN/LQFP 48-pin QFN/LQFP 10,240 (8K and 2K arrays) 16,384 (Dual 8K Arrays) RAM 2080 2080 2080 ACMP yes yes yes ADC 8-ch 8-ch 8-ch IIC yes yes yes IRQ yes yes yes KBI 8 8 8 SCI yes yes yes SPI yes yes yes TPM1 2-ch 2-ch 2-ch TPM2 2-ch - - TOD Yes Yes Yes LCD 8x24 4x28 8x16 4x20 8x16 4x20 I/O pins1 38 31 31 I/O does not include two output-only port pins. The block diagram in Figure 1 shows the structure of the MC9S08LL16 series MCU. MC9S08LL16 Series MCU Data Sheet, Rev. 6 4 Freescale Semiconductor Devices in the MC9S08LL16 Series HCS08 CORE ON-CHIP ICE DEBUG MODULE (DBG) BKGD BKP TIME OF DAY MODULE (TOD) HCS08 SYSTEM CONTROL RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT COP IRQ LVD PTA1/KBIP1/SPSCK/ADP1 PORT A INT 8-BIT KEYBOARD INTERRUPT (KBI) KBI[7:0] RESET SERIAL PERIPHERAL INTERFACE (SPI) SS SPSCK MISO PTB7/SS PTB6/SPSCK MOSI SCL IRQ IIC MODULE (IIC) 2-CHANNEL TIMER/PWM (TPM2) SDA TPM2CH1 TCLK TPM1CH0 USER FLASH B (LL16 = 8K BYTES) (LL8 = 2K BYTES) 2-CHANNEL TIMER/PWM (TPM1) SERIAL COMMUNICATIONS INTERFACE (SCI) USER RAM PTC7/IRQ/TCLK PTC6/ACMPO//BKGD/MS PTC5/TPM2CH1 PTC4/TPM2CH0 TxD RxD PORT C XTAL PTC1/TxD PTC0/RxD 12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) VLL3 VCAP2 ANALOG COMPARATOR (ACMP) LCD[31:0] VSS PTD[7:0]/LCD[7:0] ACMP– ACMP+ ACMPO PORT E VDD AD[7:0] PORT D LOW-POWER OSCILLATOR VCAP1 PTC3/TPM1CH1 PTC2/TPM1CH0 EXTAL LIQUID CRYSTAL DISPLAY DRIVER LCD PTB3 PTB2/RESET TCLK (LL8 = 2K BYTES) VLL2 PTB5/MOSI/SCL PTB4/MISO/SDA PTB1/XTAL PTB0/EXTAL TPM1CH1 (LL16 = 2K BYTES) VLL1 PTA4/KBIP4/ADP4/LCD30 PTA7/KBIP7/ADP7/ACMP– BKGD/MS USER FLASH A (LL16 = 8K BYTES) (LL8 = 8K BYTES) VLCD PTA3/KBIP3/SCL/MOSI/ADP3 PTA6/KBIP6/ADP6/ACMP+ TPM2CH0 INTERNAL CLOCK Source (ICS) PTA2/KBIP2/SDA/MISO/ADP2 PTA5/KBIP5/ADP5/LCD31 PORT B CPU PTA0/KBIP0/SS/ADP0 VOLTAGE REGULATOR VDDA/VREFH VSSA/VREFL PTE[7:0]/LCD[15:8] KEY: Pins not available on 48-pin packages. LCD[23:16] not available on 48-pin packages. Notes: When PTB2 is configured as RESET, pin becomes bi-directional with output being open-drain drive containing an internal pull-up device. When PTC6 is configured as BKGD, pin becomes bi-directional. Figure 1. MC9S08LL16 Series Block Diagram MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 5 Pin Assignments 2 Pin Assignments 64-Pin LQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LCD26 LCD27 LCD28 LCD29 PTA5/KBIP5/ADP5/LCD30 PTA4/KBIP4/ADP4/LCD31 PTA3/KBIP3/SCL/MOSI/ADP3 PTA2/KBIP2/SDA/MISO/ADP2 PTA1/KBIP1/SPSCK/ADP1 PTA0/KBIP0/SS/ADP0 PTC7/IRQ/TCLK PTC6/ACMPO/BKGD/MS PTC5/TPM2CH1 PTC4/TPM2CH0 PTC3/TPM1CH1 PTC2/TPM1CH0 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PTA6/KBIP6/ADP6/ACMP+ PTA7/KBIP7/ADP7/ACMP– VSSA/VREFL VDDA/VREFH PTB0/EXTAL PTB1/XTAL VDD VSS PTB2/RESET PTB3 PTB4/MISO/SDA PTB5/MOSI/SCL PTB6/SPSCK PTB7/SS PTC0/RxD PTC1/TxD PTE1/LCD9 PTE0/LCD8 PTD7/LCD7 PTD6/LCD6 PTD5/LCD5 PTD4/LCD4 PTD3/LCD3 PTD2/LCD2 PTD1/LCD1 PTD0/LCD0 VCAP1 VCAP2 VLL1 VLL2 VLL3 VLCD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PTE2/LCD10 PTE3/LCD11 PTE4/LCD12 PTE5/LCD13 PTE6/LCD14 PTE7/LCD15 LCD16 LCD17 LCD18 LCD19 LCD20 LCD21 LCD22 LCD23 LCD24 LCD25 This section shows the pin assignments for the MC9S08LL16 series devices. Note: VREFH/VREFL are internally connected to VDDA/VSSA. Figure 2. MC9S08LL16 Series in 64-pin LQFP Package MC9S08LL16 Series MCU Data Sheet, Rev. 6 6 Freescale Semiconductor 37 48 PTD7/LCD7 47 1 LCD27 LCD26 LCD25 LCD24 PTE7/LCD15 PTE6/LCD14 PTE5/LCD13 PTE4/LCD12 PTE3/LCD11 PTE2/LCD10 PTE1/LCD9 PTE0/LCD8 Pin Assignments 46 45 44 43 42 41 40 39 38 36 LCD28 PTD6/LCD6 2 35 LCD29 PTD5/LCD5 3 34 PTA5/KBIP5/ADP5/LCD30 PTD4/LCD4/ 4 33 PTA4/KBIP4/ADP4/LCD31 PTD3/LCD3 5 32 PTA3/KBIP3/SCL/MOSI/ADP3 PTD2/LCD2 6 31 PTA2/KBIP2/SDA/MISO/ADP2 PTD1/LCD1 7 30 PTA1/KBIP1/SPSCK/ADP1 PTD0/LCD0 8 29 PTA0/KBIP0/SS/ADP0 9 28 PTC7/IRQ/TCLK VCAP2 10 27 PTC6/ACMPO/BKGD/MS VLL1 11 26 PTC3/TPM1CH1 VCAP1 48-Pin QFN/LQFP 25 PTC2/TPM1CH0 VLL2 12 14 15 16 17 18 19 20 21 22 23 PTC0/RxD PTB2/RESET VSS VDD PTB1/XTAL PTB0/EXTAL VDDA/VREFH VSSA/VREFL PTA7/KBIP7/ADP7/ACMP– PTA6/KBIP6/ADP6/ACMP+ VLL3 PTC1/TxD 24 13 Note: VREFH/VREFL are internally connected to VDDA/VSSA Figure 3. MC9S08LL16 Series in 48-Pin QFN/LQFP Packages MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 7 Pin Assignments Table 2. Pin Availability by Package Pin-Count <-- Lowest 64 48 Port Pin 1 47 PTE1 2 48 PTE0 LCD8 3 1 PTD7 LCD7 4 2 PTD6 LCD6 5 3 PTD5 LCD5 6 4 PTD4 LCD4 7 5 PTD3 LCD3 8 6 PTD2 LCD2 9 7 PTD1 LCD1 10 8 PTD0 11 9 Vcap1 12 10 Vcap2 13 11 VLL1 14 12 VLL2 15 13 VLL3 Priority Alt 1 --> Highest Alt 2 Alt3 Alt4 LCD9 LCD0 16 — 17 14 PTA6 VLCD KBIP6 ADP6 18 15 PTA7 KBIP7 ADP7 ACMP+ ACMP– VSSA 19 16 20 17 21 18 PTB0 EXTAL 22 19 PTB1 XTAL 23 20 24 21 25 22 PTB2 26 — PTB3 27 — PTB4 VREFL VREFH VDDA VDD VSS RESET — MISO SDA SCL 28 — PTB5 — MOSI 29 — PTB6 — SPSCK 30 — PTB7 — 31 23 PTC0 SS RxD 32 24 PTC1 TxD 33 25 PTC2 TPM1CH0 34 26 PTC3 TPM1CH1 35 — PTC4 TPM2CH0 36 — PTC5 37 27 PTC6 38 28 PTC7 39 29 PTA0 TPM2CH1 ACMPO KBIP0 BKGD MS IRQ TCLK — SS ADP0 MC9S08LL16 Series MCU Data Sheet, Rev. 6 8 Freescale Semiconductor Electrical Characteristics Table 2. Pin Availability by Package Pin-Count (continued) <-- Lowest Port Pin Alt 1 Priority --> Highest 64 48 Alt 2 Alt3 40 30 PTA1 KBIP1 — SPSCK ADP1 41 31 PTA2 KBIP2 SDA MISO ADP2 ADP3 42 32 PTA3 KBIP3 SCL MOSI 43 33 PTA4 KBIP4 ADP4 LCD31 44 34 PTA5 KBIP5 ADP5 LCD30 45 35 LCD29 46 36 LCD28 47 37 LCD27 48 38 LCD26 49 39 LCD25 50 40 LCD24 51 — LCD23 52 — LCD22 53 — LCD21 54 — LCD20 55 LCD19 56 LCD18 57 LCD17 58 LCD16 59 41 PTE7 LCD15 60 42 PTE6 LCD14 61 43 PTE5 LCD13 62 44 PTE4 LCD12 63 45 PTE3 LCD11 64 46 PTE2 LCD10 3 Electrical Characteristics 3.1 Introduction Alt4 This section contains electrical and timing specifications for the MC9S08LL16 series of microcontrollers available at the time of publication. 3.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 9 Electrical Characteristics Table 3. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 3.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. Table 4. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to 3.8 V Maximum current into VDD IDD 120 mA Digital input voltage VIn –0.3 to VDD + 0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID 25 mA Tstg –55 to 150 C Storage temperature range 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins, except for PTB2 are internally clamped to V SS and VDD. 3 Power supply must maintain regulation within operating V DD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). MC9S08LL16 Series MCU Data Sheet, Rev. 6 10 Freescale Semiconductor Electrical Characteristics 3.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 5. Thermal Characteristics Rating Operating temperature range (packaged) Maximum junction temperature Symbol Value Unit TA TL to TH –40 to 85 C TJM 95 C Thermal resistance Single-layer board 64-pin LQFP 72 JA 48-pin QFN 48-pin LQFP 84 C/W 81 Thermal resistance Four-layer board 64-pin LQFP 54 JA 48-pin QFN 48-pin LQFP 30 C/W 57 The average chip-junction temperature (TJ) in C can be obtained from: TJ = TA + (PD JA) Eqn. 3-1 where: TA = Ambient temperature, C JA = Package thermal resistance, junction-to-ambient, C/W PD = Pint PI/O Pint = IDD VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K (TJ + 273C) Eqn. 3-2 Solving Equation 3-1 and Equation 3-2 for K gives: K = PD (TA + 273C) + JA (PD)2 Eqn. 3-3 MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 11 Electrical Characteristics where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 3-1 and Equation 3-2 iteratively for any value of TA. 3.5 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be taken to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification, ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless instructed otherwise in the device specification. Table 6. ESD and Latch-up Test Conditions Model Description Symbol Value Unit R1 1500 C 100 pF — 3 Series resistance R1 0 Storage capacitance C 200 pF Number of pulses per pin — 3 Series resistance Human Body Model Storage capacitance Number of pulses per pin Charge Device Model Minimum input voltage limit –2.5 V Maximum input voltage limit 7.5 V Latch-up Table 7. ESD and Latch-Up Protection Characteristics No. 1 Rating1 Symbol Min Max Unit 1 Human body model (HBM) VHBM 2000 — V 2 Charge device model (CDM) VCDM 500 — V 3 Latch-up current at TA = 85C ILAT 100 — mA Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. MC9S08LL16 Series MCU Data Sheet, Rev. 6 12 Freescale Semiconductor Electrical Characteristics 3.6 DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. Table 8. DC Characteristics Num C 1 Characteristic Output high P voltage Output high P voltage C D Output high current Output low P voltage C PTA[4:5], PTD[0:7], PTE[0:7], high-drive strength Max total IOH for all ports VOH Output low P voltage C Output low current Typ1 PTA[0:3], PTA[6:7], PTB[0:7], PTC[0:7], high-drive strength VOL PTA[4:5], PTD[0:7], PTE[0:7], high-drive strength 7 D Max total IOL for all ports 8 P Input high C voltage all digital inputs 9 P Input low C voltage all digital inputs 10 C Input hysteresis 11 P Input leakage current all digital inputs all input only pins (per pin) VOL VIL 3.6 V — — VDD > 2.7 V ILoad = –10 mA VDD – 0.5 — — VDD > 1.8 V ILoad = –3 mA VDD – 0.5 — — VDD > 1.8 V ILoad = –0.5 mA VDD – 0.5 — — VDD > 2.7 V ILoad = –3 mA VDD – 0.5 — — VDD > 1.8 V ILoad = –1 mA VDD – 0.5 — — — — 100 VDD >1.8 V ILoad = 0.6 mA — — 0.5 VDD > 2.7 V ILoad = 10 mA — — 0.5 VDD > 1.8 V ILoad = 3 mA — — 0.5 VDD > 1.8 V ILoad = 0.5 mA — — 0.5 VDD > 2.7 V ILoad = 3 mA — — 0.5 VDD > 1.8 V ILoad = 1 mA — — 0.5 — — 100 VDD 2.7 V 0.70 VDD — — V V mA V V mA VDD 1.8 V 0.85 VDD — — VDD 2.7 V — — 0.35 x VDD VDD 1.8 V — — 0.30 x VDD 0.06 VDD — — mV — 0.025 1 A Vhys |IIn| Unit VDD – 0.5 IOLT VIH Max VDD >1.8 V ILoad = –0.6 mA IOHT PTA[4:5], PTD[0:7], PTE[0:7], low-drive strength C 6 VOH PTA[0:3], PTA[6:7], PTB[0:7], PTC[0:7], low-drive strength C 5 PTA[0:3], PTA[6:7], PTB[0:7], PTC[0:7]2, high-drive strength PTA[4:5], PTD[0:7], PTE[0:7], low-drive strength C 4 Min 1.8 PTA[0:3], PTA[6:7], PTB[0:7], PTC[0:7]2, low-drive strength C 3 Condition Operating voltage C 2 Symbol VIn = VDD or VSS V MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 13 Electrical Characteristics Table 8. DC Characteristics (continued) Num C 12 Hi-Z (off-state) P leakage current 13 P 14 P Pullup, pulldown resistors when P enabled 2 3 4 5 6 7 8 Condition Min Typ1 Max Unit all input/output (per pin) |IOZ| VIn = VDD or VSS — 0.025 1 A Total leakage current3 Total leakage current for all pins |IInT| VIn = VDD or VSS — 2 A DC injection current 4, 5, 6 PTA[0:3], PTA[6:7], PTB[0:7], PTC[0:7] PTA[4:5], PTD[0:7], PTE[0:7] D 16 C Input capacitance, all pins 17 C RAM retention voltage Total MCU limit, includes sum of all stressed pins 7 — 52.5 RPU, RPD — IIC VIN < VSS, VIN > VDD 17.5 — k 69.5 Single pin limit 15 –0.2 — 0.2 mA –5 — 5 mA CIn — — 8 pF VRAM — 0.6 1.0 V 18 C POR re-arm voltage VPOR 0.9 1.4 2.0 V 19 D POR re-arm time tPOR 10 — — s 20 P Low-voltage detection threshold VLVD VDD falling VDD rising 1.80 1.88 1.84 1.92 1.88 1.96 V 21 P Low-voltage warning threshold VLVW VDD falling VDD rising 2.08 2.14 2.2 V 22 P Low-voltage inhibit reset/recover hysteresis Vhys — 80 — mV VBG 1.15 1.17 1.18 V 23 1 Symbol Characteristic P Bandgap voltage reference 8 Typical values are measured at 25 C. Characterized, not tested All I/O pins except for LCD pins in open drain mode. Total leakage current is the sum value for all GPIO pins. This leakage current is not distributed evenly across all pins but characterization data shows that individual pin leakage current maximums are less than 250 nA. All functional non-supply pins, except for PTB2 are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If the positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure that external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). POR will occur below the minimum voltage. Factory trimmed at VDD = 3.0 V, Temp = 25 C. MC9S08LL16 Series MCU Data Sheet, Rev. 6 14 Freescale Semiconductor Electrical Characteristics Figure 4. Non-LCD pins I/O Pullup and Pulldown Typical Resistor Values (VDD = 3.0 V) MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 15 Electrical Characteristics Figure 5. LCD/GPIO Pins I/O Pullup/Pulldown Typical Resistor Values MC9S08LL16 Series MCU Data Sheet, Rev. 6 16 Freescale Semiconductor Electrical Characteristics Figure 6. Typical Low-Side Driver (Sink) Characteristics (Non-LCD pins) — Low Drive (PTxDSn = 0) MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 17 Electrical Characteristics Figure 7. Typical Low-Side Driver (Sink) Characteristics(Non-LCD pins) — High Drive (PTxDSn = 1) MC9S08LL16 Series MCU Data Sheet, Rev. 6 18 Freescale Semiconductor Electrical Characteristics Figure 8. Typical High-Side (Source) Characteristics (Non-LCD Pins) — Low Drive (PTxDSn = 0) MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 19 Electrical Characteristics Figure 9. Typical High-Side (Source) Characteristics(Non-LCD Pins) — High Drive (PTxDSn = 1) MC9S08LL16 Series MCU Data Sheet, Rev. 6 20 Freescale Semiconductor Electrical Characteristics Preliminary IOL (mA) Figure 10. Typical Low-Side Driver (Sink) Characteristics (LCD/GPIO Pins) — Low Drive (PTxDSn = 0) MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 21 Electrical Characteristics Figure 11. Typical Low-Side Driver (Sink) Characteristics(LCD/GPIO Pins) — High Drive (PTxDSn = 1) MC9S08LL16 Series MCU Data Sheet, Rev. 6 22 Freescale Semiconductor Electrical Characteristics Figure 12. Typical High-Side (Source) Characteristics (LCD/GPIO Pins) — Low Drive (PTxDSn = 0) MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 23 Electrical Characteristics Figure 13. Typical High-Side (Source) Characteristics(LCD/GPIO pins) — High Drive (PTxDSn = 1) MC9S08LL16 Series MCU Data Sheet, Rev. 6 24 Freescale Semiconductor Electrical Characteristics 3.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. Table 9. Supply Current Characteristics Num 1 2 P T T T T 3 T T 4 T T 5 T 6 7 Parameter C P C T Symbol Run supply current FEI mode, all modules on RIDD Run supply current FEI mode, all modules off RIDD Run supply current LPRS=0, all modules off RIDD Run supply current LPRS=1, all modules off; running from Flash RIDD Run supply current LPRS=1, all modules off; running from RAM RIDD Wait mode supply current FEI mode, all modules off WIDD Wait mode supply current LPRS = 1, all modules off WIDD P 8 1 MHz 10 MHz 1 MHz 16 kHz FBILP 16 kHz FBELP 16 kHz FBILP 16 kHz FBELP 16 kHz FBILP 16 kHz FBELP 8 MHz 1 MHz 16 kHz FBELP n/a P n/a C 3 3 Max Unit Temp (C) 4.2 5.7 mA 1 1.52 –40 to 85 C 3.60 — 0.50 — mA –40 to 85 C 165 — A –40 to 85 C 105 — 77 — A –40 to 85 C 21 — 77 — A –40 to 85 C 7.3 — 1.4 3.5 0.8 1.15 mA –40 to 85 C 1.3 — A –40 to 85 C 350 930 –40 to 25 C 1000 — 50 C 2500 4000 70 C 5100 — 250 — –40 to 25 C 2000 — 70 C 4000 — 85 C 400 1030 –40 to 25 C 1300 — 50 C 4000 6000 70 C 8000 — 350 — –40 to 25 C 3000 — 70 C 6000 — 85 C 3 3 3 3 3 2 3 S3IDD n/a Typ1 3 S2IDD C Stop3 mode supply current No clocks active VDD (V) 8 MHz n/a Stop2 mode supply current 9 Bus Freq 2 nA nA 85 C 85 C MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 25 Electrical Characteristics Table 9. Supply Current Characteristics (continued) 1 2 Num C 10 C 11 C Parameter Symbol Bus Freq VDD (V) Typ1 Max Unit Temp (C) Application Stop3 mode supply current2 ApS3IDD n/a 3 6.1 — A 25 C Application Stop3 mode supply current2 ApS3IDD n/a 3 7.5 — A 50 C Typical values are measured at 25 C. Characterized, not tested. 32 kHz crystal enabled in low power mode. TOD module enabled. VIREG enabled for 3 V LCD glass 500pf 8x24 LCD glass at 32 Hz frame rate with LCD Charge pump clock set to low setting and every other segment “on.” Table 10. Stop Mode Adders Temperature (C) Num Parameter Condition Units –40 25 70 85 100 100 150 175 nA 250 360 400 460 nA 63 70 77 81 A 1 T LPO 2 T ERREFSTEN 3 T IREFSTEN1 4 T TOD Does not include clock source current 50 50 75 100 nA 5 T LVD1 LVDSE = 1 110 110 112 115 A 6 T ACMP1 Not using the bandgap (BGBE = 0) 12 12 20 23 A 7 T ADC1 ADLPC = ADLSMP = 1 Not using the bandgap (BGBE = 0) 95 95 101 120 A LCD VIREG enabled for Contrast control, 1/8 Duty cycle, 8x24 configuration for driving 192 Segments, 32Hz frame rate, No LCD glass connected. 1 1 4.2 12 A 8 1 C T RANGE = HGO = 0 Not available in stop2 mode. MC9S08LL16 Series MCU Data Sheet, Rev. 6 26 Freescale Semiconductor Electrical Characteristics 3.8 External Oscillator (XOSCVLP) Characteristics Refer to Figure 14 and Figure 15 for crystal or resonator circuits. Table 11. XOSCVLP and ICS Specifications (Temperature Range = –40 to 85 C Ambient) Num 1 2 C Characteristic Load capacitors Low range (RANGE=0), low power (HGO=0) D Other oscillator settings 3 4 Series resistor — Low range, low power (RANGE = 0, HGO = 0)2 Low range, high gain (RANGE = 0, HGO = 1) High range, low power (RANGE = 1, HGO = 0) D High range, high gain (RANGE = 1, HGO = 1) 8 MHz 4 MHz 1 MHz 6 Min Typ1 Max Unit flo fhi fhi 32 1 1 — — — 38.4 16 8 kHz MHz MHz Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) C High range (RANGE = 1), high gain (HGO = 1) High range (RANGE = 1), low power (HGO = 0) Feedback resistor Low range, low power (RANGE=0, HGO=0)2 D Low range, high gain (RANGE=0, HGO=1) High range (RANGE=1, HGO=X) 5 Symbol Crystal start-up time 4 Low range, low power Low range, high gain C High range, low power High range, high gain RF RS t t Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE mode D FBE or FBELP mode See Note 2 See Note 3 C1,C2 CSTL CSTH fextal — — — — 10 1 — — — — — — — 100 0 — — — — — — 0 0 0 0 10 20 — — — — 600 400 5 15 — — — — ms 0.03125 0 — — 20 20 MHz MHz M k 1 Data in Typical column was characterized at 3.0 V, 25C or is typical recommended value. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0. 3 See crystal or resonator manufacturer’s recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications. 2 MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 27 Electrical Characteristics XOSCVLP EXTAL XTAL RS RF C1 Crystal or Resonator C2 Figure 14. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain XOSCVLP EXTAL XTAL Crystal or Resonator Figure 15. Typical Crystal or Resonator Circuit: Low Range/Low Power 3.9 Internal Clock Source (ICS) Characteristics Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient) Num C Characteristic Symbol Min Typ1 Max Unit 1 P Average internal reference frequency — factory trimmed at VDD = 3.6 V and temperature = 25 C fint_ft — 32.768 — kHz 2 P Average internal reference frequency - trimmed fint_t 31.25 — 39.063 kHz 3 T Internal reference start-up time tIRST — — 6 s 4 P DCO output frequency range - untrimmed fdco_ut 12.8 16.8 21.33 MHz 5 P DCO output frequency range - trimmed fdco_t 16 — 20 MHz 6 C Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) fdco_res_t — 0.1 0.2 %fdco 7 C Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) fdco_res_t — 0.2 0.4 %fdco 8 C Total deviation from trimmed DCO output frequency over voltage and temperature fdco_t — + 0.5 –1.0 2 %fdco MC9S08LL16 Series MCU Data Sheet, Rev. 6 28 Freescale Semiconductor Electrical Characteristics Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85C Ambient) (continued) Num C Characteristic 9 C 10 C FLL acquisition time 2 11 C Total deviation from trimmed DCO output frequency over fixed voltage and temperature range of 0C to 70 C Long term jitter of DCO output clock (averaged over 2-ms interval) 3 Symbol Min Typ1 Max Unit fdco_t — 0.5 1 %fdco tAcquire — — 1 ms CJitter — 0.02 0.2 %fdco Data in Typical column was characterized at 3.0 V, 25 C or is typical recommended value. This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 3 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in the crystal oscillator frequency increase the CJitter percentage for a given interval. 1 2 Figure 16. Deviation of DCO Output from Trimmed Frequency (20 MHz, 3.0 V) MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 29 Electrical Characteristics 3.10 AC Characteristics This section describes timing characteristics for each peripheral system. 3.10.1 Control Timing Table 13. Control Timing Symbol Min Typ1 Max Unit Bus frequency (tcyc = 1/fBus) fBus dc — 10 MHz D Internal low power oscillator period tLPO 700 — 1300 s 3 D External reset pulse width2 textrst 100 — — ns 4 D Reset low drive trstdrv 34 tcyc — — ns 5 D BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes tMSSU — — ns 6 D BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 tMSH — — s 7 D IRQ pulse width Asynchronous path2 Synchronous path4 tILIH, tIHIL 100 1.5 tcyc — — — — ns Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 tILIH, tIHIL 100 1.5 tcyc — — — — ns Port rise and fall time — Non-LCD Pins Low output drive (PTxDS = 0) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise, tFall — — 16 23 — — Port rise and fall time — Non-LCD Pins High output drive (PTxDS = 1) (load = 50 pF)5, 6 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise, tFall — — 5 9 — — — 6 10 Num C 1 D 2 D 8 9 10 1 2 3 4 5 6 Rating 500 100 ns C C Voltage Regulator Recovery time tVRR ns us Typical values are based on characterization data at VDD = 3.0 V, 25 C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset pin request. To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD rises above VLVD. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized. Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 C to 85 C. Except for LCD pins in Open Drain mode. MC9S08LL16 Series MCU Data Sheet, Rev. 6 30 Freescale Semiconductor Electrical Characteristics textrst RESET PIN Figure 17. Reset Timing tIHIL IRQ/KBIPx IRQ/KBIPx tILIH Figure 18. IRQ/KBIPx Timing 3.10.2 TPM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 14. TP Input Timing No. C 1 D 2 Function Symbol Min Max Unit External clock frequency fTCLK 0 fBus/4 Hz D External clock period tTCLK 4 — tcyc 3 D External clock high time tclkh 1.5 — tcyc 4 D External clock low time tclkl 1.5 — tcyc 5 D Input capture pulse width tICPW 1.5 — tcyc tTCLK tclkh TCLK tclkl Figure 19. Timer External Clock MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 31 Electrical Characteristics tICPW TPMCHn TPMCHn tICPW Figure 20. Timer Input Capture Pulse 3.10.3 SPI Timing Table 15 and Figure 21 through Figure 24 describe the timing requirements for the SPI system. Table 15. SPI Timing No. C — Function Symbol Min Max Unit fop fBus/2048 0 fBus/2 fBus/4 Hz tSPSCK 2 4 2048 — tcyc tcyc D Operating frequency Master Slave 1 D SPSCK period Master Slave 2 D Enable lead time Master Slave tLead 12 1 — — tSPSCK tcyc 3 D Enable lag time Master Slave tLag 12 1 — — tSPSCK tcyc 4 D Clock (SPSCK) high or low time Master Slave tWSPSCK tcyc –30 tcyc – 30 1024 tcyc — ns ns 5 D Data setup time (inputs) Master Slave tSU 15 15 — — ns ns 6 D Data hold time (inputs) Master Slave tHI 0 25 — — ns ns 7 D Slave access time ta — 1 tcyc 8 D Slave MISO disable time tdis — 1 tcyc 9 D Data valid (after SPSCK edge) Master Slave tv — — 25 25 ns ns MC9S08LL16 Series MCU Data Sheet, Rev. 6 32 Freescale Semiconductor Electrical Characteristics Table 15. SPI Timing (continued) No. C Function Symbol Min Max Unit 10 D Data hold time (outputs) Master Slave tHO 0 0 — — ns ns 11 D Rise time Input Output tRI tRO — — tcyc – 25 25 ns ns 12 D Fall time Input Output tFI tFO — — tcyc – 25 25 ns ns SS1 (OUTPUT) 1 2 SPSCK (CPOL = 0) (OUTPUT) 11 3 4 4 12 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MS BIN2 9 MOSI (OUTPUT) BIT 6 . . . 1 LSB IN 9 MSB OUT2 BIT 6 . . . 1 10 LSB OUT NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 21. SPI Master Timing (CPHA = 0) MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 33 Electrical Characteristics SS1 (OUTPUT) 1 2 12 11 11 12 3 SPSCK (CPOL = 0) (OUTPUT) 4 SPSCK (CPOL = 1) (OUTPUT) 4 5 MISO (INPUT) 6 MSB IN2 BIT 6 . . . 1 9 LSB IN 10 MOSI (OUTPUT) PORT DATA BIT 6 . . . 1 MASTER MSB OUT2 MASTER LSB OUT PORT DATA NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 22. SPI Master Timing (CPHA =1) SS (INPUT) 1 12 11 11 12 3 SPSCK (CPOL = 0) (INPUT) 2 4 4 SPSCK (CPOL = 1) (INPUT) 8 7 MISO (OUTPUT) 9 SLAVE MSB OUT SLAVE LSB OUT SEE NOTE 1 6 5 MOSI (INPUT) BIT 6 . . . 1 10 10 MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally MSB of character just received. Figure 23. SPI Slave Timing (CPHA = 0) MC9S08LL16 Series MCU Data Sheet, Rev. 6 34 Freescale Semiconductor Electrical Characteristics SS (INPUT) 1 3 2 SPSCK (CPOL = 0) (INPUT) 4 SPSCK (CPOL = 1) (INPUT) 4 9 MISO (OUTPUT) SEE NOTE 1 MSB OUT 5 7 11 11 12 10 SLAVE MOSI (INPUT) 12 8 BIT 6 . . . 1 SLAVE LSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received. Figure 24. SPI Slave Timing (CPHA = 1) 3.11 Analog Comparator (ACMP) Electricals Table 16. Analog Comparator Electrical Specifications C Characteristic Symbol Min Typical Max Unit VDD 1.8 — 3.6 V D Supply voltage C Supply current (active) IDDAC — 20 35 A D Analog input voltage VAIN VSS – 0.3 — VDD V P Analog input offset voltage VAIO 20 40 mV C Analog comparator hysteresis VH 3.0 9.0 15.0 mV P Analog input leakage current IALKG — — 1.0 A C Analog comparator initialization delay tAINIT — — 1.0 s 3.12 ADC Characteristics Table 17. 12-bit ADC Operating Conditions Symb Min Typ1 Max Unit Absolute VDDA 1.8 — 3.6 V Delta to VDD (VDD–VDDA)2 VDDA –100 0 100 mV Delta to VSS (VSS–VSSA)2 VSSA –100 0 100 mV Characteristic Supply voltage Ground voltage Conditions Comment MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 35 Electrical Characteristics Table 17. 12-bit ADC Operating Conditions Symb Min Typ1 Max Unit Ref Voltage High VREFH 1.8 VDDA VDDA V Input Voltage VADIN VREFL — VREFH V Input Capacitance CADIN — 4.5 5.5 pF Input Resistance RADIN — 5 7 k — — — — 2 5 — — — — 5 10 — — 10 0.4 — 8.0 0.4 — 4.0 Characteristic Conditions 12-bit mode fADCK > 4MHz fADCK < 4MHz Analog Source Resistance 10-bit mode fADCK > 4MHz fADCK < 4MHz RAS k 8-bit mode (all valid fADCK) ADC Conversion Clock Freq. High speed (ADLPC = 0) fADCK Low power (ADLPC = 1) Comment External to MCU MHz Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. 1 SIMPLIFIED INPUT PIN EQUIVALENT CIRCUIT Pad leakage due to input protection ZAS RAS ZADIN SIMPLIFIED CHANNEL SELECT CIRCUIT RADIN ADC SAR ENGINE + VADIN VAS + – CAS – RADIN INPUT PIN INPUT PIN RADIN RADIN INPUT PIN CADIN Figure 25. ADC Input Impedance Equivalency Diagram MC9S08LL16 Series MCU Data Sheet, Rev. 6 36 Freescale Semiconductor Electrical Characteristics Table 18. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) Symb Min Typ1 Max Unit T Supply Current ADLPC=1 ADLSMP=1 ADCO=1 IDDA — 120 — A T Supply Current ADLPC=1 ADLSMP=0 ADCO=1 IDDA — 200 — A T Supply Current ADLPC=0 ADLSMP=1 ADCO=1 IDDA — 290 — A P Supply Current ADLPC=0 ADLSMP=0 ADCO=1 IDDA — 0.53 1 mA 2 3.3 5 C Characteristic P C P C Conditions ADC Asynchronous Clock Source High Speed (ADLPC=0) Conversion Time (Including sample time) Short Sample (ADLSMP=0) P Low Power (ADLPC=1) Long Sample (ADLSMP=1) fADACK tADC Short Sample (ADLSMP=0) Sample Time C Long Sample (ADLSMP=1) T 12-bit mode, 3.6>VDDA>2.7V Total Unadjusted Error 12-bit mode, 2.7>VDDA>1.8V tADS ETUE MHz 1.25 2 3.3 — 20 — — 40 — — 3.5 — — 23.5 — — –1 to 3 –2.5 to 5.5 — –1 to 3 –3.0 to 6.0 P 10-bit mode — 1 2.5 T 8-bit mode — 0.5 1.0 T 12-bit mode — 1 –1.5 to 2.0 — 0.5 1.0 P Differential Non-Linearity 10-bit mode3 DNL T 8-bit mode3 — 0.3 0.5 T 12-bit mode — 1.5 –2.5 to 1.0 — 0.5 1.0 — 0.3 0.5 P Integral Non-Linearity T 10-bit mode 8-bit mode INL ADCK cycles ADCK cycles LSB2 Comment tADACK = 1/fADACK See ADC chapter in the LL16 Reference Manual for conversion time variances Includes quantization LSB2 LSB2 MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 37 Electrical Characteristics Table 18. 12-bit ADC Characteristics (VREFH = VDDA, VREFL = VSSA) (continued) C Characteristic T P Conditions Symb 12-bit mode Zero-Scale Error 10-bit mode EZS Min Typ1 Max — 1.5 2.5 — 0.5 1.5 T 8-bit mode — 0.5 0.5 T 12-bit mode — 1 –3.5 to 1.0 — 0.5 1 8-bit mode — 0.5 0.5 12-bit mode — –1 to 0 — — — 0.5 8-bit mode — — 0.5 12-bit mode — 2 — — 0.2 4 — 0.1 1.2 — 1.646 — — 1.769 — — 701.2 — P Full-Scale Error T D D Quantization Error Input Leakage Error EFS 10-bit mode EQ 10-bit mode EIL 10-bit mode 8-bit mode D D Temp Sensor Slope Temp Sensor Voltage –40 C to 25 C 25 C to 85 C 25 C m VTEMP25 Unit Comment LSB2 VADIN = VSSA LSB2 VADIN = VDDA LSB2 LSB2 Pad leakage4 * RAS mV/C mV Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (V N REFH – VREFL)/2 3 Monotonicity and No-Missing-Codes guaranteed in 10-bit and 8-bit modes 4 Based on input pad leakage current. Refer to pad electricals. 1 MC9S08LL16 Series MCU Data Sheet, Rev. 6 38 Freescale Semiconductor Electrical Characteristics 3.13 LCD Specifications Table 19. LCD Electricals, 3 V Glass C D Characteristic LCD Supply Voltage Symbol Min Typ Max VLCD 0.9 1.5 1.8 28 D LCD Frame Frequency fFrame D LCD Charge Pump Capacitance CLCD D LCD Bypass Capacitance D LCD Glass Capacitance D VIREG HRefSel = 0 VIREG TRIM Resolution D VIREG Ripple D 1 2 30 58 Hz 100 100 nF 100 100 nF Cglass 2000 8000 pF VIREG .89 1.00 1.15 1.49 1.67 1.851 RTRIM VLCD Buffered Adder2 V CBYLCD HRefSel = 1 D Unit 1.5 % VIREG HRefSel = 0 0.1 HRefSel = 1 0.15 IBuff V 1 V A VIREG Max can not exceed VDD – 0.15 V VSUPPLY = 10, BYPASS = 0 3.14 Flash Specifications This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section. MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 39 Electrical Characteristics Table 20. Flash Characteristics C Characteristic Symbol Min Typical Max Unit D Supply voltage for program/erase -40C to 85C Vprog/erase 1.8 3.6 V D Supply voltage for read operation VRead 1.8 3.6 V fFCLK 150 200 kHz tFcyc 5 6.67 s 1 D Internal FCLK frequency D Internal FCLK period (1/FCLK) P P P P D D 2 Byte program time (random location) Byte program time (burst mode) 2 2 Page erase time 2 Mass erase time Byte program current Page erase 3 current3 tprog 9 tFcyc tBurst 4 tFcyc tPage 4000 tFcyc tMass 20,000 tFcyc RIDDBP — 4 — mA RIDDPE — 6 — mA 10,000 — 100,000 — — cycles 15 100 — years endurance4 C Program/erase TL to TH = –40C to + 85C T = 25C C Data retention5 tD_ret 1 The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run I . These values are measured at room temperatures DD with VDD = 3.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for FLASH was evaluated for this product family on the 9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory. 2 3.15 EMC Performance Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board design and layout, circuit topology choices, location and characteristics of external components as well as MCU software operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC performance. 3.15.1 Radiated Emissions Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller are measured in a TEM cell in two package orientations (North and East). MC9S08LL16 Series MCU Data Sheet, Rev. 6 40 Freescale Semiconductor Ordering Information The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported emissions levels. Table 21. Radiated Emissions, Electric Field Parameter Symbol Conditions Frequency fOSC/fBUS VRE_TEM VDD = 3.3 V TA = 25 oC package type 64-pin LQFP 0.15 – 50 MHz 32 kHz crystal 10 MHz bus Radiated emissions, electric field 1 50 – 150 MHz Level1 (Max) Unit –7 dBV –9 150 – 500 MHz –6 500 – 1000 MHz –6 IEC Level N — SAE Level 1 — Data based on qualification test results. 4 Ordering Information This section contains the ordering information and the device numbering system for the MC9S08LL16 Series. 4.1 Device Numbering System Example of the device numbering system: MC 9 S08 LL 16 Status (MC = Fully Qualified) Memory (9 = Flash-based) Core Family 5 C XX Package designator (see Table 22) Temperature range (C = –40 C to 85 C) Approximate FLASH size in KB Package Information and Mechanical Drawings Table 22 provides the available package types and their document numbers. The latest package outline/mechanical drawings are available on the MC9S08LL16 Series Product Summary pages at http://www.freescale.com. To view the latest drawing, either: • Click on the appropriate link in Table 22, or • Open a browser to the Freescale® website (http://www.freescale.com), and enter the appropriate document number (from Table 22) in the “Enter Keyword” search box at the top of the page. MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 41 Package Information and Mechanical Drawings Table 22. Package Descriptions Pin Count Abbreviation Designator Case No. Document No. Low Quad Flat Package LQFP LH 840F 98ASS23234W 48 Low Quad Flat Package LQFP LF 932 98ASH00962A 48 Quad Flat No-Leads QFN GT 1314 98ARH99048A 64 Package Type MC9S08LL16 Series MCU Data Sheet, Rev. 6 42 Freescale Semiconductor Package Information and Mechanical Drawings MC9S08LL16 Series MCU Data Sheet, Rev. 6 Freescale Semiconductor 43 How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. 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