FREESCALE PC33892PNC

Freescale Semiconductor, Inc.
MOTOROLA
Document order number: MC33892
Rev 1.0, 03/2004
SEMICONDUCTOR TECHNICAL DATA
Preliminary Information
33892
Quad Intelligent High-Side Switch
(Dual 10 mΩ and Dual 35 mΩ)
Freescale Semiconductor, Inc...
The 33892 is one in a family of devices designed for low-voltage automotive
and industrial lighting and motor control applications. Its four low RDS(ON)
MOSFETs (two 10 mΩ, two 35 mΩ) can control the high sides of four separate
resistive or inductive loads or serve as high-side switches for a pair of DC
motors.
QUAD INTELLIGENT
HIGH-SIDE SWITCH
Programming, control, and diagnostics are accomplished using a 16-bit SPI
interface. Additionally, each output has its own parallel input for PWM control
if desired. The 33892 allows the user to program via the SPI the fault current
trip levels and duration of acceptable lamp inrush or motor stall intervals. Such
programmability allows tight control of fault currents and can protect wiring
harnesses and circuit boards as well as loads.
The 33892 is packaged in a power-enhanced 10 x 10 nonleaded Power
QFN package with exposed tabs.
PNC SUFFIX
CASE 1558-02
24-TERMINAL PQFN
Features
• Dual 10 mΩ and Dual 35 mΩ High-Side Switches
• Operating Voltage Range of 6.0 V to 27 V with Standby Current < 5.0 µA
• SPI Control of Overcurrent Limit, Overcurrent Fault Blanking Time,
Output-OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout, Slew Rates, and Fault Status Reporting
• SPI Status Reporting of Overcurrent, Open and Shorted Loads,
Overtemperature, Undervoltage and Overvoltage Shutdown, Fail-Safe
Terminal Status, and Program Status
• Analog Current Feedback with Selectable Ratio
• Enhanced 16 V Reverse Polarity VPWR Protection
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
PC33892PNC/R2
-40°C to 125°C
24 PQFN
Simplified Application Diagram
33892 Simplified Application Diagram
VPWR
VDD
VDD
VDD
VPWR
33892
VDD
VPWR
HS0
WAKE
SO
SCLK
MCU
CS
SI
SO
I/O
RST
I/O
FS
I/O
IN0
I/O
IN1
I/O
IN2
I/O
LOAD 0
SCLK
CS
A/D
GND
SI
HS1
LOAD 1
HS2
LOAD 2
HS3
IN3
CSNS
FSI
LOAD 3
GND
This document contains information on a product under development.
Motorola reserves the right to change or discontinue this product without notice.
© Motorola, Inc. 2004
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
VDD
VPWR
Internal
Regulator
Freescale Semiconductor, Inc...
CS
SCLK
SO
SI
RST
WAKE
FS
IN0
Over/Undervoltage
Protection
Selectable Slew
Rate Gate Drive
SPI
3.0 MHz
HS0
Selectable Current Limit
HS[0:1]: 100 A or 70 A
HS[2:3]: 50 A or 35 A
Logic
Selectable Current
Detection Time
0.15 ms–620 ms
IN1
IN2
Selectable Overcurrent Detection
HS[0:1]: 4.8 A–18.2 A
HS[2:3]: 2.4 A–9.1 A
Open
Load
Detection
IN3
Overtemperature
Detection
HS0
HS1
Programmable
Watchdog
310 ms–2500 ms
HS1
HS2
HS2
FSI
HS3
HS3
Selectable Output Current
Recopy (Analog MUX)
HS[0:1]: 1/13000 or 1/40000
HS[2:3]: 1/6500 or 1/20000
GND
CSNS
Figure 1. 33892 Simplified Internal Block Diagram
33892
2
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
4
3
IN1
IN3
6 5
IN2
FS
7
WAKE
RST
8
GND
CS
10 9
SI
Transparent Top View of Package
SCLK
Freescale Semiconductor, Inc.
2 1
24
IN0
12
23
CSNS
13
22
FSI
VDD
11
SO
GND
GND
14
15
21
HS3
HS2
Freescale Semiconductor, Inc...
16
VPWR
HS1
17
18
HS1
19
20
HS0
HS0
TERMINAL FUNCTION DESCRIPTION
Terminal
Terminal Name
Formal Name
Definition
1
2
3
24
IN1
IN2
IN3
IN0
Serial Inputs
The IN0–IN3 high-side input terminals are used to directly control HS0–HS3 high-side
output terminals, respectively. An SPI register determines if each input is activated or
if the input logic state is ORed or ANDed with the SPI instruction. These terminals are
to be driven with 5.0 V CMOS levels, and they have an internal active pull-down current
source.
4
FS
Fault Status
(Active Low)
This terminal is an open drain configured output requiring an external pull-up resistor
to VDD for fault reporting. If a device fault condition is detected, this terminal is active
LOW. Specific device diagnostic faults are reported via the SPI SO terminal.
5
WAKE
Wake
This terminal is an input that controls the device mode and watchdog timeout feature
if enabled. An internal clamp protects this terminal from high damaging voltages when
the output is current limited with an external resistor. This input has an internal passive
pull-down.
6, 13, 15
GND
Ground
7
RST
Reset
This terminal is an input used to initialize the device configuration and fault registers,
as well as place the device in a low-current sleep mode. The terminal also starts the
watchdog timer when transitioning from logic [0] to logic [1]. This terminal should not
be allowed to be logic [1] until VDD is in regulation. This terminal has an internal passive
pull-down.
8
CS
Chip Select
(Active Low)
This terminal is an input terminal connected to a chip select output of a master
microcontroller (MCU). The MCU determines which device is addressed (selected) to
receive data by pulling the CS terminal of the selected device logic LOW, thereby
enabling SPI communication with the device. Other unselected devices on the serial
link having their CS terminals pulled up logic HIGH disregard the SPI communication
data sent. This terminal has an internal active pull-up current source and requires
CMOS logic levels.
9
SCLK
Serial Clock
This terminal is an input terminal connected to the MCU providing the required bit shift
clock for SPI communication. It transitions one time per bit transferred at an operating
frequency, fSPI, defined by the communication interface. The 50 percent duty cycle
CMOS level serial clock signal is idle between command transfers. The signal is used
to shift data into and out-of the device. This terminal has an internal active pull-down.
These terminals are the ground for the logic and analog circuitry of the device.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33892
3
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
TERMINAL FUNCTION DESCRIPTION (continued)
Terminal
Terminal Name
Formal Name
Definition
10
SI
Serial Input
This terminal is a command data input terminal connected to the SPI Serial Data
Output of the MCU or to the SO terminal of the previous device of a daisy chain of
devices. The input requires CMOS logic level signals and incorporates an internal
active pull-down. Device control is facilitated by the input's receiving the MSB first of a
serial 8-bit control command. The MCU ensures data is available upon the falling edge
of SCLK. The logic state of SI present upon the rising edge of SCLK loads that bit
command into the internal command shift register. This terminal has an internal active
pull-down.
11
VDD
Digital Drain Voltage
(Power)
12
SO
Serial Output
16
VPWR
Positive Power Supply
14
21
HS3
HS2
High-Side Outputs
Protected 35 mΩ high-side power output terminals to the load.
17, 18
19, 20
HS1 (Note 1)
HS0 (Note 2)
High-Side Outputs
Protected 10 mΩ high-side power output terminals to the load.
22
FSI
Fail-Safe Input
The value of the resistance connected between this terminal and ground determines
the state of the outputs after a Watchdog timeout occurs. Depending on the resistance
value, either all outputs are OFF or the output HSO only is ON. If the FSI terminal is
left to float up to a logic [1] level, then the outputs HS0 and HS2 will turn ON when in
the Fail-Safe state. When the FSI terminal is connected to GND, the Watchdog circuit
and Fail-Safe operation are disabled. This terminal incorporates an active internal pullup.
23
CSNS
Output Current
Monitoring
The Current Sense terminal sources a current proportional to the designated HS0–
HS3 output. That current is fed into a ground referenced resistor and its voltage is
monitored by an MCU's A/D. The channel to be monitored is selected via the SPI. This
terminal can be tri-stated through SPI.
This terminal is an external voltage input terminal used to supply power to the SPI
circuit. In the event VDD is lost, an internal supply provides power to a portion of the
logic, ensuring limited functionality of the device.
This terminal is an output terminal connected to the SPI Serial Data Input terminal of
the MCU or to the SI terminal of the next device of a daisy chain of devices. This output
will remain tri-stated (high-impedance OFF condition) so long as the CS terminal of the
device is logic HIGH. SO is only active when the CS terminal of the device is asserted
logic LOW. The generated SO output signals are CMOS logic levels. SO output data
is available on the falling edge of SCLK and transitions immediately on the rising edge
of SCLK.
This terminal connects to the positive power supply and is the source of operational
power for the device. The VPWR contact is the backside surface mount tab of the
package.
Notes
1. HS1 output (17 and 18) must be connected externally on the PCB as close as possible to the terminals.
2. HS0 output (19 and 20) must be connected externally on the PCB as close as possible to the terminals.
33892
4
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MAXIMUM RATINGS
All voltages are with respect to ground unless otherwise noted.
Rating
Symbol
Operating Voltage Range
VPWR(SS)
Unit
V
-16 to 41
Steady-State
VDD Supply Voltage
VDD
0 to 5.5
V
VIN[0:3], RST, FSI,
CSNS, SI, SCLK,
CS, FS
-0.3 to 7.0
V
SO Output Voltage (Note 3)
VSO
-0.3 to VDD +0.3
V
WAKE Input Clamp Current
ICL(WAKE)
2.5
mA
CSNS Input Clamp Current
ICL(CSNS)
10
mA
Output Current (Note 4)
IHS0, IHS1
25
A
Output Current (Note 4)
IHS2, IHS3
12
A
Output Clamp Energy (Note 5)
ECL0, ECL1
TBD
J
Output Clamp Energy (Note 5)
ECL2, ECL3
TBD
J
TSTG
-55 to 150
°C
Operating Ambient Temperature
TA
-40 to 125
°C
Operating Junction Temperature
TJ
-40 to 150
°C
Junction to Case
RθJC
<1.0
Junction to Ambient
RθJA
TBD
Input/Output Voltage (Note 3)
Freescale Semiconductor, Inc...
Value
Storage Temperature
°C/W
Thermal Resistance
V
ESD Voltage
Human Body Model (Note 6)
VESD1
±2000
Machine Model (Note 7)
VESD2
±200
TSOLDER
240
Terminal Soldering Temperature (Note 8)
°C
Notes
3. Exceeding voltage limits on IN[0:3], RST, FSI, CSNS, SI, SO, SCLK, CS, or FS terminals may cause a malfunction or permanent damage to
the device.
4. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output current
using package thermal resistance is required.
5. Active clamp energy using single-pulse method (L = 16 mH, RL = 0 Ω, VPWR = 12 V, TJ = 150°C).
6.
ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
7.
ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω) and in accordance with the system module
specification with a capacitor > 0.01 µF connected from high-side outputs to GND.
Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
8.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33892
5
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Battery Supply Voltage Range
VPWR
Fully Operational
6.0
–
27
–
–
20
mA
IPWR(on)
VPWR Operating Supply Current
Outputs ON, IHS[0:3] = 0 A
VPWR Supply Current
Freescale Semiconductor, Inc...
V
mA
IPWR(sby)
Outputs OFF, Open Load Detection Disabled, WAKE > 0.7 VDD,
RST = VLOGIC HIGH
Sleep State Supply Current (VPWR < 14 V, RST < 0.5 V, WAKE < 0.5 V)
–
–
5.0
µA
IPWR(sleep)
TJ = 25°C
–
–
10
TJ = 85°C
–
–
50
4.5
5.0
5.5
VDD Supply Voltage
VDD(on)
VDD Supply Current
IDD(on)
V
mA
No SPI Communication
–
–
1.0
3.0 MHz SPI Communication
–
–
5.0
VDD Sleep State Current
IDD(sleep)
–
–
5.0
µA
Overvoltage Shutdown Threshold
VPWR(OV)
28
32
36
V
Overvoltage Shutdown Hysteresis
VPWR(OVHYS)
0.2
0.8
1.5
V
VPWR(UV)
4.75
5.24
5.75
V
Undervoltage Hysteresis (Note 10)
VPWR(UVHYS)
–
0.25
–
V
Undervoltage Power-ON Reset
VPWR(UVPOR)
–
–
5.0
V
Undervoltage Shutdown Threshold (Note 9)
Notes
9. Output will automatically recover to instructed state when VPWR voltage is restored to normal so long as the VPWR degradation level did not
go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is supplied by VPWR and assumes that the
external VDD supply is within specification.
10.
33892
6
This applies when the undervoltage fault is not latched (IN = 0).
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUTS HS0 AND HS1
Output Drain-to-Source ON Resistance (IHS[0:1] = 10 A, TJ = 25°C)
mΩ
VPWR = 6.0 V
–
–
15
VPWR = 10 V
–
–
10
VPWR = 13 V
–
–
10
Output Drain-to-Source ON Resistance (IHS[0:1] = 10 A, TJ = 150°C)
Freescale Semiconductor, Inc...
RDS(ON)25
mΩ
RDS(ON)150
VPWR = 6.0 V
–
–
26
VPWR = 10 V
–
–
17
VPWR = 13 V
–
–
17
–
10
20
SOCH = 0
IOCH0
80
100
120
SOCH = 1
IOCH1
56
70
84
000
IOCL0
14.6
18.2
22.8
001
IOCL1
13.0
16.3
20.4
010
IOCL2
11.5
14.4
18
011
IOCL3
10.0
12.5
15.7
100
IOCL4
8.4
10.5
13.2
101
IOCL5
6.9
8.6
10.8
110
IOCL6
5.4
6.7
8.4
111
IOCL7
3.8
4.8
6.0
DICR D2 = 0
CSR0
–
1/13000
–
DICR D2 = 1
CSR1
–
1/40000
–
Output Source-to-Drain ON Resistance (Note 11)
mΩ
RSD(ON)
IHS = 15 A, TJ = 25°C, VPWR = -12 V
Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V)
A
A
Overcurrent Low Detection Levels (SOCL[2:0], 9.0 V < VPWR < 16 V)
Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V)
–
%
CSR0_ACC
Current Sense Ratio (CSR0) Accuracy
Output Current
5.0 A
-20
–
20
10 A
-14
–
14
12.5 A
-13
–
13
15 A
-12
–
12
20 A
-13
–
13
25 A
-13
–
13
Notes
11. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33892
7
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
OUTPUTS HS0 AND HS1 (continued)
%
CSR1_ACC
Current Sense Ratio (CSR1) Accuracy
Freescale Semiconductor, Inc...
Output Current
5.0 A
-25
–
25
10 A
-19
–
19
12.5 A
-18
–
18
15 A
-17
–
17
20 A
-18
–
18
25 A
-18
–
18
4.5
6.0
7.0
30
–
100
Maximum Current Sense Clamp Voltage
V
VCL(MAXCSNS)
ICSNS = 15 mA
Open Load Detection Current (Note 12)
IOLDC
Output Fault Detection Threshold
V
VOFD(THRES)
Output Programmed OFF
Output Negative Clamp Voltage
2.0
3.0
4.0
-20
–
–
150
175
190
5.0
–
20
V
VCL
0.5 A < = IHS < = 2.0 A, Output OFF
Overtemperature Shutdown (Note 13)
°C
TSD
TA = 125°C, Output OFF
Overtemperature Shutdown Hysteresis (Note 13)
TSD(HYS)
µA
°C
OUTPUTS HS2 AND HS3
Output Drain-to-Source ON Resistance (IHS[2:3] = 5.0 A, TJ = 25°C)
mΩ
RDS(ON)25
VPWR = 6.0 V
–
–
55
VPWR = 10 V
–
–
35
VPWR = 13 V
–
–
35
VPWR = 6.0 V
–
–
94
VPWR = 10 V
–
–
60
VPWR = 13 V
–
–
60
–
35
70
SOCH = 0
IOCH0
40
50
62
SOCH = 1
IOCH1
28
35
43
Output Drain-to-Source ON Resistance (IHS[2:3] = 5.0 A, TJ = 150°C)
Output Source-to-Drain ON Resistance (Note 14)
RDS(ON)150
mΩ
RDS(ON)
IHS = 15 A, TJ = 25°C, VPWR = -12 V
mΩ
Output Overcurrent High Detection Levels (9.0 V < VPWR < 16 V)
A
Notes
12. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.
13. Guaranteed by process monitoring. Not production tested.
14. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity VPWR.
33892
8
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
IOCL0
7.2
9.1
11
001
IOCL1
6.5
8.15
9.8
010
IOCL2
5.7
7.2
8.7
011
IOCL3
5.0
6.25
7.5
100
IOCL4
4.2
5.25
6.3
101
IOCL5
3.4
4.3
5.2
110
IOCL6
2.6
3.35
4.1
111
IOCL7
1.9
2.4
2.9
Unit
OUTPUTS HS2 AND HS3 (continued)
Overcurrent Low Detection Levels (SOCL[2:0], 9.0 V < VPWR < 16 V)
Freescale Semiconductor, Inc...
000
A
Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V)
–
DICR D2 = 0
CSR2
–
1/6500
–
DICR D2 = 1
CSR3
–
1/20000
–
%
CSR2_ACC
Current Sense Ratio (CSR2) Accuracy
Output Current
2.0 A
-20
–
20
5.0 A
-14
–
14
10 A
-13
–
13
12.5 A
-12
–
12
15 A
-13
–
13
20 A
-13
–
13
Current Sense Ratio (CSR3) Accuracy
%
CSR3_ACC
Output Current
5.0 A
-25
–
25
10 A
-19
–
19
12.5 A
-18
–
18
15 A
-17
–
17
20 A
-18
–
18
25 A
-18
–
18
4.5
6.0
7.0
30
–
100
2.0
3.0
4.0
-20
–
–
150
175
190
5.0
–
20
Maximum Current Sense Clamp Voltage
V
VCL(MAXCSNS)
ICSNS = 15 mA
Open Load Detection Current (Note 15)
IOLDC
Output Fault Detection Threshold
V
VOFD(THRES)
Output Programmed OFF
Output Negative Clamp Voltage
V
VCL
0.5 A < = IHS < = 2.0 A, Output OFF
°C
TSD
Overtemperature Shutdown (Note 16)
TA = 125°C, Output OFF
Overtemperature Shutdown Hysteresis (Note 16)
TSD(HYS)
µA
°C
Notes
15. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an
open load condition when the specific output is commanded OFF.
16. Guaranteed by process monitoring. Not production tested.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33892
9
Freescale Semiconductor, Inc.
STATIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
Input Logic High Voltage (Note 17)
VIH
0.7VDD
–
–
V
Input Logic Low Voltage (Note 17)
VIL
–
–
0.2VDD
V
VIN(HYS)
100
350
750
mV
Input Logic Pull-Down Current (SCLK, IN, SI, IN[0:3])
IDWN
5.0
–
20
µA
RST Input Voltage Range
VRST
4.5
5.0
5.5
V
SO, FS Tri-State Capacitance (Note 18)
CSO
–
–
20
pF
Input Logic Pull-Down Resistor (RST) and WAKE
IDWN
100
200
400
kΩ
CIN
–
4.0
12
pF
7.0
–
14
CONTROL INTERFACE
Freescale Semiconductor, Inc...
Input Logic Voltage Hysteresis (Note 17)
Input Capacitance (Note 19)
Wake Input Clamp Voltage (Note 20)
VCL(WAKE)
ICL(WAKE) < 2.5 mA
Wake Input Forward Voltage
V
VF(WAKE)
V
-2.0
ICL(WAKE) = -2.5 mA
SO High-State Output Voltage
–
-0.3
VSOH
V
0.8VDD
–
–
–
0.2
0.4
-5.0
0
5.0
5.0
–
20
RFSdis
–
0
1.0
FSI Enabled, all HS OFF
RFSoffoff
6.0
6.5
7.0
FSI Enabled, HS0 ON, HS[1:3] OFF
RFSonoff
15
17
19
FSI Enabled, HS0 and HS2 ON, HS1 and HS3 OFF
RFSonon
30
Infinite
–
IOH = 1.0 mA
FS, SO Low-State Output Voltage
VSOL
IOL = -1.6 mA
SO Tri-State Leakage Current
V
µA
ISO(LEAK)
CS > 0.7 VDD
Input Logic Pull-Up Current (Note 21)
µA
IUP
CS, VIN > 0.7 VDD
FSI Input terminal External Pull-Down Resistance (Note 22)
FSI Disabled, HS[0:3] Indeterminate
RFS
kΩ
Notes
17. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IN[0:3], and WAKE input signals. The WAKE and RST signals
may be supplied by a derived voltage referenced to VPWR.
18.
19.
20.
21.
Parameter is guaranteed by process monitoring but is not production tested.
Input capacitance of SI, CS, SCLK, RST, and WAKE. This parameter is guaranteed by process monitoring but is not production tested.
The current must be limited by a series resistance when using voltages > 7.0 V.
Pull-up current is with CS OPEN. CS has an active internal pull-up to VDD.
22.
The selection of the RFS must take into consideration the tolerance, temperature coefficient and lifetime duration to assure that the resistance
value will always be within the desired (specified) range.
33892
10
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
0.1
0.3
0.5
0.015
0.05
0.15
0.2
0.5
1.5
0.015
0.05
0.5
Unit
POWER OUTPUT TIMING HS0, HS1, HS2, AND HS3
Output Rising Slow Slew Rate A (DICR D3 = 0) (Note 23)
SRRA_SLOW
9.0 V < VPWR < 16 V
Output Rising Slow Slew Rate B (DICR D3 = 0) (Note 24)
SRRB_SLOW
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate A (DICR D3 = 1) (Note 23)
Freescale Semiconductor, Inc...
V/µs
SRRB_FAST
9.0 V < VPWR < 16 V
Output Falling Slow Slew Rate A (DICR D3 = 0) (Note 23)
V/µs
SRRA_FAST
9.0 V < VPWR < 16 V
Output Rising Fast Slew Rate B (DICR D3 = 1) (Note 24)
V/µs
V/µs
SRFA_SLOW
V/µs
0.1
9.0 V < VPWR < 16 V
Output Falling Slow Slew Rate B (DICR D3 = 0) (Note 24)
V/µs
0.015
0.175
0.6
µs
tDLY(ON)
2.0
30
200
40
460
1000
20
120
400
fPWM
–
–
300
tOCL0
tOCL1
tOCL2
tOCL3
108
155
202
434
620
806
DICR = 0, DICR = 1
µs
tDLY_SLOW(OFF)
DICR = 0
µs
tDLY_FAST(OFF)
DICR = 1
Direct Input Switching Frequency (DICR D3 = 0)
2.0
V/µs
0.05
Output Turn-OFF Delay Time in Fast Slew Rate Mode (Note 26)
1.0
SRFB_FAST
9.0 V < VPWR < 16 V
Output Turn-OFF Delay Time in Slow Slew Rate Mode (Note 26)
0.15
V/µs
0.4
Output Turn-ON Delay Time in Fast/Slow Slew Rate (Note 25)
0.05
SRFA_FAST
9.0 V < VPWR < 16 V
Output Falling Fast Slew Rate B (DICR D3 = 1) (Note 24)
0.5
SRFB_SLOW
9.0 V < VPWR < 16 V
Output Falling Fast Slew Rate A (DICR D3 = 1) (Note 23)
0.3
Overcurrent Low Detection Blanking Time (OCLT[1:0])
00
01
10
11
Hz
ms
55
75
95
0.08
0.15
0.25
Notes
23. Rise and Fall Slew Rates A measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR -3.5 V (see Figure 2, page 14). These
parameters are guaranteed by process monitoring.
24. Rise and Fall Slew Rates B measured across a 5.0 Ω resistive load at high-side output = 0.5 V to VPWR -3.5 V (see Figure 2). These
parameters are guaranteed by process monitoring.
25. Turn-ON delay time measured from rising edge of any signal (IN[0:3], SCLK, CS) that would turn the output ON to VHS = 0.5 V with RL = 5.0 Ω
resistive load.
26. Turn-OFF delay time measured from falling edge of any signal (IN[0:3], SCLK, CS) that would turn the output OFF to VHS = VPWR -0.5 V with
RL = 5.0 Ω resistive load.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33892
11
Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
tOCH
1.0
10
20
µs
CNSVAL
–
–
10
µs
00
tWDTO0
496
620
806
01
tWDTO1
248
310
403
10
tWDTO2
2000
2500
3250
11
tWDTO3
1000
1250
1625
POWER OUTPUT TIMING HS0, HS1, HS2, AND HS3 (continued)
Overcurrent High Detection Blanking Time
CS to CSNS Valid Time (Note 27)
Freescale Semiconductor, Inc...
Watchdog Timeout (WD[1:0]) (Note 28)
ms
Notes
27. Time necessary for the CSNS to be with ±5% of the targeted value.
28. Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output driven
OFF and FSI floating. The values shown are for WDR setting of [00]. The accuracy of tWDTO is consistent for all configured watchdog
timeouts.
33892
12
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 27 V, -40°C ≤ TJ ≤ 150°C unless otherwise noted. Typical
values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
fSPI
–
–
3.0
MHz
tWRST
–
50
350
ns
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (Note 30)
tCS
–
–
300
ns
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (Note 30)
tENBL
–
–
5.0
µs
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (Note 30)
tLEAD
–
50
167
ns
Required High State Duration of SCLK (Required Setup Time) (Note 30)
tWSCLKh
–
–
167
ns
Required Low State Duration of SCLK (Required Setup Time) (Note 30)
tWSCLKl
–
–
167
ns
tLAG
–
50
167
ns
SI to Falling Edge of SCLK (Required Setup Time) (Note 31)
tSI(SU)
–
25
83
ns
Falling Edge of SCLK to SI (Required Setup Time) (Note 31)
tSI(HOLD)
–
25
83
ns
–
25
50
–
25
50
SPI INTERFACE CHARACTERISTICS
Maximum Frequency of SPI Operation
Freescale Semiconductor, Inc...
Required Low State Duration for RST (Note 29)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (Note 30)
tRSO
SO Rise Time
CL = 200 pF
ns
tFSO
SO Fall Time
CL = 200 pF
ns
SI, CS, SCLK, Incoming Signal Rise Time (Note 31)
tRSI
–
–
50
ns
SI, CS, SCLK, Incoming Signal Fall Time (Note 31)
tFSI
–
–
50
ns
Time from Falling Edge of CS to SO Low Impedance (Note 32)
tSO(EN)
–
–
145
ns
Time from Rising Edge of CS to SO High Impedance (Note 33)
tSO(DIS)
–
65
145
ns
–
65
105
Time from Rising Edge of SCLK to SO Data Valid (Note 34)
0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF
Notes
29.
30.
31.
32.
33.
34.
tVALID
ns
RST low duration measured with outputs enabled and going to OFF or disabled condition.
Maximum setup time required for the 33892 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for output status data to be available for use at SO. 1.0 kΩ on pull-up on CS.
Time required for output status data to be terminated at SO. 1.0 kΩ on pull-up on CS.
Time required to obtain valid data out from SO following the rise of SCLK.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33892
13
Freescale Semiconductor, Inc.
Timing Diagrams
CS
VPWR
VPWR
- 0.5V
VVPWR
PWR -0.5 V
VPWR
- 3VV
-3.5
VPWR
SRFB
SRfB
SRRB
SRrB
SR
SRfA
FA
SRRA
SRrA
0.5V
0.5
V
tDLY(OFF)
Tdly(off)
Freescale Semiconductor, Inc...
tDLY(ON)
Tdly
(on)
Figure 2. Output Slew Rate and Time Delays
IOCHx
ILOAD2
Load
Current
ILOAD1
tOCH
IOCLx
tOCLx
Time
Figure 3. Overcurrent Shutdown
33892
14
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
IOCH0
IOCH1
IOCL0
IOCL1
IOCL2
Load
Current
IOCL3
IOCL4
IOCL5
IOCL6
Freescale Semiconductor, Inc...
IOCL7
Time
tOCH
tOCL3
tOCL2
tOCL1
tOCL0
Figure 4. Overcurrent Low and High Detection
VIH
V
IH
RSTB
RST
0.2
VDD
0.2
VDD
VIL
VIL
TwRSTB
tWRST
tENBL
tTCSB
CS
TENBL
VIH
V
0.7
VDD
0.7VDD
CS
CSB
IH
0.7
VDD
0.7VDD
tTlead
LEAD
VIL
V
IL
tRSI
tWSCLKh
TwSCLKh
TrSI
tLAG Tlag
0.70.7VDD
VDD
SCLK
SCLK
VIH
VIH
0.2 VDD
0.2VDD
VIL
V
tSI(SU)
TSIsu
IL
tWSCLKl
TwSCLKl
tSI(HOLD)
TSI(hold)
SI
SI
Don’t Care
0.7
0.7 V
VDD
DD
0.2VDD
0.2
VDD
tTfSI
FSI
VIH
V
Valid
Don’t Care
Valid
Don’t Care
IH
VIH
VIL
Figure 5. Input Timing Switching Characteristics
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33892
15
Freescale Semiconductor, Inc.
tFSI
tRSI
TrSI
TfSI
VOH
VOH
3.5 V
3.5V
50%
SCLK
SCLK
1.0VV
1.0
VOL
VOL
tSO(EN)
TdlyLH
Freescale Semiconductor, Inc...
SO
SO
0.7 V
VDD
DD
0.20.2
VDD
VDD
Low-to-High
Low
to High
TrSO
tRSO
VOH
VOH
VOL
VOL
VALID
tTVALID
SO
TfSO
tFSO
SO
VOH
VOH
VDD
VDD
High to Low 0.70.7
High-to-Low
0.2VDD
0.2 VDD
TdlyHL
VOL
VOL
tSO(DIS)
Figure 6. SCLK Waveform and Valid SO Data Delay Time
33892
16
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
The 33892 is one in a family of devices designed for lowvoltage automotive and industrial lighting and motor control
applications. Its four low RDS(ON) MOSFETs (two 10 mΩ, two
35 mΩ) can control the high sides of four separate resistive or
inductive loads or serve as high-side switches for a pair of DC
motors.
Programming, control, and diagnostics are accomplished
using a 16-bit SPI interface. Additionally, each output has its
own parallel input for PWM control if desired. The 33892 allows
the user to program via the SPI the fault current trip levels and
duration of acceptable lamp inrush or motor stall intervals. Such
programmability allows tight control of fault currents and can
protect wiring harnesses and circuit boards as well as loads.
The 33892 is packaged in a power-enhanced 10 x 10 PQFN
package with exposed tabs.
Freescale Semiconductor, Inc...
FUNCTIONAL DESCRIPTION
SPI Protocol Description
Serial Clock (SCLK)
The SPI interface has a full duplex, three-wire synchronous
data transfer with four I/O lines associated with it: Serial Input
(SI), Serial Output (SO), Serial Clock (SCLK), and Chip Select
(CS).
The SCLK terminal clocks the internal shift registers of the
33892 device. The serial input (SI) terminal accepts data into
the input shift register on the falling edge of the SCLK signal
while the serial output (SO) terminal shifts data information out
of the SO line driver on the rising edge of the SCLK signal. It is
important the SCLK terminal be in a logic low state whenever
CS makes any transition. For this reason, it is recommended the
SCLK terminal be in a logic [0] whenever the device is not
accessed (CS logic [1] state). SCLK has an internal pull-down.
When CS is logic [1], signals at the SCLK and SI terminals are
ignored and SO is tri-stated (high impedance) (see Figure 7,
page 18).
The SI/SO terminals of the 33892 follow a first-in first-out
(D15 to D0) protocol, with both input and output words
transferring the most significant bit (MSB) first. All inputs are
compatible with 5.0 V CMOS logic levels.
The SPI lines perform the following functions:
Serial Input (SI)
This is a serial interface (SI) command data input terminal.
Each SI bit is read on the falling edge of SCLK. A 16-bit stream
of serial data is required on the SI terminal, starting with D15 to
D0. The internal registers of the 33892 are configured and
controlled using a 5-bit addressing scheme described in
Table 1, page 18. Register addressing and configuration are
described in Table 2, page 19. The SI input has an internal pulldown, IDWN.
Serial Output (SO)
The SO data terminal is a tri-stateable output from the shift
register. The SO terminal remains in a high-impedance state
until the CS terminal is put into a logic [0] state. The SO data is
capable of reporting the status of the output, the device
configuration, and the state of the key inputs. The SO terminal
changes state on the rising edge of SCLK and reads out on the
falling edge of SCLK. Fault and input status descriptions are
provided in Table 9, page 22.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
Chip Select (CS)
The CS terminal enables communication with the master
microcontroller (MCU). When this terminal is in a logic [0] state,
the device is capable of transferring information to, and
receiving information from, the MCU. The 33892 latches in data
from the Input Shift registers to the addressed registers on the
rising edge of CS. The 33892 transfers status information from
the power output to the Shift register on the falling edge of CS.
The SO output driver is enabled when CS is logic [0]. CS should
transition from a logic [1] to a logic [0] state only when SCLK is
a logic [0]. CS has an internal pull-up, IUP.
For More Information On This Product,
Go to: www.freescale.com
33892
17
Freescale Semiconductor, Inc.
CSB
CS
CS
SCLK
SI
Freescale Semiconductor, Inc...
SO
D15
D14
D13
D12
D11
D10
D9
OD15 OD14 OD13 OD12 OD11 OD10 OD9
D8
OD8
D7
D6
OD7
OD6
D5
D4
OD5
OD4
D3
OD3
D2
OD2
D1
D0
OD1 OD0
Notes 1. RST is a logic [1] state during the above operation.
RSTB is in a logic H state during the above operation.
2.
D15–D0 relate to the most recent ordered entry of data into the device.
device.
DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX
IC
3. OD15–OD0 relate to the first 16 bits of ordered fault and status data out of the device.
device.
OD0, OD1, OD2, ..., and OD15 relate to the first 16 bits of ordered fault and status data out of the LUX
IC
NOTES: 1.
2.
3.
Figure 7. Single 16-Bit Word SPI Communication
Serial Input Communication
Table 1. SI Message Bit Assignment
SPI communication is accomplished using 16-bit messages.
A message is transmitted by the MCU starting with the MSB
D15 and ending with the LSB, D0 (Table 1). Each incoming
command message on the SI terminal can be interpreted using
the following bit assignments: the MSB, D15, is the watchdog
bit. In some cases, output channel selection is done with bits
D12–D11. The next three bits, D10–D8, are used to select the
command register. The remaining five bits, D4–D0, are used to
configure and control the outputs and their protection features.
MSB
Multiple messages can be transmitted in succession to
accommodate those applications where daisy chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to latch
in a message that is not 16 bits will be ignored.
The 33892 has defined registers, which are used to
configure the device and to control the state of the outputs.
Table 2, page 19, summarizes the SI registers.
33892
18
Message Bit Description
Bit Sig SI Msg Bit
LSB
D15
Watchdog in: toggled to satisfy watchdog
requirements.
D14–D15
Not used.
D12–D11
Register address bits used in some cases for
output channel selection.
D10–D8
Register address bits.
D7–D5
Not used.
D4–D1
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
D0
Used to configure the inputs, outputs, and the
device protection features and SO status
content.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Table 2. Serial Input Address and Configuration Bit Map
Freescale Semiconductor, Inc...
SI Register
SI Data
D15
D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SOA3
SOA2
SOA1
SOA0
IN_SPI1
IN_SPI0
STATR
WDIN
x
x
x
x
0
0
0
x
x
x
SOA4
OCR0
WDIN
x
x
x
0
0
0
1
x
x
x
x
IN_SPI3
IN_SPI2
OCR1
WDIN
x
x
x
1
0
0
1
x
x
x
x
CSNS EN3
CSNS EN2
CSNS EN1 CSNS EN0
SOCHLR_s
WDIN
x
x
A1
A0
0
1
0
x
x
x
x
SOCH_s
SOCL2_s
SOCL1_s
SOCL0_s
CDTOLR_s
WDIN
x
x
A1
A0
0
1
1
x
x
x
x
OL_DIS_s
OCL_DIS_s
OCLT1_s
OCLT0_s
DICR_s
WDIN
x
x
A1
A0
1
0
0
x
x
x
x
UOVR
WDIN
x
x
x
0
1
0
1
x
x
x
x
x
x
UV_DIS
OV_DIS
WDR
WDIN
x
x
x
1
1
0
1
x
x
x
x
x
x
WD1
WD0
NAR
WDIN
x
x
x
x
1
1
0
x
x
x
x
No Action (Allow Toggling of D15–WDIN)
TEST
WDIN
x
x
x
x
1
1
1
x
x
x
x
Motorola Internal Use (Test)
FAST_SR_s CSNS_high_s DIR_DIS_s
A/O_s
x=Don’t care.
s=Output selection with the bits A1A0 as defined in Table 3.
Device Register Addressing
The following section describes the possible register
addresses and their impact on device operation.
Address xx000—Status Register (STATR)
The STATR register is used to read the device status and
the various configuration register contents without disrupting
the device operation or the register contents. The register bits
D[4:0] determine the content of the first sixteen bits of SO data.
In addition to the device status, this feature provides the ability
to read the content of the OCR0, OCR1, SOCHLR, CDTOLR,
DICR, UOVR, WDR, and NAR registers. (Refer to the section
entitled Serial Output Communication (Device Status Return
Data) beginning on page 21.)
Address x0001—Output Control Register (OCR0)
The OCR0 register allows the MCU to control the ON/OFF
state of four outputs through the SPI. Incoming message bit
D[3:0] reflects the desired states of the four high-side outputs
(IN_SPI), respectively. A logic [1] enables the corresponding
output switch and a logic [0] turns it OFF.
Address x1001—Output Control Register (OCR1)
Incoming message bit D[3:0] reflects the desired channel
that will be mirrored on the Current Sense (CSNS) terminal. A
logic [1] on message bit D[3:0] enables the CSNS terminal for
the outputs HS3–HS0, respectively. In the event that the
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
current sense is enabled for multiple outputs, the current will be
summed. In the event that all bits D[3:0] are logic [0], the output
CSNS will then tri-stated. This is useful when several CSNS
terminals of several devices share the same A/D converter.
Address A1A0010—Select Overcurrent High and Low
Register (SOCHLR_s)
The SOCHLR_s register allows the MCU to configure the
output overcurrent low and high detection levels, respectively.
Each output “s” is independently selected for configuration
based on the state of the D12–D11 bits (Table 3).
Table 3. Channel Selection
A1 (D12)
A0 (D11)
HS_s
0
0
HS0
0
1
HS1
1
0
HS2
1
1
HS3
Each output can be configured to different levels. In addition
to protecting the device, this slow blow fuse emulation feature
can be used to optimize the load requirements matching
system characteristics. Bits D2–D0 set the overcurrent low
detection level to one of eight possible levels, as shown in
Table 4, page 20. Bit D3 sets the overcurrent high detection
level to one of two levels, as outlined in Table 5, page 20.
For More Information On This Product,
Go to: www.freescale.com
33892
19
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
Table 4. Overcurrent Low Detection Levels
SOCL2_s*
(D2)
SOCL1_s*
(D1)
SOCL0_s*
(D0)
0
0
0
Overcurrent Low
Detection (Amperes)
A logic [1] on bit D2 (OCL_DIS_s) disables the overcurrent
low detection feature. When disabled, there is no timeout for the
selected output and the overcurrent low detection feature is
disabled.
HS0 or HS1
HS2 or HS3
0
18.2
9.1
0
1
16.3
8.15
0
1
0
14.4
7.2
Address A1A0100—Direct Input Control Register (DICR)
0
1
1
12.5
6.25
1
0
0
10.5
5.25
1
0
1
8.6
4.3
The DICR register is used by the MCU to enable, disable, or
configure the direct IN terminal control of each output. Each
output is independently selected for configuration based on the
state bits D12–D11 (refer to Table 3, page 19).
1
1
0
6.7
3.35
1
1
1
4.8
2.4
* “_s” refers to the channel, which is selected through bits D12–D11;
refer to Table 3, page 19.
Table 5. Overcurrent High Detection
Levels
SOCH_s* (D3)
Overcurrent High Detection
(Amperes)
HS0 or HS1
HS2 or HS3
0
100
50
1
70
35
* “_s” refers to the channel, which is selected
through bits D12–D11; refer to Table 3, page 19.
Address A1A0011—Current Detection Time and Open Load
Register (CDTOLR)
The CDTOLR register is used by the MCU to determine the
amount of time the 33892 will allow an overcurrent low condition
before an output latches OFF. Each output is independently
selected for configuration based on A1A0 , which are the state of
the D12–D11 bits (refer to Table 3, page 19).
Bits D1–D0 (OCLT[1:0]_s) allow the MCU to select one of
four overcurrent fault blanking times defined in Table 6. Note
that these timeouts apply only to the overcurrent low detection
levels. If the selected overcurrent high level is reached, the
device will latch off within 20 µs.
Table 6. Overcurrent Low Detection
Blanking Time
OCLT[1:0]_s*
Timing
00
155 ms
01
620 ms
10
75 ms
11
150 µs
A logic [1] on bit D3 (OL_DIS_s) disables the open load (OL)
detection feature for the channel corresponding to the state of
bits D12–D11.
For the selected output, a logic [0] on bit D1 (DIR_DIS_s) will
enable the output for direct control. A logic [1] on bit D1 will
disable the output from direct control.
While addressing this register, if the Input was enabled for
direct control, a logic [1] for the D0 (A/O_s) bit will result in a
Boolean AND of the IN terminal with its corresponding IN_SPI
D[4:0] message bit when addressing OCR0. Similarly, a logic
[0] on the D0 terminal results in a Boolean OR of the IN terminal
to the corresponding message bits when addressing the OCR0.
This register is especially useful if several loads are required to
be independently PWM controlled. For example, the IN
terminals of several devices can be configured to operate all of
the outputs with one PWM output from the MCU. If each output
is then configured to be Boolean ANDed to its respective IN
terminal, each output can be individually turned OFF by SPI
while controlling all of the outputs, commanded on with the
single PWM output.
A logic [1] on bit D2 (CSNS_high_s) is used to select the
high ratio on the CSNS terminal for the selected output. The
default value [0] is used to select the low ratio (Table 7).
Table 7. Current Sense Ratio
CSNS_high_s* (D2)
Current Sense Ratio
HS0 or HS1
HS2 or HS3
0
1/13000
1/6500
1
1/40000
1/20000
* “_s” refers to the channel, which is selected through
bits D12–D11; refer to Table 3, page 19.
A logic [1] on bit D3 (FAST_SR_s) is used to select the high
speed slew rate for the selected output, the default value [0]
corresponds to the low speed slew rate
Address x0101—Undervoltage/Overvoltage Register
(UOVR)
The UOVR register disables the undervoltage (D1) and/or
overvoltage (D0) protection. When these two bits are [0], the
under- and overvoltage are active (default value).
* “_s” refers to the channel, which is selected through
bits D12–D11; refer to Table 3, page 19.
33892
20
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Address x1101— Watchdog Register (WDR)
The WDR register is used by the MCU to configure the
Watchdog timeout. The Watchdog timeout is configured using
bits D1 and D0. When D1 and D0 bits are programmed for the
desired watchdog timeout period (Table 8), the WDSPI bit
should be toggled as well, ensuring the new timeout period is
programmed at the beginning of a new count sequence.
Freescale Semiconductor, Inc...
Table 8. Watchdog Timeout
WD[1:0] (D1, D0)
Timing (ms)
00
620
01
310
10
2500
11
1250
Address xx110—No Action Register (NAR)
The NAR register can be used to no-operation fill SPI data
packets in a daisy-chain SPI configuration. This would allow
devices to be unaffected by commands being clocked over a
daisy-chained SPI configuration. By toggling the WD bit (D15)
the watchdog circuitry would continue to be reset while no
programming or data read back functions are being requested
from the device.
Address xx111—TEST
The TEST register is reserved for test and is not accessible
with SPI during normal operation.
SO data will represent information ranging from fault status
to register contents, user selected by writing to the STATR bits
OD4, OD3, OD2, OD1, and OD0. The value of the previous bits
SOA4 and SOA3 will determine which output the SO
information applies to for the registers which are output specific;
viz., Fault, SOCHLR, CDTOLR, and DICR registers.
Note that the SO data will continue to reflect the information
for each output (depending on the previous OD4, OD3 state)
that was selected during the most recent STATR write until
changed with an updated STATR write.
The output status register correctly reflects the status of the
STATR-selected register data at the time that the CS is pulled
to a logic [0] during SPI communication, and/or for the period of
time since the last valid SPI communication, with the following
exceptions:
• The previous SPI communication was determined to be
invalid. In this case, the status will be reported as though
the invalid SPI communication never occurred.
• Battery transients below 6.0 V resulting in an undervoltage shutdown of the outputs may result in incorrect
data loaded into the status register. The SO data
transmitted to the MCU during the first SPI communication
following an undervoltage VPWR condition should be
ignored.
• The RST terminal transition from a logic [0] to [1] while the
WAKE terminal is at logic [0] may result in incorrect data
loaded into the Status register. The SO data transmitted
to the MCU during the first SPI communication following
this condition should be ignored.
Serial Output Bit Assignment
Serial Output Communication (Device Status Return
Data)
When the CS terminal is pulled low, the output register is
loaded. Meanwhile, the data is clocked out MSB- (OD15-) first
as the new message data is clocked into the SI terminal. The
first sixteen bits of data clocking out of the SO, and following a
CS transition, is dependent upon the previously written SPI
word.
Any bits clocked out of the Serial Output (SO) terminal after
the first 16 bits will be representative of the initial message bits
clocked into the SI terminal since the CS terminal first
transitioned to a logic [0]. This feature is useful for daisy
chaining devices as well as message verification.
A valid message length is determined following a CS
transition of [0] to [1]. If there is a valid message length, the data
is latched into the appropriate registers. A valid message length
is a multiple of 16 bits. At this time, the SO terminal is tri-stated
and the fault status register is now able to accept new fault
status information.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
The 16 bits of serial output data depend on the previous
serial input message, as explained in the following paragraphs.
Table 9, page 22, summarizes SO returned data for bits OD15
through OD0.
• Bit OD15 is the MSB; it reflects the state of the Watchdog
bit from the previously clocked-in message.
• Bit OD14 remains logic [0] except when an undervoltage
condition occurred.
• Bit OD13 remains logic [0] except when an overvoltage
condition occurred.
• Bits OD[12:8] reflect the state of the bits SOA[4:0] from the
previously clocked in message.
• Bits OD[7:4] give the fault status flag of the outputs HS3,
HS2, HS1, and HS0, respectively.
• The contents of bits OD[3:0] depend on bits D[4:0] from
the most recent STATR command SOA[4:0] as explained
in the paragraphs following the table.
For More Information On This Product,
Go to: www.freescale.com
33892
21
Freescale Semiconductor, Inc.
Table 9. Serial Output Bit Map Description
Previous STATR
SO SO SO SO SO
A4 A3 A2 A1 A0
A1 A0
OD
15
OD
14
OD
13
OD
12
OD
11
OD
OD9 OD8 OD7 OD6 OD5 OD4
10
OD3
OD2
OD1
OD0
0
0
0
WDIN
UVF
OVF
SOA4
SOA3
SOA2
SOA1
SOA0
ST3
ST2
ST1
ST0
OTF_s
OCHF_s
OCLF_s
OLF_s
x
0
0
0
1
WDIN
UVF
OVF
SOA4
SOA3
SOA2
SOA1
SOA0
ST3
ST2
ST1
ST0
IN_SPI3
IN_SPI2
IN_SPI1
IN_SPI0
x
1
0
0
1
WDIN
UVF
OVF
SOA4
SOA3
SOA2
SOA1
SOA0
ST3
ST2
ST1
ST0
CSNS EN3
CSNS EN2
CSNS EN1
CSNS EN0
0
WDIN
UVF
OVF
SOA4
SOA3
SOA2
SOA1
SOA0
ST3
ST2
ST1
ST0
SOCH_s
SOCL2_s
SOCL1_s
SOCL0_s
UVF
OVF
SOA4
SOA3
SOA2
SOA1
SOA0
ST3
ST2
ST1
ST0
OL_DIS_s
OCL_DIS_s
OCLT1_s
OCLT0_s
CSNS_high_s
DIR_DIS_s
A/O_s
A1 A0
Freescale Semiconductor, Inc...
SO Returned Data
0
1
A1 A0
0
1
1
WDIN
A1 A0
1
0
0
WDIN
UVF
OVF
SOA4
SOA3
SOA2
SOA1
SOA0
ST3
ST2
ST1
ST0
Fast_SR_s
x
0
1
0
1
WDIN
UVF
OVF
SOA4
SOA3
SOA2
SOA1
SOA0
ST3
ST2
ST1
ST0
–
–
UV_DIS
OV_DIS
x
1
1
0
1
WDIN
UVF
OVF
SOA4
SOA3
SOA2
SOA1
SOA0
ST3
ST2
ST1
ST0
–
WDTO
WD1
WD0
x
0
1
1
0
WDIN
UVF
OVF
SOA4
SOA3
SOA2
SOA1
SOA0
ST3
ST2
ST1
ST0
HS2_failsaf
HS0_failsaf
WD_en
WAKE
x
1
1
1
0
WDIN
UVF
OVF
SOA4
SOA3
SOA2
SOA1
SOA0
ST3
ST2
ST1
ST0
IN3
IN2
IN1
IN0
x=Don’t care.
s=Output selection with the bits A1A0 as defined in Table 3, page 19.
Previous Address SOA[4:0]=A1A0000
Previous Address SOA[4:0]=A1A0011
The bits OD[3:0] will reflect the current state of the Fault
Register (FLTR) corresponding to the output previously
selected with the bits A1A0 (Table 10).
The returned data contains the programmed values in the
CDTOLR register for the output selected with A1A0.
Table 10. Channel-Specific Fault Register
OD3
OD2
OD1
OD0
OTF_s
OCHF_s
OCLF_s
OLF_s
s=Selection of the output.
Previous Address SOA[4:0]=A1A0100
The returned data contains the programmed values in the
DICR register for the output selected with A1A0.
Previous Address SOA[4:0]=A1A0101
Note The FS terminal reports all faults. For latched faults,
this terminal is reset by a new Switch ON command (via SPI or
direct input IN).
The returned data contains the programmed values in the
UOVR register.
Previous Address SOA[4:0]=x0001
The returned data contains the programmed values in the
WDR register. Bit OD2 (WDTO) reflects the status of the
watchdog circuitry. If WDTO bit is [1], the watchdog has timed
out and the 33892 is in Fail-Safe mode. IF WDTO is [0], the
device is in Normal mode (assuming the device is powered and
not in the Sleep mode), with the watchdog either enabled or
disabled.
Data in bits OD[3:0] contains IN_SPI[3:0]-programmed bits
for channel from HS3 to HS0, respectively.
Previous Address SOA[4:0]=x1001
Data in bits OD[3:0] contains the programmed CSNS EN[3:0]
bits for channels HS3 to HS0, respectively.
Previous Address SOA[4:0]=x1101
Previous Address SOA[4:0]=x0110
Previous Address SOA[4:0]=A1A0010
Data returned in bits OD[3:0] are programmed current values
for the overcurrent high detection level (refer to Table 5,
page 20) and the overcurrent low detection level (refer to
Table 4, page 20), corresponding to the output previously
selected with A1A0.
The returned data OD3 and OD2 contain the state of the
outputs HS2 and HS0, respectively, in case of Fail-Safe state.
This information is stated with the external resistance placed at
the FSI terminal. OD1 indicates if the watchdog is enabled or
not. OD0 returns the state of the WAKE terminal.
Previous Address SOA[4:0]=x1110
The returned data OD[3:0] reflects the state of the direct
terminals IN3 to IN0, respectively.
33892
22
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MODES OF OPERATION
The 33892 has four operating modes. They are Sleep,
Normal, Fault, and Fail-Safe. Table 11 summarizes details
contained in succeeding paragraphs.
Freescale Semiconductor, Inc...
Table 11. Fail-Safe Operation and Transitions
to Other 33892 Modes
Mode
FS
Sleep
x
0
0
x
Device is in Sleep mode. All
outputs are OFF
Normal
1
x
1
No
Normal mode. Watchdog is
active if enabled.
0
1
1
0
1
0
0
x
1
1
0
1
1
1
1
1
1
0
Fault
Wake RST WDTO
FailSafe
No
Yes
Comments
Device is currently in fault
mode. The faulted output(s) is
(are) OFF.
Watchdog has timed out and
the device is in Fail-Safe
Mode. The outputs are as
configured with the RFS
resistor connected to FSI.
RST and WAKE must be
transitioned to logic [0]
simultaneously to bring the
device out of the Fail-safe
mode or momentarily tied the
FSI pin to ground.
x = Don’t care.
Sleep Mode
The Default mode of the 33892 is the Sleep mode. This is the
state of the device after first applying battery voltage (VPWR)
prior to any I/O transitions. This is also the state of the device
when the WAKE and RST are both logic [0]. In the Sleep mode,
the output and all unused internal circuitry, such as the internal
5.0 V regulator, are off to minimize current draw. In addition, all
SPI-configurable features of the device are as if set to logic [0].
The device will transition to the Normal or Fail-Safe operating
modes based on the WAKE and RST inputs as defined in
Table 11.
Normal Mode
The 33892 is in Normal mode when:
• VPWR is within the normal voltage range.
• RST terminal is logic [1].
• No fault has occurred.
Fail-Safe Mode
Fail-Safe Mode and Watchdog
If the FSI input is not grounded, the watchdog timeout
detection is active when either the WAKE or RST input terminal
transitions from logic [0] to [1]. The WAKE input is capable of
being pulled up to VPWR with a series of limiting resistance
limiting the internal clamp current according to the specification.
The Watchdog timeout is a multiple of an internal oscillator
and is specified in the Table 8, page 21. As long as the WD bit
(D15) of an incoming SPI message is toggled within the
minimum watchdog timeout period (WDTO), based on the
programmed value of the WDR, the device will operate
normally. If an internal watchdog timeout occurs before the WD
bit, the device will revert to a Fail-Safe mode until the device is
reinitialized.
During the Fail-Safe mode, the outputs will be ON or OFF
depending upon the resistor RFS connected to the FSI pin,
regardless of the state of the various direct inputs and modes
(Table 12).
Table 12. Output State During
Fail-Safe Mode
RFS (kΩ)
High-Side State
0
Fail-Safe Mode Disabled
6.0
All HS OFF
15
HS0 ON
HS[1:3] OFF
30
HS0 and HS2 ON
HS1 and HS3 OFF
In the Fail-Safe mode, the SPI register content is retained
except for overcurrent high and low detection levels and timing,
which are reset to their default value (SOCL, SOCH, and
OCTL). Then the watchdog, overvoltage, overtemperature, and
overcurrent circuitry (with default value) are fully operational.
The Fail-Safe mode can be detected by monitoring the
WDTO bit D2 of the WD register. This bit is logic [1] when the
device is in Fail-Safe mode. The device can be brought out of
the Fail-Safe mode by transitioning the WAKE and RST pins
from logic [1] to logic [0] or forcing the FSI pin to logic [0].
Table 11 summarizes the various methods for resetting the
device from the latched Fail-Safe mode.
If the FSI pin is tied to GND, the Watchdog Fail-Safe
operation is disabled.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33892
23
Freescale Semiconductor, Inc.
Loss of VDD
If the external 5.0 V supply is not within specification, or even
disconnected, all register content is reset. The outputs can still
be driven by the direct inputs IN[0:3]. The 33892 uses the
battery input to power the output MOSFET-related current
sense circuitry and any other internal logic providing fail-safe
device operation with no VDD supplied. In this state, the
watchdog, overvoltage, overtemperature, and overcurrent
circuitry are fully operational with default values.
level then returns above 5.75 V, the 33892 can be returned to
the state that it was in prior to the low VPWR excursion. Once the
output latches OFF, the outputs must be turned OFF and ON
again to re-enable them. In the case IN[1:0]=0, this fault is nonlatched.
The undervoltage protection can be disabled through SPI (bit
UV_DIS). When disabled, the returned SO bit OD14 still reflects
any undervoltage condition (undervoltage warning).
Open Load Fault (Non-Latching)
Fault Mode
Freescale Semiconductor, Inc...
The 33892 indicates the faults below as they occur by driving
the FS terminal to [0]:
•
•
•
•
Overtemperature fault
Overvoltage and Undervoltage fault
Open load fault
Overcurrent fault (high and low)
The FS terminal will automatically return to [1] when the fault
condition is removed, except for overcurrent and in some cases
undervoltage.
Fault information is retained in the fault register and is
available (and reset) via the SO terminal during the first valid
SPI communication (refer to Table 10, page 22).
Overtemperature Fault (Non-Latching)
The 33892 incorporates overtemperature detection and
shutdown circuitry in the output structure. Overtemperature
detection is enabled when the output is in the ON state.
For the output, an overtemperature fault (OTF) condition
results in the faulted output turning OFF until the temperature
falls below the TSD(HYS). This cycle will continue indefinitely until
action is taken by the MCU to shut OFF the output, or until the
offending load is removed.
The 33892 incorporates open load detection circuitry on the
output. Output open load fault (OLF) is detected and reported
as a fault condition when the output is disabled (OFF). The
open load fault is detected and latched into the status register
after the internal gate voltage is pulled low enough to turn OFF
the output. The OLF fault bit is set in the status register. If the
open load fault is removed, the status register will be cleared
after reading the register.
The open load protection can be disabled trough SPI (bit
OL_DIS).
Overcurrent Fault (Latching)
The 33892 has eight programmable overcurrent low
detection levels (IOCL) and two programmable overcurrent high
detection levels (IOCH) for maximum device protection. The two
selectable, simultaneously active overcurrent detection levels,
defined by IOCH and IOCL, are illustrated in Figure 4, page 15.
The eight different overcurrent low detection levels (IOCL0,
IOCL1, IOCL2, IOCL3, IOCL4, IOCL5, IOCL6, and IOCL7) are
illustrated in Figure 4.
If the load current level ever reaches the selected
overcurrent low detection level and the overcurrent condition
exceeds the programmed overcurrent time period (tOCx), the
device will latch the output OFF.
When experiencing this fault, the OTF fault bit will be set in
the status register and cleared after either a valid SPI read or a
power reset of the device.
If, at any time, the current reaches the selected IOCH level,
then the device will immediately latch the fault and turn OFF the
output, regardless of the selected tOCLx driver.
Overvoltage Fault (Non-Latching)
For both cases, the device output will stay off indefinitely until
the device is commanded OFF and then ON again.
The 33892 shuts down the output during an overvoltage fault
(OVF) condition on the VPWR terminal. The output remains in
the OFF state until the overvoltage condition is removed. When
experiencing this fault, the OVF fault bit is set in the bit D1 and
cleared after either a valid SPI read or a power reset of the
device.
The overvoltage protection can be disabled through SPI (bit
OV_DIS). When disabled, the returned SO bit OD13 still reflects
any overvoltage condition (overvoltage warning).
Undervoltage Shutdown (Latching or Non-Latching)
The output latches OFF at some battery voltage between
4.75 V and 5.75 V. As long as the VDD level stays within the
normal specified range, the internal logic states within the
device will be sustained. This ensures that when the battery
33892
24
Reverse Battery
The output survives the application of reverse voltage as low
as -16 V. Under these conditions, the output’s gate is enhanced
to keep the junction temperature less than 150°C. The ON
resistance of the output is fairly similar to that in the Normal
mode. No additional passive components are required.
Ground Disconnect Protection
In the event the 33892 ground is disconnected from load
ground, the device protects itself and safely turns OFF the
output regardless of the state of the output at the time of
disconnection.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
PACKAGE DIMENSIONS
PNC SUFFIX
24-TERMINAL POWER QFN
NON-LEADED PACKAGE
CASE 1558-02
ISSUE A
SHEET 1 OF 2
10
A
DETAIL G
5
Freescale Semiconductor, Inc...
M
2X
10
2
0.1 C
1
11
24
13
22
14
21
5
10
PIN 1
INDEX AREA
17
18
19
20
M
2X
B
0.1 C
PIN NUMBER
REF. ONLY
5.85
PIN NUMBER
REF. ONLY
4.95
4.65
VIEW A
0.1 C A B
1
2
10
24
11
22
13
2X
3.0
2.7
0.1 C A B
0.65
15
3.2
2.525
14
21
1.375
4.45
4.05
2.45
2.05
16
0.1 C A B
(0.25)
2X
2X 1.43
0.93
20
2X 1.3
0.8
(0.25)
19
18
(0.25)
(0.75)
(0.25)
2X
(0.1)
(1.25)
0.5
17
2.3
1.8
(0.25)
2.2
1.8
0.1 C A B
7.2
6.8
2X
0.1 C A B
9.70
9.30
1.65
1.35
0.1 C A B
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. THE COMPLETE JEDEC DESIGNATOR FOR THIS
PACKAGE IS: HF-PQFP-N.
4. COPLANARITY APPLIES TO LEADS AND CORNER
LEADS.
5. METAL PADS CONNECTED TO THE GND.
6. MINIMUM METAL GAP SHOULD BE 0.25MM.
0.1 C A B
VIEW M M
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33892
25
Freescale Semiconductor, Inc.
PNC SUFFIX
24-TERMINAL POWER QFN
NON-LEADED PACKAGE
CASE 1558-02
ISSUE A
SHEET 2 OF 2
0.1 C
2.2
2.0
2.20
1.95
4
Freescale Semiconductor, Inc...
0.05 C
0.05
0.00
(0.65)
(0.4)
C
SEATING
PLANE
DETAIL G
VIEW ROTATED 90˚ CW
3.5
9X
16X
0.65
0.325
2X
0.47
0.33
0.1 M C A B
0.05 M C
1.20
0.95
6X
1.20
0.95
(0.05)
10
(0.2)
8X
0.90
0.65
11
0.3±0.2 5
X0.3±0.2
0.1 C A B
3.025
2 PLACES
0.25±0.2 5
X0.25±0.2
0.1 C A B
2.5
2 PLACES
1.8
1.3
2.0
1.6
1.0
0.6
(0.25)
2.8
2.6
0.6
0.2
2 PLACES
VIEW A
33892
26
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On
This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
NOTES
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33892
27
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do
vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer
application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or
sustain life, or for any other appl ication in which the failure of the Motorola product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its
officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.
MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their
respective owners.
© Motorola, Inc. 2004
HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED: Motorola Literature Distribution: P.O. Box 5405, Denver, Colorado 80217.
1-303-675-2140 or 1-800-441-2447
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1 Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan.
81-3-3440-3569
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tao Po, N.T.,
Hong Kong. 852-26668334
TECHNICAL INFORMATION CENTER: 1-800-521-6274
For More Information On This Product,
Go to: www.freescale.com
MC33892