FUJITSU MB91F467DB

FUJITSU MICROELECTRONICS
DATA SHEET
DS07-16612-2E
32-bit Microcontroller
CMOS
FR60 MB91460D Series
MB91F465DA, MB91F467DA/F467DB
■ DESCRIPTION
MB91460D series is a line of general-purpose 32-bit RISC microcontrollers designed for embedded control
applications which require high-speed real-time processing, such as consumer devices and on-board vehicle
systems. This series uses the FR60 CPU, which is compatible with the FR family* of CPUs.
This series contains the LIN-USART and CAN controllers.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Microelectronics Limited.
■ FEATURES
1. FR60 CPU core
•
•
•
•
•
•
•
•
32-bit RISC, load/store architecture, five-stage pipeline
16-bit fixed-length instructions (basic instructions)
Instruction execution speed: 1 instruction per cycle
Instructions including memory-to-memory transfer, bit manipulation, and barrel shift instructions: Instructions
suitable for embedded applications
Function entry/exit instructions and register data multi-load store instructions : Instructions supporting C
language
Register interlock function: Facilitating assembly-language coding
Built-in multiplier with instruction-level support
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
Interrupts (save PC/PS) : 6 cycles (16 priority levels)
(Continued)
For the information for microcontroller supports, see the following web site.
This web site includes the "Customer Design Review Supplement" which provides the latest cautions on
system development and the minimal requirements to be checked to prevent problems before the system
development.
http://edevice.fujitsu.com/micom/en-support/
Copyright©2009 FUJITSU MICROELECTRONICS LIMITED All rights reserved
2009.8
MB91460D Series
(Continued)
• Harvard architecture enabling program access and data access to be performed simultaneously
• Instructions compatible with the FR family
2. Internal peripheral resources
• General-purpose ports : Maximum 170 ports
• DMAC (DMA Controller)
Maximum of 5 channels able to operate simultaneously. (External to external : 1 channel)
3 transfer sources (external pin/internal peripheral/software)
Activation source can be selected using software.
Addressing mode specifies full 32-bit addresses (increment/decrement/fixed)
Transfer mode (demand transfer/burst transfer/step transfer/block transfer)
Fly-by transfer support (between external I/O and memory)
Transfer data size selectable from 8/16/32-bit
Multi-byte transfer enabled (by software)
DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H)
• A/D converter (successive approximation type)
10-bit resolution: 24 channels
Conversion time: minimum 1 μs
• External interrupt inputs : 14 channels
8 channels shared with CAN RX or I2C pins
• Bit search module (for REALOS)
Function to search from the MSB (most significant bit) for the position of the first “0”, “1”, or changed bit in a word
• LIN-USART (full duplex double buffer): 5 channels
Clock synchronous/asynchronous selectable
Sync-break detection
Internal dedicated baud rate generator
• I2C bus interface (supports 400 kbps): 3 channels
Master/slave transmission and reception
Arbitration function, clock synchronization function
• CAN controller (C-CAN): 3 channels
Maximum transfer speed: 1 Mbps
32 transmission/reception message buffers
• Stepper motor controller : 6 channels
4 high current output to each channel
2 synchronized PWMs per channel (8/10-bit)
• Sound generator : 1 channel
Tone frequency : PWM frequency divide-by-two (reload value + 1)
• Alarm comparator : 1 channel
Monitor external voltage
Generate an interrupt in case of voltage lower/higher than the defined thresholds (reference voltage)
• 16-bit PPG timer : 12 channels
• 16-bit PFM timer : 1 channel
• 16-bit reload timer: 8 channels
• 16-bit free-run timer: 8 channels (1 channel each for ICU and OCU)
• Input capture: 8 channels (operates in conjunction with the free-run timer)
• Output compare: 4 channels (operates in conjunction with the free-run timer)
• Up/Down counter: 3 channels (3*8-bit or 1*16-bit + 1*8-bit)
• Watchdog timer
(Continued)
2
DS07-16612-2E
MB91460D Series
(Continued)
• Real-time clock
• Low-power consumption modes : Sleep/stop mode function
• Supply Supervisor: Low voltage detection circuit for external VDD5 and internal 1.8V core voltage
• Clock supervisor
Monitors the sub-clock (32 kHz) and the main clock (4 MHz) , and switches to a recovery clock (CR oscillator,
etc.) when the oscillations stop.
• Clock modulator
• Clock monitor
• Sub-clock calibration
Corrects the real-time clock timer when operating with the 32 kHz or CR oscillator
• Main oscillator stabilization timer
Generates an interrupt in sub-clock mode after the stabilization wait time has elapsed on the 23-bit stabilization
wait time counter
• Sub-oscillator stabilization timer
Generates an interrupt in main clock mode after the stabilization wait time has elapsed on the 15-bit stabilization
wait time counter
3. Package and technology
•
•
•
•
Package : QFP-208
CMOS 0.18 μm technology
Power supply range 3 V to 5 V (1.8 V internal logic provided by a step-down voltage converter)
Operating temperature range: between − 40°C and + 105°C
DS07-16612-2E
3
MB91460D Series
■ PRODUCT LINEUP
MB91V460A
MB91F465DA
MB91F467DA
MB91F467DB
Max. core frequency (CLKB)
80MHz
100MHz
96MHz
Feature
Max. resource frequency (CLKP)
40MHz
50MHz
48MHz
Max. external bus freq. (CLKT)
40MHz
50MHz
48MHz
Max. CAN frequency (CLKCAN)
20MHz
50MHz
48MHz
Max. FlexRay frequency (SCLK)
-
-
-
0.35μm
0.18μm
0.18μm
yes
yes
yes
yes (disengageable)
yes
yes
yes
yes
yes
Technology
Watchdog timer
Watchdog timer (RC osc. based)
Bit Search
Reset input (INITX)
yes
yes
yes
Hardware Standby input (HSTX)
yes
no
no
Clock Modulator
yes
yes
yes
Clock Monitor
yes
yes
yes
Low Power Mode
yes
yes
yes
DMA
5 ch
5 ch
5 ch
MAC (uDSP)
MMU/MPU
Flash memory
no
no
no
MPU (16 ch) 1)
MPU (8 ch) 1)
MPU (8 ch) 1)
Emulation SRAM 32bit read data
544 KByte
1088 KByte
Satellite Flash memory
-
no
no
Flash Protection
-
yes
yes
D-RAM
64 KByte
32 KByte
32 KByte
ID-RAM
64 KByte
16 KByte
32 KByte
Flash-Cache (Instruction cache)
16 KByte
8 KByte
8 KByte
4 KByte fixed
4 KByte
4 KByte
Boot-ROM / BI-ROM
RTC
1 ch
1 ch
1 ch
Free Running Timer
8 ch
8 ch
8 ch
ICU
8 ch
8 ch
8 ch
OCU
8 ch
4 ch
4 ch
Reload Timer
8 ch
8 ch
8 ch
PPG 16-bit
16 ch
12 ch
12 ch
PFM 16-bit
1 ch
1 ch
1 ch
Sound Generator
1 ch
1 ch
1 ch
4 ch (8-bit) / 2 ch (16-bit)
3 ch (8-bit) / 1 ch (16-bit)
3 ch (8-bit) / 1 ch (16-bit)
Up/Down Counter (8/16-bit)
C_CAN
LIN-USART
I2C (400k)
FR external bus
4
6 ch (128msg)
3 ch (32msg)
3 ch (32msg)
4 ch + 4 ch FIFO + 8 ch
1 ch + 4 ch FIFO
1 ch + 4 ch FIFO
4 ch
3 ch
3 ch
yes (32bit addr, 32bit data)
yes (26bit addr, 32bit data)
yes (26bit addr, 32bit data)
DS07-16612-2E
MB91460D Series
MB91V460A
MB91F465DA
MB91F467DA
MB91F467DB
External Interrupts
16 ch
14 ch
14 ch
NMI Interrupts
1 ch
-
-
SMC
6 ch
6 ch
6 ch
LCD controller (40x4)
1 ch
-
-
Feature
ADC (10 bit)
32 ch
24 ch
24 ch
Alarm Comparator
2 ch
1 ch
1 ch
Supply Supervisor
(low voltage detection)
yes
yes
yes
Clock Supervisor
yes
yes
yes
Main clock oscillator
4MHz
4MHz
4MHz
Sub clock oscillator
32kHz
32kHz
32kHz
RC Oscillator
100kHz
100kHz / 2MHz
100kHz / 2MHz
PLL
x 20
x 25
x 24
DSU4
yes
EDSU
Supply Voltage
Regulator
Power Consumption
yes (32 BP)
*1
yes (16 BP)
*1
yes (16 BP) *1
3V / 5V
3V / 5V
3V / 5V
yes
yes
yes
n.a.
<1W
<1W
Temperature Range (Ta)
0..70 C
-40..105 C
-40..105 C
Package
BGA660
QFP208
QFP208
Power on to PLL run
< 20 ms
< 20 ms
< 20 ms
Flash Download Time
n.a.
< 5 sec. typical
< 6 sec typical
*1 : MPU channels use EDSU breakpoint registers (shared operation between MPU and EDSU).
DS07-16612-2E
5
MB91460D Series
■ PIN ASSIGNMENT
1. MB91F465DA, MB91F467Dx
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
VDD35
P02_7/D15
P02_6/D14
P02_5/D13
P02_4/D12
P02_3/D11
P02_2/D10
P02_1/D9
P02_0/D8
P03_7/D7
P03_6/D6
P03_5/D5
P03_4/D4
P03_3/D3
P03_2/D2
P03_1/D1
P03_0/D0
P13_2/DEOTX0/DEOP0
P13_1/DACKX0
P13_0/DREQ0
VSS5
P25_7/SMC2M5
P25_6/SMC2P5
P25_5/SMC1M5
P25_4/SMC1P5
HVSS5
HVDD5
P25_3/SMC2M4
P25_2/SMC2P4
P25_1/SMC1M4
P25_0/SMC1P4
P26_7/SMC2M3/AN31
P26_6/SMC2P3/AN30
P26_5/SMC1M3/AN29
P26_4/SMC1P3/AN28
HVSS5
HVDD5
P26_3/SMC2M2/AN27
P26_2/SMC2P2/AN26
P26_1/SMC1M2/AN25
P26_0/SMC1P2/AN24
P27_7/SMC2M1/AN23
P27_6/SMC2P1/AN22
P27_5/SMC1M1/AN21
P27_4/SMC1P1/AN20
HVSS5
HVDD5
P27_3/SMC2M0/AN19
P27_2/SMC2P0/AN18
P27_1/SMC1M0/AN17
P27_0/SMC1P0/AN16
VSS5
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
QFP-208
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VDD5
P29_7/AN7
P29_6/AN6
P29_5/AN5
P29_4/AN4
P29_3/AN3
P29_2/AN2
P29_1/AN1
P29_0/AN0
ALARM_0
AVCC5
AVRH5
AVSS5
P16_7/PPG15/ATGX
P16_6/PPG14/PFM
P16_5/PPG13/SGO
P16_4/PPG12/SGA
P16_3/PPG11
P16_2/PPG10
P16_1/PPG9
P16_0/PPG8
P17_7/PPG7
P17_6/PPG6
P17_5/PPG5
P17_4/PPG4
VSS5
VDD5
P14_7/ICU7/TIN7/TTG7/15
P14_6/ICU6/TIN6/TTG6/14
P14_5/ICU5/TIN5/TTG5/13
P14_4/ICU4/TIN4/TTG4/12
P14_3/ICU3/TIN3/TTG11
P14_2/ICU2/TIN2/TTG10
P14_1/ICU1/TIN1/TTG9
P14_0/ICU0/TIN0/TTG8
P15_3/OCU3/TOT3
P15_2/OCU2/TOT2
P15_1/OCU1/TOT1
P15_0/OCU0/TOT0
P18_6/SCK7/ZIN3/CK7
P18_5/SOT7/BIN3
P18_4/SIN7/AIN3
P18_2/SCK6/ZIN2/CK6
P18_1/SOT6/BIN2
P18_0/SIN6/AIN2
P19_6/SCK5/CK5
P19_5/SOT5
P19_4/SIN5
P19_2/SCK4/CK4
P19_1/SOT4
P19_0/SIN4
VSS5
VSS5
P08_6/BRQ
P08_7/RDY
P09_0/CSX0
P09_1/CSX1
P09_2/CSX2
P09_3/CSX3
P09_6/CSX6
P09_7/CSX7
P10_1/ASX
P10_2/BAAX
P10_3/WEX
P10_4/MCLKO
P10_5/MCLKI
P10_6/MCLKE
MONCLK
VSS5
MD_2
MD_1
MD_0
INITX
X1A
X0A
X1
X0
VDD5
VSS5
VCC18C
VDD5R
VDD5R
P24_0/INT0
P24_1/INT1
P24_2/INT2
P24_3/INT3
P24_4/INT4/SDA2
P24_5/INT5/SCL2
P24_6/INT6/SDA3
P24_7/INT7/SCL3
P23_0/RX0/INT8
P23_1/TX0
P23_2/RX1/INT9
P23_3/TX1
P23_4/RX2/INT10
P23_5/TX2
P22_0/INT12
P22_2/INT13
P22_4/SDA0/INT14
P22_5/SCL0
P20_0/SIN2/AIN0
P20_1/SOT2/BIN0
P20_2/SCK2/ZIN0/CK2
VDD5
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
VSS5
P01_0/D16
P01_1/D17
P01_2/D18
P01_3/D19
P01_4/D20
P01_5/D21
P01_6/D22
P01_7/D23
P00_0/D24
P00_1/D25
P00_2/D26
P00_3/D27
P00_4/D28
P00_5/D29
P00_6/D30
P00_7/D31
P07_0/A0
P07_1/A1
P07_2/A2
P07_3/A3
P07_4/A4
P07_5/A5
P07_6/A6
P07_7/A7
VDD35
VSS5
P06_0/A8
P06_1/A9
P06_2/A10
P06_3/A11
P06_4/A12
P06_5/A13
P06_6/A14
P06_7/A15
P05_0/A16
P05_1/A17
P05_2/A18
P05_3/A19
P05_4/A20
P05_5/A21
P05_6/A22
P05_7/A23
P04_0/A24
P04_1/A25
P08_0/WRX0
P08_1/WRX1
P08_2/WRX2
P08_3/WRX3
P08_4/RDX
P08_5/BGRNTX
VDD35
FPT-208P-M04
6
DS07-16612-2E
MB91460D Series
■ PIN DESCRIPTION
1. MB91F465DA, MB91F467Dx
Pin no.
2 to 9
10 to 17
18 to 25
28 to 35
36 to 43
44, 45
46 to 49
Pin name
P01_0 to P01_7
D16 to D23
P00_0 to P00_7
D24 to D31
P07_0 to P07_7
A0 to A7
P06_0 to P06_7
A8 to A15
P05_0 to P05_7
A16 to A23
P04_0, P04_1
A24, A25
P08_0 to P08_3
WRX0 to WRX3
P08_4
50
RDX
P08_5
51
BGRNTX
P08_6
54
BRQ
P08_7
55
56 to 59
60, 61
RDY
P09_0 to P09_3
CSX0 to CSX3
P09_6, P09_7
CSX6, CSX7
62
63
64
65
P10_1
ASX
P10_2
BAAX
P10_3
WEX
P10_4
MCLKO
I/O
I/O circuit
type*
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
I/O
A
Function
General-purpose input/output ports
Signal pins of external data bus (bit16 to bit23)
General-purpose input/output ports
Signal pins of external data bus (bit24 to bit31)
General-purpose input/output ports
Signal pins of external address bus (bit0 to bit7)
General-purpose input/output ports
Signal pins of external address bus (bit8 to bit15)
General-purpose input/output ports
Signal pins of external address bus (bit16 to bit23)
General-purpose input/output ports
Signal pins of external address bus (bit24, bit25)
General-purpose input/output ports
External write strobe output pins
General-purpose input/output port
External read strobe output pin
General-purpose input/output port
External bus release reception output pin
General-purpose input/output port
External bus release request input pin
General-purpose input/output port
External ready input pin
General-purpose input/output ports
Chip select output pins
General-purpose input/output ports
Chip select output pins
General-purpose input/output port
Address strobe output pin
General-purpose input/output port
Burst address advance output pin
General-purpose input/output port
Write enable output pin
General-purpose input/output port
Clock output pin for memory
(Continued)
DS07-16612-2E
7
MB91460D Series
(Continued)
Pin no.
66
67
Pin name
P10_5
MCLKI
P10_6
MCLKE
I/O
I/O circuit
type*
I/O
A
I/O
A
Function
General-purpose input/output port
Clock input pin for memory
General-purpose input/output port
Clock enable signal pin for memory
68
MONCLK
O
M
70
MD_2
I
G
71
MD_1
I
G
72
MD_0
I
G
73
INITX
I
H
External reset input pin
74
X1A
⎯
J2
Sub clock (oscillation) output
75
X0A
⎯
J2
Sub clock (oscillation) input
76
X1
⎯
J1
Clock (oscillation) output
77
X0
⎯
J1
Clock (oscillation) input
I/O
A
83 to 86
P24_0 to P24_3
INT0 to INT3
P24_4
87
88
89
90
91
INT4
I/O
C
General-purpose input/output ports
External interrupt input pins
External interrupt input pin
SDA2
I2C bus DATA input/output pin
P24_5
General-purpose input/output port
INT5
I/O
C
External interrupt input pin
SCL2
I2C bus clock input/output pin
P24_6
General-purpose input/output port
INT6
I/O
C
External interrupt input pin
SDA3
I2C bus DATA input/output pin
P24_7
General-purpose input/output port
INT7
I/O
C
External interrupt input pin
SCL3
I2C bus clock input/output pin
P23_0
General-purpose input/output port
RX0
I/O
A
P23_1
TX0
RX1
INT9
RX input pin of CAN0
External interrupt input pin
I/O
A
P23_2
93
Mode setting pins
General-purpose input/output port
INT8
92
Clock monitor pin
General-purpose input/output port
TX output pin of CAN0
General-purpose input/output port
I/O
A
RX input pin of CAN1
External interrupt input pin
(Continued)
8
DS07-16612-2E
MB91460D Series
(Continued)
Pin no.
94
Pin name
P23_3
TX1
I/O
I/O circuit
type*
I/O
A
P23_4
95
RX2
97
98
P23_5
TX2
P22_0
INT12
P22_2
INT13
I/O
A
SDA0
I/O
A
I/O
A
I/O
A
P22_5
SCL0
I/O
C
SIN2
I/O
C
I/O
A
I/O
A
ZIN0
107
P19_0
SIN4
P19_1
SOT4
I/O
A
SCK4
CK4
I2C bus data input/output pin
General-purpose input/output port
I2C bus clock input/output pin
Data input pin of USART2
Data output pin of USART2
Clock input/output pin of USART2
Up/down counter input pin
External clock input pin of free-run timer 2
I/O
A
I/O
A
P19_2
108
External interrupt input pin
General-purpose input/output port
CK2
106
General-purpose input/output port
Up/down counter input pin
P20_2
SCK2
External interrupt input pin
General-purpose input/output port
BIN0
103
General-purpose input/output port
Up/down counter input pin
P20_1
SOT2
TX output pin of CAN2
General-purpose input/output port
AIN0
102
General-purpose input/output port
External interrupt input pin
P20_0
101
RX input pin of CAN2
General-purpose input/output port
INT14
100
TX output pin of CAN1
External interrupt input pin
P22_4
99
General-purpose input/output port
General-purpose input/output port
INT10
96
Function
General-purpose input/output port
Data input pin of USART4
General-purpose input/output port
Data output pin of USART4
General-purpose input/output port
I/O
A
Clock input/output pin of USART4
External clock input pin of free-run timer 4
(Continued)
DS07-16612-2E
9
MB91460D Series
(Continued)
Pin no.
109
110
Pin name
P19_4
SIN5
P19_5
SOT5
I/O
I/O circuit
type*
I/O
A
I/O
A
P19_6
111
SCK5
I/O
A
I/O
A
I/O
A
ZIN2
I/O
A
I/O
A
General-purpose input/output port
I/O
A
BIN3
SCK7
ZIN3
General-purpose input/output port
I/O
A
CK7
OCU0 to OCU3
I/O
A
General-purpose input/output ports
ICU0 to ICU7
TTG8 to TTG11,
TTG4/12 to
TTG7/15
Output compare output pins
Reload timer output pins
P14_0 to P14_7
TIN0 to TIN7
Up/down counter input pin
General-purpose input/output ports
TOT0 to TOT3
122 to 129
Clock input/output pin of USART7
External clock input pin of free-run timer 7
P15_0 to P15_3
118 to 121
Data output pin of USART7
Up/down counter input pin
P18_6
117
Data input pin of USART7
Up/down counter input pin
P18_5
SOT7
Up/down counter input pin
General-purpose input/output port
AIN3
116
Clock input/output pin of USART6
External clock input pin of free-run timer 6
P18_4
SIN7
Data output pin of USART6
General-purpose input/output port
CK6
115
Data input pin of USART6
Up/down counter input pin
P18_2
SCK6
Clock input/output pin of USART5
General-purpose input/output port
BIN2
114
Data output pin of USART5
Up/down counter input pin
P18_1
SOT6
General-purpose input/output port
General-purpose input/output port
AIN2
113
Data input pin of USART5
External clock input pin of free-run timer 5
P18_0
SIN6
General-purpose input/output port
General-purpose input/output port
CK5
112
Function
Input capture input pins
I/O
A
External trigger input pins of reload timer
External trigger input pins of PPG timer
(Continued)
10
DS07-16612-2E
MB91460D Series
(Continued)
Pin no.
132 to 135
136 to 139
Pin name
P17_4 to P17_7
PPG4 to PPG7
P16_0 to P16_3
PPG8 to PPG11
I/O
I/O circuit
type*
I/O
A
I/O
A
P16_4
140
PPG12
141
I/O
A
I/O
A
SGO output pin of sound generator
P16_6
General-purpose input/output port
ALARM_0
P29_0 to P29_7
AN0 to AN7
I/O
A
161
164
SMC1P0
Output pin of PPG timer
Pulse frequency modulator output pin
General-purpose input/output port
I/O
A
PPG timer output pin
A/D converter external trigger input pin
I
N
I/O
B
P27_0
160
Output pin of PPG timer
SGO
ATGX
159
Output pin of PPG timer
General-purpose input/output port
PPG15
158
PPG timer output pins
P16_5
P16_7
148 to 155
General-purpose input/output ports
General-purpose input/output port
PFM
147
Output pins of PPG timer
SGA output pin of sound generator
PPG14
143
General-purpose input/output ports
SGA
PPG13
142
Function
Alarm comparator input pin
General-purpose input/output ports
Analog input pins of A/D converter
General-purpose input/output port
I/O
F
Controller output pin of Stepper motor
AN16
Analog input pin of A/D converter
P27_1
General-purpose input/output port
SMC1M0
I/O
F
Controller output pin of Stepper motor
AN17
Analog input pin of A/D converter
P27_2
General-purpose input/output port
SMC2P0
I/O
F
Controller output pin of Stepper motor
AN18
Analog input pin of A/D converter
P27_3
General-purpose input/output port
SMC2M0
I/O
F
Controller output pin of Stepper motor
AN19
Analog input pin of A/D converter
P27_4
General-purpose input/output port
SMC1P1
AN20
I/O
F
Controller output pin of Stepper motor
Analog input pin of A/D converter
(Continued)
DS07-16612-2E
11
MB91460D Series
(Continued)
Pin no.
Pin name
I/O
I/O circuit
type*
P27_5
165
166
167
168
169
170
171
174
175
176
177
SMC1M1
Function
General-purpose input/output port
I/O
F
Controller output pin of Stepper motor
AN21
Analog input pin of A/D converter
P27_6
General-purpose input/output port
SMC2P1
I/O
F
Controller output pin of Stepper motor
AN22
Analog input pin of A/D converter
P27_7
General-purpose input/output port
SMC2M1
I/O
F
Controller output pin of Stepper motor
AN23
Analog input pin of A/D converter
P26_0
General-purpose input/output port
SMC1P2
I/O
F
Controller output pin of Stepper motor
AN24
Analog input pin of A/D converter
P26_1
General-purpose input/output port
SMC1M2
I/O
F
Controller output pin of Stepper motor
AN25
Analog input pin of A/D converter
P26_2
General-purpose input/output port
SMC2P2
I/O
F
Controller output pin of Stepper motor
AN26
Analog input pin of A/D converter
P26_3
General-purpose input/output port
SMC2M2
I/O
F
Controller output pin of Stepper motor
AN27
Analog input pin of A/D converter
P26_4
General-purpose input/output port
SMC1P3
I/O
F
Controller output pin of Stepper motor
AN28
Analog input pin of A/D converter
P26_5
General-purpose input/output port
SMC1M3
I/O
F
Controller output pin of Stepper motor
AN29
Analog input pin of A/D converter
P26_6
General-purpose input/output port
SMC2P3
I/O
F
Controller output pin of Stepper motor
AN30
Analog input pin of A/D converter
P26_7
General-purpose input/output port
SMC2M3
AN31
I/O
F
Controller output pin of Stepper motor
Analog input pin of A/D converter
(Continued)
12
DS07-16612-2E
MB91460D Series
(Continued)
Pin no.
Pin name
P25_0
178
SMC1P4
P25_1
179
SMC1M4
P25_2
180
SMC2P4
P25_3
181
SMC2M4
P25_4
184
SMC1P5
P25_5
185
SMC1M5
P25_6
186
SMC2P5
P25_7
187
SMC2M5
P13_0
189
DREQ0
P13_1
190
DACKX0
I/O
I/O circuit
type*
I/O
E
I/O
E
I/O
E
I/O
E
I/O
E
I/O
E
I/O
E
I/O
E
I/O
A
I/O
A
P13_2
191
DEOTX0
200 to 207
P03_0 to P03_7
D0 to D7
P02_0 to P02_7
D8 to D15
General-purpose input/output port
Controller output pin of Stepper motor
General-purpose input/output port
Controller output pin of Stepper motor
General-purpose input/output port
Controller output pin of Stepper motor
General-purpose input/output port
Controller output pin of Stepper motor
General-purpose input/output port
Controller output pin of Stepper motor
General-purpose input/output port
Controller output pin of Stepper motor
General-purpose input/output port
Controller output pin of Stepper motor
General-purpose input/output port
Controller output pin of Stepper motor
General-purpose input/output port
DMA external transfer request input
General-purpose input/output port
DMA external transfer acknowledge output pin
General-purpose input/output port
I/O
A
DEOP0
192 to 199
Function
DMA external transfer EOT (End of Track) output pin
DMA external transfer EOP (End of Process) output pin
I/O
A
I/O
A
General-purpose input/output ports
Signal pins of external data bus (bit0 to bit7)
General-purpose input/output ports
Signal pins of external data bus (bit8 to bit15)
* : For information about the I/O circuit type, refer to “■ I/O CIRCUIT TYPES”.
DS07-16612-2E
13
MB91460D Series
[Power supply/Ground pins]
Pin no.
Pin name
I/O
Function
1, 27, 53, 69, 79, 105,
131, 157, 188
VSS5
163, 173, 183
HVSS5
Ground pins for Stepper motor controller
26, 52
VDD35
Power supply pins for external data bus
78, 104, 130, 156
VDD5
Power supply pins
162, 172, 182
HVDD5
81, 82
VDD5R
Power supply pins for internal regulator
144
AVSS5
Analog ground pin for A/D converter
146
AVCC5
Power supply pin for A/D converter
145
AVRH5
Reference power supply pin for A/D converter
80
VCC18C
Capacitor connection pin for internal regulator
14
Ground pins
Supply
Power supply pins for Stepper motor controller
DS07-16612-2E
MB91460D Series
■ I/O CIRCUIT TYPES
Type
Circuit
A
Remarks
pull-up control
driver strength
control
data line
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
B
pull-up control
driver strength
control
data line
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
analog input
DS07-16612-2E
15
MB91460D Series
Type
Circuit
C
Remarks
pull-up control
data line
CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
D
pull-up control
data line
CMOS level output (IOL = 3mA, IOH = -3mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
pull- down control
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
analog input
16
DS07-16612-2E
MB91460D Series
Type
Circuit
E
Remarks
pull-up control
driver strength
control
data line
pull- down control
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA,
and IOL = 30mA, IOH = -30mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
F
pull-up control
driver strength
control
data line
pull- down control
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA,
and IOL = 30mA, IOH = -30mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
analog input
DS07-16612-2E
17
MB91460D Series
Type
Circuit
Remarks
G
R
Hysteresis
inputs
H
Mask ROM and EVA device:
CMOS Hysteresis input pin
Flash device:
CMOS input pin
12 V withstand (for MD [2:0])
CMOS Hysteresis input pin
Pull-up resistor value: 50 kΩ approx.
Pull-up
Resistor
R
Hysteresis
inputs
J1
X1
R
0
Xout
1
High-speed oscillation circuit:
• Programmable between oscillation mode
(external crystal or resonator connected
to X0/X1 pins) and
Fast external Clock Input (FCI) mode
(external clock connected to X0 pin)
• Feedback resistor = approx. 2 * 0.5 MΩ.
Feedback resistor is grounded in the center
when the oscillator is disabled or in FCI mode.
FCI
R
X0
FCI or osc disable
J2
Xout
X1A
Low-speed oscillation circuit:
• Feedback resistor = approx. 2 * 5 MΩ.
Feedback resistor is grounded in the center
when the oscillator is disabled.
R
R
X0A
osc disable
18
DS07-16612-2E
MB91460D Series
Type
Circuit
K
Remarks
pull-up control
driver strength
control
data line
pull- down control
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
LCD SEG/COM output
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
LCD SEG/COM
L
pull-up control
driver strength
control
data line
pull- down control
CMOS level output
(programmable IOL = 5mA, IOH = -5mA
and IOL = 2mA, IOH = -2mA)
2 different CMOS hysteresis inputs with input
shutdown function
Automotive input with input shutdown function
TTL input with input shutdown function
Programmable pull-up resistor: 50kΩ approx.
Analog input
LCD Voltage input
R
CMOS hysteresis type1
CMOS hysteresis type2
Automotive inputs
TTL input
standby control for
input shutdown
VLCD
DS07-16612-2E
19
MB91460D Series
Type
Circuit
Remarks
M
CMOS level tri-state output
(IOL = 5mA, IOH = -5mA)
tri-state control
data line
N
Analog input pin with protection
analog input line
20
DS07-16612-2E
MB91460D Series
■ HANDLING DEVICES
1. Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage higher than (VDD5, VDD35 or HVDD5) or less than (VSS5 or HVSS5)
is applied to an input or output pin or if a voltage exceeding the rating is applied between the power supply pins
and ground pins. If latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal
breakdown of the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum
ratings.
2. Handling of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistor (2KΩ to 10KΩ) or enable internal pullup or pulldown resisters (PPER/PPCR)
before the input enable (PORTEN) is activated by software. The mode pins MD_x can be connected to VSS5 or
VDD5 directly. Unused ALARM input pins can be connected to AVSS5 directly.
3. Power supply pins
In MB91460D series, devices including multiple power supply pins and ground pins are designed as follows;
pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latchup. All of the power supply pins and ground pins must be externally connected to the power supply and ground
respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground
level rising and to follow the total output current ratings. Furthermore, the power supply pins and ground pins of
the MB91460D series must be connected to the current supply source via a low impedance.
It is also recommended to connect a ceramic capacitor of approximately 0.1 μF as a bypass capacitor between
power supply pin and ground pin near this device.
This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 μF (use a X7R ceramic
capacitator) to VCC18C pin for the regulator.
4. Crystal oscillator circuit
Noise in proximity to the X0 (X0A) and X1 (X1A) pins can cause the device to operate abnormally. Printed circuit
boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass
capacitors connected to ground, are located near the device and ground.
It is recommended that the printed circuit board layout be designed such that the X0 and X1 pins or X0A and
X1A pins are surrounded by ground plane for the stable operation.
Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this
device.
5. Notes on using external clock
When using the external clock, it is necessary to simultaneously supply the X0 (X0A) and the X1 (X1A) pins. In
the described combination, X1 (X1A) should be supplied with a clock signal which has the opposite phase to
the X0 (X0A) pins. At X0 and X1, a frequency up to 16 MHz is possible.
(Continued)
DS07-16612-2E
21
MB91460D Series
(Continued)
Example of using opposite phase supply
X0 (X0A)
X1 (X1A)
22
DS07-16612-2E
MB91460D Series
6. Mode pins (MD_x)
These pins should be connected directly to the power supply or ground pins. To prevent the device from entering
test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and power
supply pin or ground pin on the printed circuit board as possible and connect them with low impedance.
7. Notes on operating in PLL clock mode
If the oscillator is disconnected or the clock input stops when the PLL clock is selected, the microcontroller may
continue to operate at the free-running frequency of the self-oscillating circuit of the PLL. However, this selfrunning operation cannot be guaranteed.
8. Pull-up control
The AC standard is not guaranteed in case a pull-up resistor is connected to the pin serving as an external bus pin.
9. Notes on PS register
As the PS register is processed in advance by some instructions, when the debugger is being used, the exception
handling may result in execution breaking in an interrupt handling routine or the displayed values of the flags in
the PS register being updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,
the operation before and after the EIT always proceeds according to specification.
• The following behavior may occur if any of the following occurs in the instruction
immediately after a DIV0U/DIV0S instruction:
(a) a user interrupt or NMI is accepted;
(b) single-step execution is performed;
(c) execution breaks due to a data event or from the emulator menu.
1. D0 and D1 flags are updated in advance.
2. An EIT handling routine (user interrupt/NMI or emulator) is executed.
3. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed
and the D0 and D1 flags are updated to the same values as those in 1.
• The following behavior occurs when an ORCCR, STILM, MOV Ri,PS instruction is executed
to enable a user interrupt or NMI source while that interrupt is in the active state.
1. The PS register is updated in advance.
2. An EIT handling routine (user interrupt/NMI or emulator) is executed.
3. Upon returning from the EIT, the above instructions are executed and the PS register
is updated to the same value as in 1.
DS07-16612-2E
23
MB91460D Series
■ NOTES ON DEBUGGER
1. Execution of the RETI Command
If single-step execution is used in an environment where an interrupt occurs frequently, the corresponding
interrupt handling routine will be executed repeatedly to the exclusion of other processing. This will prevent the
main routine and the handlers for low priority level interrupts from being executed (For example, if the time-base
timer interrupt is enabled, stepping over the RETI instruction will always break on the first line of the time-base
timer interrupt handler).
Disable the corresponding interrupts when the corresponding interrupt handling routine no longer needs debugging.
2. Break function
If the range of addresses that cause a hardware break (including event breaks) is set to the address of the
current system stack pointer or to an area that contains the stack pointer, execution will break after each
instruction regardless of whether the user program actually contains data access instructions.
To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the
target of the hardware break (including an event breaks).
3. Operand break
It may cause malfunctions if a stack pointer exists in the area which is set as the DSU operand break. Do not
set the access to the areas containing the address of system stack pointer as a target of data event break.
24
DS07-16612-2E
MB91460D Series
■ BLOCK DIAGRAM
1. MB91F465DA, MB91F467Dx
FR60 CPU
core
Flash-Cache
8 Kbytes
I-bus
32
D-RAM
32 Kbytes
Bit search
Flash memory
1088 Kbytes (MB91F467Dx)
544 Kbytes (MB91F465DA)
D-bus
32
CAN
3 channels
RX0 to RX2
TX0 to TX2
32 <-> 16
bus adapter
ID-RAM
32 Kbytes
(MB91F467Dx)
16 Kbytes
(MB91F465DA)
External
bus
interface
Bus converter
BAAX
WEX
ASX
RDX
WRX0 to WRX3
BRQ
MCLKE
MCLKO
MCLKI
BGRNTX
CSX0 to CSX3,CSX6,CSX7
A0 to A25
DREQ0
DACKX0
DEOP0
DEOTX0
D0 to D31
DMAC
5 channels
Clock modulator
Clock supervisor
Clock monitor
Clock control
Interrupt controller
TTG8 to TTG11, TTG4/12 to TTG7/15
PPG4 to PPG15
PPG timer
12 channels
TIN0 to TIN7
TOT0 to TOT3
Reload timer
8 channels
CK2,CK4 to CK7
ICU0 to ICU7
R-bus
16
Free-run timer
8 channels
Input capture
8 channels
External interrupt
14 channels
MONCLK
INT0 to INT10,
INT12 to INT14
LIN-USART
5 channels
SIN2,SIN4 to SIN7
SOT2,SOT4 to SOT7
SCK2,SCK4 to SCK7
I2C
3 channels
SDA0,SDA2,SDA3
SCL0,SCL2,SCL3
Real time clock
OCU0 to OCU3
AIN0,AIN2,AIN3
BIN0,BIN2,BIN3
ZIN0,ZIN2,ZIN3
PFM
ALARM_0
DS07-16612-2E
Output compare
4 channels
Up/down counter
3 channels
PFM timer
1 channel
Alarm comparator
1 channel
A/D converter
24 channels
Stepper motor controller
6 channels
Sound generator
1 channel
AN0 to AN7,
AN16 to AN31
ATGX
SMC1P0 to SMC1P5
SMC1M0 to SMC1M5
SMC2P0 to SMC2P5
SMC2M0 to SMC2M5
SGA
SGO
25
MB91460D Series
■ CPU AND CONTROL UNIT
The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced
instructions for embedded applications.
1. Features
• Adoption of RISC architecture
Basic instruction: 1 instruction per cycle
• General-purpose registers: 32-bit × 16 registers
• 4 Gbytes linear memory space
• Multiplier installed
32-bit × 32-bit multiplication: 5 cycles
16-bit × 16-bit multiplication: 3 cycles
• Enhanced interrupt processing function
Quick response speed (6 cycles)
Multiple-interrupt support
Level mask function (16 levels)
• Enhanced instructions for I/O operation
Memory-to-memory transfer instruction
Bit processing instruction
Basic instruction word length: 16 bits
• Low-power consumption
Sleep mode/stop mode
2. Internal architecture
• The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent
of each other.
• A 32-bit ↔ 16-bit buffer is connected to the 32-bit bus (D-bus) to provide an interface between the CPU and
peripheral resources.
• A Harvard ↔ Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between
the CPU and the bus controller.
26
DS07-16612-2E
MB91460D Series
3. Programming model
3.1.
Basic programming model
32 bits
Initial value
R0
XXXX XXXXH
...
R1
General-purpose registers
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Program counter
PC
Program status
RS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiply & divide registers
MDH
ILM
SCR
CCR
MDL
DS07-16612-2E
27
MB91460D Series
4. Registers
4.1.
General-purpose register
32 bits
Initial value
R0
XXXX XXXXH
...
R1
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation
operations and as pointers for memory access.
Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular
applications.
R13 : Virtual accumulator
R14 : Frame pointer
R15 : Stack pointer
Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value).
4.2.
PS (Program Status)
This register holds the program status, and is divided into three parts, ILM, SCR, and CCR.
All undefined bits (-) in the diagram are reserved bits. The read values are always “0”. Write access to these
bits is invalid.
Bit position → bit 31
bit 20
bit 16
ILM
28
bit 10 bit 8 bit 7
SCR
bit 0
CCR
DS07-16612-2E
MB91460D Series
4.3.
CCR (Condition Code Register)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SV
S
I
N
Z
V
C
Initial value
- 000XXXXB
SV : Supervisor flag
S
: Stack flag
I
: Interrupt enable flag
N : Negative enable flag
Z
: Zero flag
V
: Overflow flag
C : Carry flag
4.4.
SCR (System Condition Register)
bit 10 bit 9
D1
bit 8
D0
Initial value
T
XX0B
Flag for step division (D1, D0)
This flag stores interim data during execution of step division.
Step trace trap flag (T)
This flag indicates whether the step trace trap is enabled or disabled.
The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution
of user programs.
4.5.
ILM (Interrupt Level Mask register)
bit 20 bit 19 bit 18 bit 17 bit 16
Initial value
ILM4 ILM3 ILM2 ILM1 ILM0
01111B
This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking.
The register is initialized to value “01111B” at reset.
4.6.
PC (Program Counter)
bit 31
bit 0
Initial value
XXXXXXXXH
The program counter indicates the address of the instruction that is being executed.
The initial value at reset is undefined.
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29
MB91460D Series
4.7.
TBR (Table Base Register)
bit 31
bit 0
Initial value
000FFC00H
The table base register stores the starting address of the vector table used in EIT processing.
The initial value at reset is 000FFC00H.
4.8.
RP (Return Pointer)
bit 31
bit 0
Initial value
XXXXXXXXH
The return pointer stores the address for return from subroutines.
During execution of a CALL instruction, the PC value is transferred to this RP register.
During execution of a RET instruction, the contents of the RP register are transferred to PC.
The initial value at reset is undefined.
4.9.
USP (User Stack Pointer)
bit 31
bit 0
Initial value
XXXXXXXXH
The user stack pointer, when the S flag is “1”, this register functions as the R15 register.
• The USP register can also be explicitly specified.
The initial value at reset is undefined.
• This register cannot be used with RETI instructions.
4.10. Multiply & divide registers
bit 31
bit 0
MDH
MDL
These registers are for multiplication and division, and are each 32 bits in length.
The initial value at reset is undefined.
30
DS07-16612-2E
MB91460D Series
■ EMBEDDED PROGRAM/DATA MEMORY (FLASH)
1. Flash features
•
•
•
•
•
•
MB91F467Dx: 1088 Kbytes (16 × 64 Kbytes + 8 × 8 Kbytes) = 8.5 Mbits
MB91F465DA: 544 Kbytes (8 × 64 Kbytes + 4 × 8 Kbytes) = 4.25 Mbits
Programmable wait state for read/write access
Flash and Boot security with security vector at 0x0014:8000 - 0x0014:800F
Boot security
Basic specification: Same as MBM29LV400TC (except size and part of sector configuration)
2. Operation modes
(1) 64-bit CPU mode (available on MB91F467Dx only) :
• CPU reads and executes programs in word (32-bit) length units.
• Flash writing is not possible.
• Actual Flash Memory access is performed in d-word (64-bit) length units.
(2) 32-bit CPU mode :
• MB91F465DA: CPU reads and executes programs in word (32-bit) length units.
MB91F467Dx: CPU reads, writes and executes programs in word (32-bit) length units.
• Actual Flash Memory access is performed in word (32-bit) length units.
(3) 16-bit CPU mode :
• CPU reads and writes in half-word (16-bit) length units.
• Program execution from the Flash is not possible.
• Actual Flash Memory access is performed in half-word (16-bit) length units.
Note: The operation mode of the flash memory can be selected using a Boot-ROM function. The function start
address is 0xBF60. The parameter description is given in the Hardware Manual in chapter 54.6 "Flash
Access Mode Switching".
DS07-16612-2E
31
MB91460D Series
3. Flash access in CPU mode
3.1.
Flash configuration
3.1.1.
Flash memory map MB91F467Dx
Address
0014:FFFFh
0014:C000h
SA6 (8KB)
SA7 (8KB)
0014:BFFFh
0014:8000h
SA4 (8KB)
SA5 (8KB)
0014:7FFFh
0014:4000h
SA2 (8KB)
SA3 (8KB)
0014:3FFFh
0014:0000h
SA0 (8KB)
SA1 (8KB)
0013:FFFFh
0012:0000h
SA22 (64KB)
SA23 (64KB)
0011:FFFFh
0010:0000h
SA20 (64KB)
SA21 (64KB)
000F:FFFFh
000E:0000h
SA18 (64KB)
SA19 (64KB)
ROMS5
000D:FFFFh
000C:0000h
SA16 (64KB)
SA17 (64KB)
ROMS4
000B:FFFFh
000A:0000h
SA14 (64KB)
SA15 (64KB)
ROMS3
0009:FFFFh
0008:0000h
SA12 (64KB)
SA13 (64KB)
ROMS2
0007:FFFFh
0006:0000h
SA10 (64KB)
SA11 (64KB)
ROMS1
0005:FFFFh
0004:0000h
SA8 (64KB)
SA9 (64KB)
ROMS0
ROMS7
ROMS6
addr+0
16bit read/write
32bit read/write
64bit read
32
addr+1
addr+2
dat[31:16]
addr+3
addr+4
dat[15:0]
addr+5
addr+6
dat[31:16]
dat[31:0]
addr+7
dat[15:0]
dat[31:0]
dat[63:0]
DS07-16612-2E
MB91460D Series
3.1.2.
Flash memory map MB91F465DA
Addr
0014:FFFFh
0014:C000h
SA6 (8KB)
SA7 (8KB)
0014:BFFFh
0014:8000h
SA4 (8KB)
SA5 (8KB)
0014:7FFFh
0014:4000h
SA2 (8KB)
SA3 (8KB)
0014:3FFFh
0014:0000h
SA0 (8KB)
SA1 (8KB)
0013:FFFFh
0012:0000h
SA22 (64KB)
SA23 (64KB)
0011:FFFFh
0010:0000h
SA20 (64KB)
SA21 (64KB)
000F:FFFFh
000E:0000h
SA18 (64KB)
SA19 (64KB)
ROMS5
000D:FFFFh
000C:0000h
SA16 (64KB)
SA17 (64KB)
ROMS4
000B:FFFFh
000A:0000h
SA14 (64KB)
SA15 (64KB)
ROMS3
0009:FFFFh
0008:0000h
SA12 (64KB)
SA13 (64KB)
ROMS2
0007:FFFFh
0006:0000h
SA10 (64KB)
SA11 (64KB)
ROMS1
0005:FFFFh
0004:0000h
SA8 (64KB)
SA9 (64KB)
ROMS0
ROMS7
ROMS6
addr+0
16bit read/write
addr+1
addr+2
dat[31:16]
addr+3
dat[15:0]
addr+4
addr+5
addr+6
dat[31:16]
32bit read
dat[31:0]
dat[31:0]
Legend
Memory not available in this area
Memory available in this area
DS07-16612-2E
addr+7
dat[15:0]
33
MB91460D Series
3.2.
Flash access timing settings in CPU mode
The following tables list all settings for a given maximum Core Frequency (through the setting of CLKB or
maximum clock modulation) for Flash read and write access.
3.2.1.
ATD
ALEH
EQ
WEXH
WTC
to 24 MHz
0
0
0
-
1
to 48 MHz
0
0
1
-
2
to 96 MHz
1
1
3
-
4
to 100 MHz
1
1
3
-
4
not available on MB91F467Dx
Remark
3.2.2.
34
Flash read timing settings (synchronous read)
Core clock (CLKB)
Remark
Flash write timing settings (synchronous write)
Core clock (CLKB)
ATD
ALEH
EQ
WEXH
WTC
to 32 MHz
1
-
-
0
4
to 48 MHz
1
-
-
0
5
to 64 MHz
1
-
-
0
6
to 96 MHz
1
-
-
0
7
to 100 MHz
1
-
-
0
7
not available on MB91F467Dx
DS07-16612-2E
MB91460D Series
3.3.
Address mapping from CPU to parallel programming mode
The following tables show the calculation from CPU addresses to flash macro addresses which are used in
parallel programming.
3.3.1.
Address mapping MB91F467Dx
CPU Address
Condition
(addr)
Flash
sectors
FA (flash address) Calculation
14:0000h
to
14:FFFFh
addr[2]==0
SA0, SA2, SA4, SA6
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 05:0000h
14:0000h
to
14:FFFFh
addr[2]==1
SA1, SA3, SA5, SA7
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 05:0000h
+ 00:2000h
04:0000h
to
13:FFFFh
addr[2]==0
SA8, SA10, SA12, SA14,
SA16, SA18, SA20, SA22
(64 Kbyte)
FA := addr - addr%02:0000 + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 0C:0000h
04:0000h
to
13:FFFFh
addr[2]==1
SA9, SA11, SA13, SA15,
SA17, SA19, SA21, SA23
(64 Kbyte)
FA := addr - addr%02:0000h + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 0C:0000h
+ 01:0000h
Note: FA result is without 20:0000h offset for parallel Flash programming .
Set offset by keeping FA[21] = 1 as described in section “Parallel Flash programming mode”.
3.3.2.
Address mapping MB91F465DA
CPU Address
Condition
(addr)
Flash
sectors
FA (flash address) Calculation
14:8000h
to
14:FFFFh
addr[2]==0
SA4, SA6
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 0D:0000h
14:8000h
to
14:FFFFh
addr[2]==1
SA5, SA7
(8 Kbyte)
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 0D:0000h
+ 00:2000h
08:0000h
to
0F:FFFFh
addr[2]==0
SA12, SA14, SA16, SA18
(64 Kbyte)
FA := addr - addr%02:0000 + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 00:0000h
08:0000h
to
0F:FFFFh
addr[2]==1
SA13, SA15, SA17, SA19
(64 Kbyte)
FA := addr - addr%02:0000h + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 - 00:0000h
+ 01:0000h
Note: FA result is without 10:0000h offset for parallel Flash programming .
Set offset by keeping FA[20] = 1 as described in section “Parallel Flash programming mode”.
DS07-16612-2E
35
MB91460D Series
4. Parallel Flash programming mode
4.1.
Flash configuration in parallel Flash programming mode
Parallel Flash programming mode (MD[2:0] = 111):
MB91F467Dx
MB91F465DA
FA[21:0]
FA[20:0]
003F:FFFFh
003F:0000h
SA23 (64KB)
001F:FFFFh
001F:0000h
SA19 (64KB)
003E:FFFFh
003E:0000h
SA22 (64KB)
001E:FFFFh
001E:0000h
SA18 (64KB)
003D:FFFFh
003D:0000h
SA21 (64KB)
001D:FFFFh
001D:0000h
SA17 (64KB)
003C:FFFFh
003C:0000h
SA20 (64KB)
001C:FFFFh
001C:0000h
SA16 (64KB)
003B:FFFFh
003B:0000h
SA19 (64KB)
001B:FFFFh
001B:0000h
SA15 (64KB)
003A:FFFFh
003A:0000h
SA18 (64KB)
001A:FFFFh
001A:0000h
SA14 (64KB)
0039:FFFFh
0039:0000h
SA17 (64KB)
0019:FFFFh
0019:0000h
SA13 (64KB)
0038:FFFFh
0038:0000h
SA16 (64KB)
0018:FFFFh
0018:0000h
SA12 (64KB)
0037:FFFFh
0037:0000h
SA15 (64KB)
0036:FFFFh
0036:0000h
SA14 (64KB)
0035:FFFFh
0035:0000h
SA13 (64KB)
0034:FFFFh
0034:0000h
SA12 (64KB)
0033:FFFFh
0033:0000h
SA11 (64KB)
0032:FFFFh
0032:0000h
0017:FFFFh
0017:E000h
SA7 (8KB)
SA10 (64KB)
0031:FFFFh
0031:0000h
SA9 (64KB)
0017:DFFFh
0017:C000h
SA6 (8KB)
0030:FFFFh
0030:0000h
SA8 (64KB)
0017:BFFFh
0017:A000h
SA5 (8KB)
002F:FFFFh
002F:E000h
SA7 (8KB)
0017:9FFFh
0017:8000h
SA4 (8KB)
002F:DFFFh
002F:C000h
SA6 (8KB)
SA3 (8KB)
002F:BFFFh
002F:A000h
SA5 (8KB)
SA2 (8KB)
002F:9FFFh
002F:8000h
SA4 (8KB)
SA1 (8KB)
002F:7FFFh
002F:6000h
SA3 (8KB)
SA0 (8KB)
002F:5FFFh
002F:4000h
SA2 (8KB)
002F:3FFFh
002F:2000h
SA1 (8KB)
002F:1FFFh
002F:0000h
SA0 (8KB)
SA11 (64KB)
SA10 (64KB)
SA9 (64KB)
SA8 (64KB)
16bit write mode
FA[1:0]=00
FA[1:0]=10
DQ[15:0]
DQ[15:0]
Remark: Always keep FA[0] = 0 and FA[20] = 1
16bit write mode
Legend
FA[1:0]=00
FA[1:0]=10
DQ[15:0]
DQ[15:0]
Memory available in this area
Memory not available in this area
Remark: Always keep FA[0] = 0 and FA[21] = 1
36
DS07-16612-2E
MB91460D Series
4.2.
Pin connections in parallel programming mode
Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory’s
interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of
the signals to General Purpose Ports. Please see table below for signal mapping.
In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set
when writing/erasing using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash
memory’s Auto Algorithms are available.
Correspondence between MBM29LV400TC and Flash Memory Control Signals
MB91F465DA, MB91F467Dx external pins
MBM29LV400TC
External pins
FR-CPU mode
⎯
Comment
Flash memory
mode
Normal function
Pin number
INITX
⎯
INITX
73
RESET
⎯
FRSTX
P09_6
60
⎯
⎯
MD_2
MD_2
70
Set to ‘1’
⎯
⎯
MD_1
MD_1
71
Set to ‘1’
⎯
⎯
MD_0
MD_0
72
Set to ‘1’
RY/BY
FMCS:RDY bit
RY/BYX
P09_0
56
BYTE
Internally fixed to ’H’
BYTEX
P09_2
58
WE
WEX
P13_2
191
OE
OEX
P13_1
190
CEX
P13_0
189
ATDIN
P25_7
187
Set to ‘0’
EQIN
P25_6
186
Set to ‘0’
⎯
TESTX
P09_3
59
Set to ‘1’
⎯
RDYI
P09_1
57
Set to ‘0’
A-1
FA0
P25_5
185
Set to ‘0’
A0 to A3
FA1 to FA4
P27_0 to P27_3
158 to 161
A4 to A7
FA5 to FA8
P27_4 to P27_7
164 to 167
A8 to A11
FA9 to FA12
P26_0 to P26_3
168 to 171
A12 to A15
Internal address bus FA13 to FA16
P26_4 to P26_7
174 to 177
A16 to A19
FA17 to FA20
P25_0 to P25_3
178 to 181
CE
⎯
⎯
⎯
DS07-16612-2E
Internal control signal
+ control via interface
circuit
FA21
P25_4
184
Not needed on
MB91F465DA;
Set to ‘1’ on
MB91F467Dx
37
MB91460D Series
DQ0 to DQ7
DQ0 to DQ7
P03_0 to P03_7
192 to 199
DQ8 to DQ15
P02_0 to P02_7
200 to 207
Internal data bus
DQ8 to DQ15
5. Poweron Sequence in parallel programming mode
The flash memory can be accessed in programming mode after a certain wait time, which is needed for Security
Vector fetch:
• Minimum wait time after VDD5/VDD5R power on:
• Minimum wait time after INITX rising:
2.76 ms
1.0 ms
6. Flash Security
6.1.
Vector addresses
Two Flash Security Vectors (FSV1, FSV2) are located parallel to the Boot Security Vectors (BSV1, BSV2)
controlling the protection functions of the Flash Security Module:
FSV1: 0x14:8000
FSV2: 0x14:8008
6.2.
BSV1: 0x14:8004
BSV2: 0x14:800C
Security Vector FSV1
The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the
individual write protection of the 8 Kbytes sectors.
6.2.1.
FSV1 (bit31 to bit16)
The setting of the Flash Security Vector FSV1 bits [31:16] is responsible for the read and write protection modes.
Explanation of the bits in the Flash Security Vector FSV1 [31:16]
FSV1[18]
FSV1[17]
FSV1[16]
FSV1[31:19] Write Protection
Write Protection Read Protection
Level
set all to “0”
set to “0”
set to “0”
set to “1”
Read Protection (all device modes,
except INTVEC mode MD[2:0] = “000”)
set all to “0”
set to “0”
set to “1”
set to “0”
Write Protection (all device modes,
without exception)
set all to “0”
set to “0”
set to “1”
set to “1”
Read Protection (all device modes,
except INTVEC mode MD[2:0] = “000”)
and Write Protection (all device modes)
set all to “0”
set to “1”
set to “0”
set to “1”
Read Protection (all device modes,
except INTVEC mode MD[2:0] = “000”)
set all to “0”
set to “1”
set to “1”
set to “0”
Write Protection (all device modes,
except INTVEC mode MD[2:0] = “000”)
set to “1”
Read Protection (all device modes,
except INTVEC mode MD[2:0] = “000”)
and Write Protection (all device modes
except INTVEC mode MD[2:0] = “000”)
set all to “0”
38
Flash Security Mode
set to “1”
set to “1”
DS07-16612-2E
MB91460D Series
6.2.2.
FSV1 (bit15 to bit0)
The setting of the Flash Security Vector FSV1 bits [15:0] is responsible for the individual write protection of the
8 Kbytes sectors. It is only evaluated if write protection bit FSV1[17] is set.
Explanation of the bits in the Flash Security Vector FSV1 [15:0]
Enable Write
Disable Write
FSV1 bit
Sector
Protection
Protection
Comment
FSV1[0]
SA0 (MB91F467Dx)
set to “0”
set to “1”
FSV1[1]
SA1 (MB91F467Dx)
set to “0”
set to “1”
FSV1[2]
SA2 (MB91F467Dx)
set to “0”
set to “1”
FSV1[3]
SA3 (MB91F467Dx)
set to “0”
set to “1”
FSV1[4]
SA4
set to “0”
⎯
FSV1[5]
SA5
set to “0”
set to “1”
FSV1[6]
SA6
set to “0”
set to “1”
FSV1[7]
SA7
set to “0”
set to “1”
FSV1[8]
⎯
set to “0”
set to “1”
not available
FSV1[9]
⎯
set to “0”
set to “1”
not available
FSV1[10]
⎯
set to “0”
set to “1”
not available
FSV1[11]
⎯
set to “0”
set to “1”
not available
FSV1[12]
⎯
set to “0”
set to “1”
not available
FSV1[13]
⎯
set to “0”
set to “1”
not available
FSV1[14]
⎯
set to “0”
set to “1”
not available
FSV1[15]
⎯
set to “0”
set to “1”
not available
Write protection is mandatory!
Note : It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are located to
write protected (here sector SA4). Otherwise it is possible to overwrite the Security Vector to a setting where
it is possible to either read out the Flash content or manipulate data by writing.
See section “Flash access in CPU mode” for an overview about the sector organisation of the Flash
Memory.
DS07-16612-2E
39
MB91460D Series
6.3.
Security Vector FSV2
The setting of the Flash Security Vector FSV2 bits [31:0] is responsible for the individual write protection of the
64 Kbytes sectors. It is only evaluated if write protection bit FSV1 [17] is set.
Explanation of the bits in the Flash Security Vector FSV2[31:0]
Enable Write
Disable Write
FSV2 bit
Sector
Protection
Protection
FSV2[0]
SA8 (MB91F467Dx)
set to “0”
set to “1”
FSV2[1]
SA9 (MB91F467Dx)
set to “0”
set to “1”
FSV2[2]
SA10 (MB91F467Dx)
set to “0”
set to “1”
FSV2[3]
SA11 (MB91F467Dx)
set to “0”
set to “1”
FSV2[4]
SA12
set to “0”
set to “1”
FSV2[5]
SA13
set to “0”
set to “1”
FSV2[6]
SA14
set to “0”
set to “1”
FSV2[7]
SA15
set to “0”
set to “1”
FSV2[8]
SA16
set to “0”
set to “1”
FSV2[9]
SA17
set to “0”
set to “1”
FSV2[10]
SA18
set to “0”
set to “1”
FSV2[11]
SA19
set to “0”
set to “1”
FSV2[12]
SA20 (MB91F467Dx)
set to “0”
set to “1”
FSV2[13]
SA21 (MB91F467Dx)
set to “0”
set to “1”
FSV2[14]
SA22 (MB91F467Dx)
set to “0”
set to “1”
FSV2[15]
SA23 (MB91F467Dx)
set to “0”
set to “1”
FSV2[31:16]
⎯
set to “0”
set to “1”
Comment
not available
Note : See section “Flash access in CPU mode” for an overview about the sector organisation of the Flash Memory.
40
DS07-16612-2E
MB91460D Series
■ MEMORY SPACE
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
• Direct addressing area
The following address space area is used for I/O.
This area is called direct addressing area, and the address of an operand can be specified directly in an
instruction.
The size of directly addressable area depends on the length of the data being accessed as shown below.
Byte data access : 000H to 0FFH
Half word access : 000H to 1FFH
Word data access : 000H to 3FFH
DS07-16612-2E
41
MB91460D Series
■ MEMORY MAPS
1. MB91F465DA, MB91F467Dx
MB91F467Dx
00000000H
00000400H
00001000H
00000000H
I/O (direct addressing area)
00000400H
I/O
00001000H
DMA
00004000H
Flash-Cache (8 KBytes)
00007000H
Flash memory control
0000C000H
0000B000H
Boot ROM (4 Kbytes)
0000C000H
CAN
00028000H
00030000H
Flash-Cache (8 KBytes)
Flash memory control
Boot ROM (4 Kbytes)
CAN
0000D000H
0000D000H
00028000H
DMA
00008000H
00008000H
0000B000H
I/O
00006000H
00006000H
00007000H
I/O (direct addressing area)
00002000H
00002000H
00004000H
MB91F465DA
D-RAM (0 wait, 32 Kbytes)
00030000H
ID-RAM (32 Kbytes)
00034000H
00040000H
00038000H
00040000H
D-RAM (0 wait, 32 Kbytes)
ID-RAM (16 Kbytes)
External bus area
00080000H
Flash memory (512 Kbytes)
Flash memory (1088 Kbytes)
00100000H
00148000H
00150000H
00150000H
00180000H
00180000H
00500000H
00500000H
External data bus
External data bus
FFFFFFFFH
FFFFFFFFH
42
Flash memory (32 Kbytes)
External bus area
External bus area
Note:
External bus area
Access prohibited areas
Note:
Access prohibited areas
DS07-16612-2E
MB91460D Series
■ I/O MAP
1. MB91F465DA, MB91F467Dx
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W]
XXXXXXXX
PDR1 [R/W]
XXXXXXXX
PDR2 [R/W]
XXXXXXXX
PDR3 [R/W]
XXXXXXXX
Block
T-unit
port data register
Read/write attribute
Register initial value after reset
Register name (column 1 register at address 4n, column 2 register at
address 4n + 1...)
Leftmost register address (for word access, the register in column 1
becomes the MSB side of the data.)
Note : Initial values of register bits are represented as follows:
“ 1 ” : Initial value “ 1 ”
“ 0 ” : Initial value “ 0 ”
“ X ” : Initial value “ undefined ”
“ - ” : No physical register at this location
Access is barred with an undefined data access attribute.
DS07-16612-2E
43
MB91460D Series
Address
Register
+0
+1
+2
+3
000000H
PDR00 [R/W]
XXXXXXXX
PDR01 [R/W]
XXXXXXXX
PDR02 [R/W]
XXXXXXXX
PDR03 [R/W]
XXXXXXXX
000004H
PDR04 [R/W]
- - - - - - XX
PDR05 [R/W]
XXXXXXXX
PDR06 [R/W]
XXXXXXXX
PDR07 [R/W]
XXXXXXXX
000008H
PDR08 [R/W]
XXXXXXXX
PDR09 [R/W]
XX - - XXXX
PDR10 [R/W]
- XXXXXX -
Reserved
00000CH
Reserved
PDR13 [R/W]
- - - - - XXX
PDR14 [R/W]
XXXXXXXX
PDR15 [R/W]
- - - - XXXX
000010H
PDR16 [R/W]
XXXXXXXX
PDR17 [R/W]
XXXX - - - -
PDR18 [R/W]
- XXX - XXX
PDR19 [R/W]
- XXX - XXX
000014H
PDR20 [R/W]
- - - - - XXX
Reserved
PDR22 [R/W]
- - XX - X - X
PDR23 [R/W]
- - XXXXXX
000018H
PDR24 [R/W]
XXXXXXXX
PDR25 [R/W]
XXXXXXXX
PDR26 [R/W]
XXXXXXXX
PDR27 [R/W]
XXXXXXXX
00001CH
Reserved
PDR29 [R/W]
XXXXXXXX
000020H
to
00002CH
Block
R-bus
Port Data
Register
Reserved
Reserved
Reserved
000030H
EIRR0 [R/W]
XXXXXXXX
ENIR0 [R/W]
00000000
ELVR0 [R/W]
00000000 00000000
External interrupt
(INT 0 to INT 7)
000034H
EIRR1 [R/W]
XXXXXXXX
ENIR1 [R/W]
00000000
ELVR1 [R/W]
00000000 00000000
External interrupt
(INT 8 to INT 10,
INT 12 to INT 14)
000038H
DICR [R/W]
-------0
HRCL [R/W]
0 - - 11111
Reserved
Delay Interrupt
00003CH
to
00004CH
Reserved
Reserved
000050H
SCR02 [R/W, W] SMR02 [R/W, W] SSR02 [R/W, R]
00000000
00000000
00001000
000054H
ECCR02
[R/W, R, W]
-00000XX
000058H,
00005CH
ESCR02 [R/W]
00000X00
Reserved
RDR02/TDR02
[R/W]
00000000
LIN-USART
2
Reserved
Reserved
(Continued)
44
DS07-16612-2E
MB91460D Series
(Continued)
Register
Address
000060H
000064H
000068H
00006CH
000070H
000074H
000078H
00007CH
+0
+1
+2
+3
SCR04 [R/W, W] SMR04 [R/W, W] SSR04 [R/W, R]
00000000
00000000
00001000
RDR04/TDR04
[R/W]
00000000
ECCR04
[R/W, R, W]
-00000XX
FCR04 [R/W]
0001 - 000
ESCR04 [R/W]
00000X00
FSR04 [R]
- - - 00000
SCR05 [R/W, W] SMR05 [R/W, W] SSR05 [R/W, R]
00000000
00000000
00001000
RDR05/TDR05
[R/W]
00000000
ECCR05
[R/W, R, W]
-00000XX
FCR05 [R/W]
0001 - 000
ESCR05 [R/W]
00000X00
FSR05 [R]
- - - 00000
SCR06 [R/W, W] SMR06 [R/W, W] SSR06 [R/W, R]
00000000
00000000
00001000
RDR06/TDR06
[R/W]
00000000
ECCR06
[R/W, R, W]
-00000XX
FCR06 [R/W]
0001 - 000
ESCR06 [R/W]
00000X00
FSR06 [R]
- - - 00000
SCR07 [R/W, W] SMR07 [R/W, W] SSR07 [R/W, R]
00000000
00000000
00001000
RDR07/TDR07
[R/W]
00000000
ECCR07
[R/W, R, W]
-00000XX
FCR07 [R/W]
0001 - 000
ESCR07 [R/W]
00000X00
000080H
FSR07 [R]
- - - 00000
Reserved
BGR102 [R/W]
00000000
BGR002 [R/W]
00000000
000088H
BGR104 [R/W]
00000000
BGR004 [R/W]
00000000
BGR105 [R/W]
00000000
BGR005 [R/W]
00000000
00008CH
BGR106 [R/W]
00000000
BGR006 [R/W]
00000000
BGR107 [R/W]
00000000
BGR007 [R/W]
00000000
PWC20 [R/W]
- - - - - - XX XXXXXXXX
000094H
Reserved
000098H
PWC21 [R/W]
- - - - - - XX XXXXXXXX
00009CH
Reserved
LIN-USART
4
with FIFO
LIN-USART
5
with FIFO
LIN-USART
6
with FIFO
LIN-USART
7
with FIFO
Reserved
000084H
000090H
Block
Reserved
PWC10 [R/W]
- - - - - - XX XXXXXXXX
PWS20 [R/W]
-0000000
PWS10 [R/W]
- -000000
PWC11 [R/W]
- - - - - - XX XXXXXXXX
PWS21 [R/W]
-0000000
PWS11 [R/W]
- -000000
Baud rate
Generator
LIN-USART
2,4 to 7
Stepper Motor 0
Stepper Motor 1
(Continued)
DS07-16612-2E
45
MB91460D Series
(Continued)
Address
Register
+0
+1
0000A0H
PWC22 [R/W]
- - - - - - XX XXXXXXXX
0000A4H
Reserved
0000A8H
PWC23 [R/W]
- - - - - - XX XXXXXXXX
0000ACH
Reserved
0000B0H
PWC24 [R/W]
- - - - - - XX XXXXXXXX
0000B4H
Reserved
0000B8H
PWC25 [R/W]
- - - - - - XX XXXXXXXX
0000BCH
+2
+3
PWC12 [R/W]
- - - - - - XX XXXXXXXX
PWS22 [R/W]
-0000000
PWS12 [R/W]
- -000000
PWC13 [R/W]
- - - - - - XX XXXXXXXX
PWS23 [R/W]
-0000000
PWS13 [R/W]
- -000000
PWC14 [R/W]
- - - - - - XX XXXXXXXX
PWS24 [R/W]
-0000000
PWS14 [R/W]
- -000000
PWC15 [R/W]
- - - - - - XX XXXXXXXX
Reserved
PWS25 [R/W]
-0000000
PWS15 [R/W]
- -000000
0000C0H
Reserved
PWC0 [R/W]
-00000--
Reserved
PWC1 [R/W]
-00000--
0000C4H
Reserved
PWC2 [R/W]
-00000--
Reserved
PWC3 [R/W]
-00000--
0000C8H
Reserved
PWC4 [R/W]
-00000--
Reserved
PWC5 [R/W]
-00000--
0000CCH
Reserved
Stepper Motor 2
Stepper Motor 3
Stepper Motor 4
Stepper Motor 5
Stepper Motor Control
0 to 5
Reserved
0000D0H
IBCR0 [R/W]
00000000
IBSR0 [R]
00000000
ITBAH0 [R/W]
- - - - - - 00
ITBAL0 [R/W]
00000000
0000D4H
ITMKH0 [R/W]
00 - - - - 11
ITMKL0 [R/W]
11111111
ISMK0 [R/W]
01111111
ISBA0 [R/W]
- 0000000
0000D8H
Reserved
IDAR0 [R/W]
00000000
ICCR0 [R/W]
00011111
Reserved
0000DCH
to
000100H
Block
Reserved
I2C 0
Reserved
000104H
GCN11 [R/W]
00110010 00010000
Reserved
GCN21 [R/W]
- - - - 0000
PPG Control
4 to 7
000108H
GCN12 [R/W]
00110010 00010000
Reserved
GCN22 [R/W]
- - - - 0000
PPG Control
8 to 11
000110H
to
00012CH
Reserved
Reserved
(Continued)
46
DS07-16612-2E
MB91460D Series
(Continued)
Register
Address
+0
+1
000130H
PTMR04 [R]
11111111 11111111
000134H
PDUT04 [W]
XXXXXXXX XXXXXXXX
000138H
PTMR05 [R]
11111111 11111111
00013CH
PDUT05 [W]
XXXXXXXX XXXXXXXX
000140H
PTMR06 [R]
11111111 11111111
000144H
PDUT06 [W]
XXXXXXXX XXXXXXXX
000148H
PTMR07 [R]
11111111 11111111
00014CH
PDUT07 [W]
XXXXXXXX XXXXXXXX
000150H
PTMR08 [R]
11111111 11111111
000154H
PDUT08 [W]
XXXXXXXX XXXXXXXX
000158H
PTMR09 [R]
11111111 11111111
00015CH
PDUT09 [W]
XXXXXXXX XXXXXXXX
000160H
PTMR10 [R]
11111111 11111111
000164H
PDUT10 [W]
XXXXXXXX XXXXXXXX
000168H
PTMR11 [R]
11111111 11111111
00016CH
PDUT11 [W]
XXXXXXXX XXXXXXXX
000170H
P0TMCSRH
[R/W]
- 0 - 000 - 0
+2
+3
PCSR04 [W]
XXXXXXXX XXXXXXXX
PCNH04 [R/W]
0000000 -
PCNL04 [R/W]
000000 - 0
PCSR05 [W]
XXXXXXXX XXXXXXXX
PCNH05 [R/W]
0000000 -
PCNL05 [R/W]
000000 - 0
PCSR06 [W]
XXXXXXXX XXXXXXXX
PCNH06 [R/W]
0000000 -
PCNL06 [R/W]
000000 - 0
PCSR07 [W]
XXXXXXXX XXXXXXXX
PCNH07 [R/W]
0000000 -
PCNL07 [R/W]
000000 - 0
PCSR08 [W]
XXXXXXXX XXXXXXXX
PCNH08 [R/W]
0000000 -
PCNL08 [R/W]
000000 - 0
PCSR09 [W]
XXXXXXXX XXXXXXXX
PCNH09 [R/W]
0000000 -
PCNL09 [R/W]
000000 - 0
PCSR10 [W]
XXXXXXXX XXXXXXXX
PCNH10 [R/W]
0000000 -
PCNL10 [R/W]
000000 - 0
PCSR11 [W]
XXXXXXXX XXXXXXXX
P0TMCSRL
[R/W]
- - - 00000
PCNH11 [R/W]
0000000 -
PCNL11 [R/W]
000000 - 0
P1TMCSRH
[R/W]
- 0 - 000 - 0
P1TMCSRL
[R/W]
- - - 00000
000174H
P0TMRLR [W]
XXXXXXXX XXXXXXXX
P0TMR [R]
XXXXXXXX XXXXXXXX
000178H
P1TMRLR [W]
XXXXXXXX XXXXXXXX
P1TMR [R]
XXXXXXXX XXXXXXXX
00017CH
DS07-16612-2E
Reserved
Block
PPG 4
PPG 5
PPG 6
PPG 7
PPG 8
PPG 9
PPG 10
PPG 11
PFM
Reserved
(Continued)
47
MB91460D Series
(Continued)
Address
000180H
Register
+0
+1
+2
+3
Reserved
ICS01 [R/W]
00000000
Reserved
ICS23 [R/W]
00000000
000184H
IPCP0 [R]
XXXXXXXX XXXXXXXX
IPCP1 [R]
XXXXXXXX XXXXXXXX
000188H
IPCP2 [R]
XXXXXXXX XXXXXXXX
IPCP3 [R]
XXXXXXXX XXXXXXXX
00018CH
OCS01 [R/W]
- - - 0 - - 00 0000 - - 00
OCS23 [R/W]
- - - 0 - - 00 0000 - - 00
000190H
OCCP0 [R/W]
XXXXXXXX XXXXXXXX
OCCP1 [R/W]
XXXXXXXX XXXXXXXX
000194H
OCCP2 [R/W]
XXXXXXXX XXXXXXXX
OCCP3 [R/W]
XXXXXXXX XXXXXXXX
000198H
SGCRH [R/W]
0000 - - 00
00019CH
SGAR [R/W]
00000000
0001A0H
SGCRL [R/W]
- - 0 - - 000
Reserved
ADERH [R/W]
00000000 00000000
SGFR [R/W, R]
XXXXXXXX XXXXXXXX
SGTR [R/W]
XXXXXXXX
SGDR [R/W]
XXXXXXXX
ADCS1 [R/W]
00000000
ADCS0 [R/W]
00000000
ADCR1 [R]
000000XX
ADCR0 [R]
XXXXXXXX
0001A8H
ADCT1 [R/W]
00010000
ADCT0 [R/W]
00101100
ADSCH [R/W]
- - - 00000
ADECH [R/W]
- - - 00000
0001ACH
Reserved
ACSR0 [R/W]
- 11XXX00
TMRLR0 [W]
XXXXXXXX XXXXXXXX
0001B4H
Reserved
0001B8H
TMRLR1 [W]
XXXXXXXX XXXXXXXX
0001BCH
Reserved
0001C0H
TMRLR2 [W]
XXXXXXXX XXXXXXXX
0001C4H
Reserved
Input
Capture
0 to 3
Output
Compare
0 to 3
Sound
Generator
ADERL [R/W]
00000000 00000000
0001A4
0001B0H
Block
Reserved
A/D
Converter
Alarm Comparator 0
TMR0 [R]
XXXXXXXX XXXXXXXX
TMCSRH0
[R/W]
- - - 00000
TMCSRL0
[R/W]
0 - 000000
Reload Timer 0
TMR1 [R]
XXXXXXXX XXXXXXXX
TMCSRH1
[R/W]
- - - 00000
TMCSRL1
[R/W]
0 - 000000
TMR2 [R]
XXXXXXXX XXXXXXXX
TMCSRH2
[R/W]
- - - 00000
TMCSRL2
[R/W]
0 - 000000
Reload Timer 1
Reload Timer 2
(PPG 4, PPG 5)
(Continued)
48
DS07-16612-2E
MB91460D Series
(Continued)
Address
Register
+0
+1
0001C8H
TMRLR3 [W]
XXXXXXXX XXXXXXXX
0001CCH
Reserved
0001D0H
TMRLR4 [W]
XXXXXXXX XXXXXXXX
0001D4H
Reserved
0001D8H
TMRLR5 [W]
XXXXXXXX XXXXXXXX
0001DCH
Reserved
0001E0H
TMRLR6 [W]
XXXXXXXX XXXXXXXX
0001E4H
Reserved
0001E8H
TMRLR7 [W]
XXXXXXXX XXXXXXXX
0001ECH
Reserved
0001F0H
TCDT0 [R/W]
XXXXXXXX XXXXXXXX
+2
+3
TMR3 [R]
XXXXXXXX XXXXXXXX
TMCSRH3
[R/W]
- - - 00000
TMCSRL3
[R/W]
0 - 000000
TMR4 [R]
XXXXXXXX XXXXXXXX
TMCSRH4
[R/W]
- - - 00000
TMCSRL4
[R/W]
0 - 000000
TMR5 [R]
XXXXXXXX XXXXXXXX
TMCSRH5
[R/W]
- - - 00000
TMCSRL5
[R/W]
0 - 000000
TMR6 [R]
XXXXXXXX XXXXXXXX
TMCSRH6
[R/W]
- - - 00000
TMCSRL6
[R/W]
0 - 000000
TMR7 [R]
XXXXXXXX XXXXXXXX
TMCSRH7
[R/W]
- - - 00000
TMCSRL7
[R/W]
0 - 000000
Reserved
TCCS0 [R/W]
00000000
Block
Reload Timer 3
(PPG 6, PPG 7)
Reload Timer 4
(PPG 8, PPG 9)
Reload Timer 5
(PPG 10, PPG 11)
Reload Timer 6
(PPG 12, PPG 13)
Reload Timer 7
(PPG 14, PPG 15)
(A/D Converter)
Free Running
Timer 0
(ICU 0, ICU 1)
0001F4H
TCDT1 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS1 [R/W]
00000000
Free Running
Timer 1
(ICU 2, ICU 3)
0001F8H
TCDT2 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS2 [R/W]
00000000
Free Running
Timer 2
(OCU 0, OCU 1)
0001FCH
TCDT3 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS3 [R/W]
00000000
Free Running
Timer 3
(OCU 2, OCU 3)
(Continued)
DS07-16612-2E
49
MB91460D Series
(Continued)
Address
Register
+0
+1
+2
+3
000200H
DMACA0 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000218H
DMACA3 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W]
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W]
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to
00023CH
Reserved
000240H
DMACR [R/W]
00 - - 0000
Reserved
Reserved
ICS045 [R/W]
00000000
Reserved
Reserved
ICS67 [R/W]
00000000
0002D4H
IPCP4 [R]
XXXXXXXX XXXXXXXX
IPCP5 [R]
XXXXXXXX XXXXXXXX
0002D8H
IPCP6 [R]
XXXXXXXX XXXXXXXX
IPCP7 [R]
XXXXXXXX XXXXXXXX
0002DCH
to
0002ECH
0002F0H
DMAC
Reserved
000244H
to
0002CCH
0002D0H
Block
Reserved
TCDT4 [R/W]
XXXXXXXX XXXXXXXX
Reserved
Input
Capture
4 to 7
Reserved
TCCS4 [R/W]
00000000
Free Running
Timer 4
(ICU 4, ICU 5)
(Continued)
50
DS07-16612-2E
MB91460D Series
(Continued)
Register
Address
+0
+1
TCDT5 [R/W]
XXXXXXXX XXXXXXXX
0002F4H
+2
+3
Reserved
TCCS5 [R/W]
00000000
Block
Free Running
Timer 5
(ICU 6, ICU 7)
0002F8H
TCDT6 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS6 [R/W]
00000000
Free Running
Timer 6
0002FCH
TCDT7 [R/W]
XXXXXXXX XXXXXXXX
Reserved
TCCS7 [R/W]
00000000
Free Running
Timer 7
000300H
Reserved
UDRC0 [W]
00000000
Reserved
UDCR0 [R]
00000000
000304H
UDCCH0 [R/W]
00000000
UDCCL0 [R/W]
00001000
Reserved
UDCS0 [R/W]
00000000
000308H,
00030CH
Reserved
Reserved
000310H
UDRC3 [W]
00000000
UDRC2 [W]
00000000
UDCR3 [R]
00000000
UDCR2 [R]
00000000
000314H
UDCCH2 [R/W]
00000000
UDCCL2 [R/W]
00001000
Reserved
UDCS2 [R/W]
00000000
000318H
UDCCH3 [R/W]
00000000
UDCCL3 [R/W]
00001000
Reserved
UDCS3 [R/W]
00000000
00031CH
000320H
Reserved
GCN13 [R/W]
00110010 00010000
000324H
to
00032CH
PTMR12 [R]
11111111 11111111
000334H
PDUT12 [W]
XXXXXXXX XXXXXXXX
000338H
PTMR13 [R]
11111111 11111111
00033CH
PDUT13 [W]
XXXXXXXX XXXXXXXX
000340H
PTMR14 [R]
11111111 11111111
000344H
PDUT14 [W]
XXXXXXXX XXXXXXXX
Up/Down
Counter
2 to 3
Reserved
Reserved
GCN23 [R/W]
- - - - 0000
Reserved
000330H
Up/Down
Counter
0
PPG Control
12 to 15
Reserved
PCSR12 [W]
XXXXXXXX XXXXXXXX
PCNH12 [R/W]
0000000 -
PCNL12 [R/W]
000000 - 0
PCSR13 [W]
XXXXXXXX XXXXXXXX
PCNH13 [R/W]
0000000 -
PCNL13 [R/W]
000000 - 0
PCSR14 [W]
XXXXXXXX XXXXXXXX
PCNH14 [R/W]
0000000 -
PCNL14 [R/W]
000000 - 0
PPG 12
PPG 13
PPG 14
(Continued)
DS07-16612-2E
51
MB91460D Series
(Continued)
Address
Register
+0
+1
000348H
PTMR15 [R]
11111111 11111111
00034CH
PDUT15 [W]
XXXXXXXX XXXXXXXX
000350H
to
000364H
+2
+3
PCSR15 [W]
XXXXXXXX XXXXXXXX
PCNH15 [R/W]
0000000 -
PCNL15 [R/W]
000000 - 0
Reserved
PPG 15
Reserved
000368H
IBCR2 [R/W]
00000000
IBSR2 [R]
00000000
ITBAH2 [R/W]
- - - - - - 00
ITBAL2 [R/W]
00000000
00036CH
ITMKH2 [R/W]
00 - - - - 11
ITMKL2 [R/W]
11111111
ISMK2 [R/W]
01111111
ISBA2 [R/W]
- 0000000
000370H
Reserved
IDAR2 [R/W]
00000000
ICCR2 [R/W]
00011111
Reserved
000374H
IBCR3 [R/W]
00000000
IBSR3 [R]
00000000
ITBAH3 [R/W]
- - - - - - 00
ITBAL3 [R/W]
00000000
000378H
ITMKH3 [R/W]
00 - - - - 11
ITMKL3 [R/W]
11111111
ISMK3 [R/W]
01111111
ISBA3 [R/W]
- 0000000
00037CH
Reserved
IDAR3 [R/W]
00000000
ICCR3 [R/W]
00011111
Reserved
000380H
to
00038CH
Block
Reserved
I2C 2
I2C 3
Reserved
ROMS [R]
000390H
11111111 00000000 (MB91F467Dx)
11111111 01000011 (MB91F465DA)
Reserved
000394H
to
0003ECH
Reserved
0003F0H
BSD0 [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
000400H
to
00043CH
Reserved
ROM Select Register
Reserved
Bit Search Module
Reserved
(Continued)
52
DS07-16612-2E
MB91460D Series
(Continued)
Register
Address
+0
+1
+2
+3
000440H
ICR00 [R/W]
---11111
ICR01 [R/W]
---11111
ICR02 [R/W]
---11111
ICR03 [R/W]
---11111
000444H
ICR04 [R/W]
---11111
ICR05 [R/W]
---11111
ICR06 [R/W]
---11111
ICR07 [R/W]
---11111
000448H
ICR08 [R/W]
---11111
ICR09 [R/W]
---11111
ICR10 [R/W]
---11111
ICR11 [R/W]
---11111
00044CH
ICR12 [R/W]
---11111
ICR13 [R/W]
---11111
ICR14 [R/W]
---11111
ICR15 [R/W]
---11111
000450H
ICR16 [R/W]
---11111
ICR17 [R/W]
---11111
ICR18 [R/W]
---11111
ICR19 [R/W]
---11111
000454H
ICR20 [R/W]
---11111
ICR21 [R/W]
---11111
ICR22 [R/W]
---11111
ICR23 [R/W]
---11111
000458H
ICR24 [R/W]
---11111
ICR25 [R/W]
---11111
ICR26 [R/W]
---11111
ICR27 [R/W]
---11111
00045CH
ICR28 [R/W]
---11111
ICR29 [R/W]
---11111
ICR30 [R/W]
---11111
ICR31 [R/W]
---11111
000460H
ICR32 [R/W]
---11111
ICR33 [R/W]
---11111
ICR34 [R/W]
---11111
ICR35 [R/W]
---11111
000464H
ICR36 [R/W]
---11111
ICR37 [R/W]
---11111
ICR38 [R/W]
---11111
ICR39 [R/W]
---11111
000468H
ICR40 [R/W]
---11111
ICR41 [R/W]
---11111
ICR42 [R/W]
---11111
ICR43 [R/W]
---11111
00046CH
ICR44 [R/W]
---11111
ICR45 [R/W]
---11111
ICR46 [R/W]
---11111
ICR47 [R/W]
---11111
000470H
ICR48 [R/W]
---11111
ICR49 [R/W]
---11111
ICR50 [R/W]
---11111
ICR51 [R/W]
---11111
000474H
ICR52 [R/W]
---11111
ICR53 [R/W]
---11111
ICR54 [R/W]
---11111
ICR55 [R/W]
---11111
000478H
ICR56 [R/W]
---11111
ICR57 [R/W]
---11111
ICR58 [R/W]
---11111
ICR59 [R/W]
---11111
00047CH
ICR60 [R/W]
---11111
ICR61 [R/W]
---11111
ICR62 [R/W]
---11111
ICR63 [R/W]
---11111
000480H
RSRR [R/W]
10000000
STCR [R/W]
00110011
TBCR [R/W]
00XXX - 00
CTBR [W]
XXXXXXXX
000484H
CLKR [R/W]
---- 0000
WPR [W]
XXXXXXXX
DIVR0 [R/W]
00000011
DIVR1 [R/W]
00000000
000488H
DS07-16612-2E
Reserved
Block
Interrupt
Controller
Clock
Control
Reserved
(Continued)
53
MB91460D Series
(Continued)
Address
Register
+0
+1
+2
+3
00048CH
PLLDIVM [R/W]
- - - - 0000
PLLDIVN [R/W]
- - 000000
PLLDIVG [R/W]
- - - - 0000
PLLMULG [W]
00000000
000490H
PLLCTRL [R/W]
- - - - 0000
000494H
OSCC1 [R/W]
- - - - - 010
000498H
PORTEN [R/W]
- - - - - - 00
Block
PLL Interface
Reserved
OSCS1 [R/W]
00001111
OSCC2 [R/W]
- - - - - 010
OSCS2 [R/W]
00001111
Port Input Enable
Control
Reserved
00049CH
Reserved
WTCER [R/W]
- - - - - - 00
Main/Sub
Oscillator
Control
Reserved
WTCR [R/W]
00000000 000 - 00 - 0
0004A0H
Reserved
0004A4H
Reserved
0004A8H
WTHR [R/W]
- - - 00000
WTMR [R/W]
- - 000000
WTSR [R/W]
- - 000000
Reserved
0004ACH
CSVTR [R/W]
- - - 00010
CSVCR [R/W]
00011100
CSCFG [R/W]
0X000000
CMCFG [R/W]
00000000
WTBR [R/W]
- - - XXXXX XXXXXXXX XXXXXXXX
0004B0H
CUCR [R/W]
- - - - - - - - - - - 0 - - 00
CUTD [R/W]
10000000 00000000
0004B4H
CUTR1 [R]
- - - - - - - - 00000000
CUTR2 [R]
00000000 00000000
0004B8H
CMPR [R/W]
- - 000010 11111101
0004BCH
CMT1 [R/W]
00000000 1 - - - 0000
Reserved
CMCR [R/W]
- 001 - - 00
CMT2 [R/W]
- - 000000 - - 000000
Real Time Clock
(Watch Timer)
ClockSupervisor / Selector /
Monitor
Calibration of Sub
Clock
Clock
Modulator
0004C0H
CANPRE [R/W]
0 - - - 0000
CANCKD [R/W]
- - - - - 000*1
0004C4H
LVSEL [R/W]
00000111
LVDET [R/W]
0000 0 - 00
HWWDE [R/W]
- - - - - - 00
0004C8H
OSCRH [R/W]
000 - - 001
OSCRL [R/W]
- - - - - 000
WPCRH [R/W]
00 - - - 000
WPCRL [R/W]
- - - - - - 00
Main-/Sub-Oscillation
Stabilisation Timer
0004CCH
OSCCR [R/W]
-------0
Reserved
REGSEL [R/W]
- - 000100
REGCTR [R/W]
- - - 0 - - 00
Main- Oscillation
Standby Control
Main-/Sub regulator
Control
0004D0H
to
00063CH
Reserved
Reserved
CAN Clock Control
HWWD [R/W, W] Low Voltage Detection/
00011000
Hardware Watchdog
Reserved
(Continued)
54
DS07-16612-2E
MB91460D Series
(Continued)
Register
Address
+0
+1
+2
+3
000640H
ASR0 [R/W]
00000000 00000000
ACR0 [R/W]
1111**00 00100000*2
000644H
ASR1 [R/W]
XXXXXXXX XXXXXXXX
ACR1 [R/W]
XXXXXXXX XXXXXXXX
000648H
ASR2 [R/W]
XXXXXXXX XXXXXXXX
ACR2 [R/W]
XXXXXXXX XXXXXXXX
00064CH
ASR3 [R/W]
XXXXXXXX XXXXXXXX
ACR3 [R/W]
XXXXXXXX XXXXXXXX
000650H
ASR4 [R/W]
XXXXXXXX XXXXXXXX
ACR4 [R/W]
XXXXXXXX XXXXXXXX
000654H
ASR5 [R/W]
XXXXXXXX XXXXXXXX
ACR5 [R/W]
XXXXXXXX XXXXXXXX
000658H
ASR6 [R/W]
XXXXXXXX XXXXXXXX
ACR6 [R/W]
XXXXXXXX XXXXXXXX
00065CH
ASR7 [R/W]
XXXXXXXX XXXXXXXX
ACR7 [R/W]
XXXXXXXX XXXXXXXX
000660H
AWR0 [R/W]
01001111 11111011
AWR1 [R/W]
XXXXXXXX XXXXXXXX
000664H
AWR2 [R/W]
XXXXXXXX XXXXXXXX
AWR3 [R/W]
XXXXXXXX XXXXXXXX
000668H
AWR4 [R/W]
XXXXXXXX XXXXXXXX
AWR5 [R/W]
XXXXXXXX XXXXXXXX
00066CH
AWR6 [R/W]
XXXXXXXX XXXXXXXX
AWR7 [R/W]
XXXXXXXX XXXXXXXX
000670H
MCRA [R/W]
XXXXXXXX
000674H
000678H
MCRB [R/W]
XXXXXXXX
Block
External Bus
Reserved
Reserved
IORW0 [R/W]
XXXXXXXX
00067CH
IORW1 [R/W]
XXXXXXXX
IORW2 [R/W]
XXXXXXXX
Reserved
Reserved
000680H
CSER [R/W]
00000001
CHER [R/W]
11111111
000684H
RCRH [R/W]
00XXXXXX
RCRL [R/W]
XXXX0XXX
000688H
to
0007F8H
0007FCH
Reserved
TCR [R/W]
0000**** *3
Reserved
Reserved
Reserved
MODR [W]
XXXXXXXX
Reserved
Mode Register
(Continued)
DS07-16612-2E
55
MB91460D Series
(Continued)
Address
Register
+0
000800H
to
000CFCH
+1
+2
+3
Reserved
Reserved
000D00H
PDRD00 [R]
XXXXXXXX
PDRD01 [R]
XXXXXXXX
PDRD02 [R]
XXXXXXXX
PDRD03 [R]
XXXXXXXX
000D04H
PDRD04 [R]
- - - - - - XX
PDRD05 [R]
XXXXXXXX
PDRD06 [R]
XXXXXXXX
PDRD07 [R]
XXXXXXXX
000D08H
PDRD08 [R]
XXXXXXXX
PDRD09 [R]
XX - - XXXX
PDRD10 [R]
- XXXXXX -
Reserved
000D0CH
Reserved
PDRD13 [R]
- - - - - XXX
PDRD14 [R]
XXXXXXXX
PDRD15 [R]
- - - - XXXX
000D10H
PDRD16 [R]
XXXXXXXX
PDRD17 [R]
XXXX - - - -
PDRD18 [R]
- XXX - XXX
PDRD19 [R]
- XXX - XXX
000D14H
PDRD20 [R]
- - - - - XXX
Reserved
PDRD22 [R]
- - XX - X - X
PDRD23 [R]
- - XXXXXX
000D18H
PDRD24 [R]
XXXXXXXX
PDRD25 [R]
XXXXXXXX
PDRD26 [R]
XXXXXXXX
PDRD27 [R]
XXXXXXXX
000D1CH
Reserved
PDRD29 [R]
XXXXXXXX
000D20H
to
000D3CH
R-bus
Port Data
Direct Read
Register
Reserved
Reserved
Reserved
000D40H
DDR00 [R/W]
00000000
DDR01 [R/W]
00000000
DDR02 [R/W]
00000000
DDR03 [R/W]
00000000
000D44H
DDR04 [R/W]
- - - - - - 00
DDR05 [R/W]
00000000
DDR06 [R/W]
00000000
DDR07 [R/W]
00000000
000D48H
DDR08 [R/W]
00000000
DDR09 [R/W]
00 - - 0000
DDR10 [R/W]
- 000000 -
Reserved
000D4CH
Reserved
DDR13 [R/W]
- - - - - 000
DDR14 [R/W]
00000000
DDR15 [R/W]
- - - - 0000
000D50H
DDR16 [R/W]
00000000
DDR17 [R/W]
0000 - - - -
DDR18 [R/W]
- 000 - 000
DDR19 [R/W]
- 000 - 000
000D54H
DDR20 [R/W]
- - - - - 000
Reserved
DDR22 [R/W]
- - 00 - 0 - 0
DDR23 [R/W]
- - 000000
000D58H
DDR24 [R/W]
00000000
DDR25 [R/W]
00000000
DDR26 [R/W]
00000000
DDR27 [R/W]
00000000
000D5CH
Reserved
DDR29 [R/W]
00000000
000D60H
to
000D7CH
Block
Reserved
R-bus
Port Direction
Register
Reserved
Reserved
(Continued)
56
DS07-16612-2E
MB91460D Series
(Continued)
Register
Address
+0
+1
+2
+3
000D80H
PFR00 [R/W]
11111111
PFR01 [R/W]
11111111
PFR02 [R/W]
11111111
PFR03 [R/W]
11111111
000D84H
PFR04 [R/W]
- - - - - - 11
PFR05 [R/W]
11111111
PFR06 [R/W]
11111111
PFR07 [R/W]
11111111
000D88H
PFR08 [R/W]
11111111
PFR09 [R/W]
11 - - 1111
PFR10 [R/W]
- 111111 -
Reserved
000D8CH
Reserved
PFR13 [R/W]
- - - - - 000
PFR14 [R/W]
00000000
PFR15 [R/W]
- - - - 0000
000D90H
PFR16 [R/W]
00000000
PFR17 [R/W]
0000 - - - -
PFR18 [R/W]
- 000 - 000
PFR19 [R/W]
- 000 - 000
000D94H
PFR20 [R/W]
- - - - - 000
Reserved
PFR22 [R/W]
- - 00 - 0 - 0
PFR23 [R/W]
- - 000000
000D98H
PFR24 [R/W]
00000000
PFR25 [R/W]
00000000
PFR26 [R/W]
00000000
PFR27 [R/W]
00000000
000D9CH
Reserved
PFR29 [R/W]
00000000
000DA0H
to
000DBCH
R-bus
Port Function
Register
Reserved
Reserved
Reserved
000DC0H
EPFR00 [R/W]
--------
EPFR01 [R/W]
--------
EPFR02 [R/W]
--------
EPFR03 [R/W]
--------
000DC4H
EPFR04 [R/W]
--------
EPFR05 [R/W]
--------
EPFR06 [R/W]
--------
EPFR07 [R/W]
--------
000DC8H
EPFR08 [R/W]
--------
EPFR09 [R/W]
--------
EPFR10 [R/W]
- - 00 - - - -
Reserved
000DCCH
Reserved
EPFR13 [R/W]
-----0--
EPFR14 [R/W]
00000000
EPFR15 [R/W]
- - - - 0000
000DD0H
EPFR16 [R/W]
0000 - - - -
EPFR17 [R/W]
--------
EPFR18 [R/W]
- 00 - - 00 -
EPFR19 [R/W]
-0---0--
000DD4H
EPFR20 [R/W]
- - - - - 00 -
Reserved
EPFR22 [R/W]
--------
EPFR23 [R/W]
--------
000DD8H
EPFR24 [R/W]
--------
EPFR25 [R/W]
--------
EPFR26 [R/W]
00000000
EPFR27 [R/W]
00000000
000DDCH
Reserved
EPFR29 [R/W]
--------
000DE0H
to
000DFCH
Block
Reserved
R-bus Extra
Port Function
Register
Reserved
Reserved
(Continued)
DS07-16612-2E
57
MB91460D Series
(Continued)
Address
Register
+0
+1
+2
+3
000E00H
PODR00 [R/W]
00000000
PODR01 [R/W]
00000000
PODR02 [R/W]
00000000
PODR03 [R/W]
00000000
000E04H
PODR04 [R/W]
- - - - - - 00
PODR05 [R/W]
00000000
PODR06 [R/W]
00000000
PODR07 [R/W]
00000000
000E08H
PODR08 [R/W]
00000000
PODR09 [R/W]
00 - - 0000
PODR10 [R/W]
- 000000 -
Reserved
000E0CH
Reserved
PODR13 [R/W]
- - - - - 000
PODR14 [R/W]
00000000
PODR15 [R/W]
- - - - 0000
000E10H
PODR16 [R/W]
00000000
PODR17 [R/W]
0000 - - - -
PODR18 [R/W]
- 000 - 000
PODR19 [R/W]
- 000 - 000
000E14H
PODR20 [R/W]
- - - - - 000
Reserved
PODR22 [R/W]
- - 00 - 0 - 0
PODR23 [R/W]
- - 000000
000E18H
PODR24 [R/W]
00000000
PODR25 [R/W]
00000000
PODR26 [R/W]
00000000
PODR27 [R/W]
00000000
000E1CH
Reserved
PODR29 [R/W]
00000000
000E20H
to
000E3CH
R-bus Port
Output Drive Select
Register
Reserved
Reserved
Reserved
000E40H
PILR00 [R/W]
00000000
PILR01 [R/W]
00000000
PILR02 [R/W]
00000000
PILR03 [R/W]
00000000
000E44H
PILR04 [R/W]
- - - - - - 00
PILR05 [R/W]
00000000
PILR06 [R/W]
00000000
PILR07 [R/W]
00000000
000E48H
PILR08 [R/W]
00000000
PILR09 [R/W]
00 - - 0000
PILR10 [R/W]
- 000000 -
Reserved
000E4CH
Reserved
PILR13 [R/W]
- - - - - 000
PILR14 [R/W]
00000000
PILR15 [R/W]
- - - - 0000
000E50H
PILR16 [R/W]
00000000
PILR17 [R/W]
0000 - - - -
PILR18 [R/W]
- 000 - 000
PILR19 [R/W]
- 000 - 000
000E54H
PILR20 [R/W]
- - - - - 000
Reserved
PILR22 [R/W]
- - 00 - 0 - 0
PILR23 [R/W]
- - 000000
000E58H
PILR24 [R/W]
00000000
PILR25 [R/W]
00000000
PILR26 [R/W]
00000000
PILR27 [R/W]
00000000
000E5CH
Reserved
PILR29 [R/W]
00000000
000E60H
to
000E7CH
Block
Reserved
R-bus Port
Input Level Select
Register
Reserved
Reserved
(Continued)
58
DS07-16612-2E
MB91460D Series
(Continued)
Register
Address
+0
+1
+2
+3
000E80H
EPILR00 [R/W]
00000000
EPILR01 [R/W]
00000000
EPILR02 [R/W]
00000000
EPILR03 [R/W]
00000000
000E84H
EPILR04 [R/W]
- - - - - - 00
EPILR05 [R/W]
00000000
EPILR06 [R/W]
00000000
EPILR07 [R/W]
00000000
000E88H
EPILR08 [R/W]
00000000
EPILR09 [R/W]
00 - - 0000
EPILR10 [R/W]
- 000000 -
Reserved
000E8CH
Reserved
EPILR13 [R/W]
- - - - - 000
EPILR14 [R/W]
00000000
EPILR15 [R/W]
- - - - 0000
000E90H
EPILR16 [R/W]
00000000
EPILR17 [R/W]
0000 - - - -
EPILR18 [R/W]
- 000 - 000
EPILR19 [R/W]
- 000 - 000
000E94H
EPILR20 [R/W]
- - - - - 000
Reserved
EPILR22 [R/W]
- - 00 - 0 - 0
EPILR23 [R/W]
- - 000000
000E98H
EPILR24 [R/W]
00000000
EPILR25 [R/W]
00000000
EPILR26 [R/W]
00000000
EPILR27 [R/W]
00000000
000E9CH
Reserved
EPILR29 [R/W]
00000000
000EA0H
to
000EBCH
R-bus Extra
Port Input Level
Select Register
Reserved
Reserved
Reserved
000EC0H
PPER00 [R/W]
00000000
PPER01 [R/W]
00000000
PPER02 [R/W]
00000000
PPER03 [R/W]
00000000
000EC4H
PPER04 [R/W]
- - - - - - 00
PPER05 [R/W]
00000000
PPER06 [R/W]
00000000
PPER07 [R/W]
00000000
000EC8H
PPER08 [R/W]
00000000
PPER09 [R/W]
00 - - 0000
PPER10 [R/W]
- 000000 -
Reserved
000ECCH
Reserved
PPER13 [R/W]
- - - - - 000
PPER14 [R/W]
00000000
PPER15 [R/W]
- - - - 0000
000ED0H
PPER16 [R/W]
00000000
PPER17 [R/W]
0000 - - - -
PPER18 [R/W]
- 000 - 000
PPER19 [R/W]
- 000 - 000
000ED4H
PPER20 [R/W]
- - - - - 000
Reserved
PPER22 [R/W]
- - 00 - 0 - 0
PPER23 [R/W]
- - 000000
000ED8H
PPER24 [R/W]
00000000
PPER25 [R/W]
00000000
PPER26 [R/W]
00000000
PPER27 [R/W]
00000000
000EDCH
Reserved
PPER29 [R/W]
00000000
000EE0H
to
000EFCH
Block
Reserved
R-bus Port
Pull-Up/Down Enable
Register
Reserved
Reserved
(Continued)
DS07-16612-2E
59
MB91460D Series
(Continued)
Address
Register
+0
+1
+2
+3
000F00H
PPCR00 [R/W]
11111111
PPCR01 [R/W]
11111111
PPCR02 [R/W]
11111111
PPCR03 [R/W]
11111111
000F04H
PPCR04 [R/W]
- - - - - - 11
PPCR05 [R/W]
11111111
PPCR06 [R/W]
11111111
PPCR07 [R/W]
11111111
000F08H
PPCR08 [R/W]
11111111
PPCR09 [R/W]
11 - - 1111
PPCR10 [R/W]
- 111111 -
Reserved
000F0CH
Reserved
PPCR13 [R/W]
- - - - - 111
PPCR14 [R/W]
11111111
PPCR15 [R/W]
- - - - 1111
000F10H
PPCR16 [R/W]
11111111
PPCR17 [R/W]
1111 - - - -
PPCR18 [R/W]
- 111 - 111
PPCR19 [R/W]
- 111 - 111
000F14H
PPCR20 [R/W]
- - - - - 111
Reserved
PPCR22 [R/W]
- - 11 - 1 - 1
PPCR23 [R/W]
- - 111111
000F18H
PPCR24 [R/W]
11111111
PPCR25 [R/W]
11111111
PPCR26 [R/W]
11111111
PPCR27 [R/W]
11111111
000F1CH
Reserved
PPCR29 [R/W]
11111111
Block
R-bus Port
Pull-Up/Down Control
Register
Reserved
000F20H
to
000F3CH
Reserved
001000H
DMASA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
to
001FFCH
Reserved
Reserved
DMAC
Reserved
(Continued)
60
DS07-16612-2E
MB91460D Series
(Continued)
Register
Address
+0
002000H
to
006FFCH
007000H
+1
+2
+3
MB91F467Dx Flash-cache size is 8 Kbytes : 004000H to 005FFCH
MB91F465DA Flash-cache size is 8 Kbytes : 004000H to 005FFCH
FMCS [R/W]
01101000
007004H
FMCR [R]
- - - 00000
FMWT [R/W]
11111111 11111111
FCHCR [R/W]
- - - - - - 00 10000011
FMWT2 [R]
- 001 - - - -
FMPS [R/W]
- - - - - 000
Block
Flash-cache /
I-RAM area
Flash Memory/
Flash-cache/
I-RAM Control
Register
007008H
FMAC [R]
00000000 00000000 00000000 00000000
00700CH
FCHA0 [R/W]
- - - - - - - - - - - 00000 00000000 00000000
007010H
FCHA1 [R/W]
- - - - - - - - - - - 00000 00000000 00000000
007014H
to
007FFCH
Reserved
Reserved
008000H
to
00BFFCH
MB91F467Dx Boot-ROM size is 4 Kbytes : 00B000H to 00BFFCH
MB91F465DA Boot-ROM size is 4 Kbytes : 00B000H to 00BFFCH
(instruction access is 1 wait cycle, data access is 1 wait cycle)
Boot ROM area
00C000H
CTRLR0 [R/W]
00000000 00000001
STATR0 [R/W]
00000000 00000000
00C004H
ERRCNT0 [R]
00000000 00000000
BTR0 [R/W]
00100011 00000001
00C008H
INTR0 [R]
00000000 00000000
TESTR0 [R/W]
00000000 X0000000
00C00CH
BRPE0 [R/W]
00000000 00000000
Reserved
00C010H
IF1CREQ0 [R/W]
00000000 00000001
IF1CMSK0 [R/W]
00000000 00000000
00C014H
IF1MSK20 [R/W]
11111111 11111111
IF1MSK10 [R/W]
11111111 11111111
00C018H
IF1ARB20 [R/W]
00000000 00000000
IF1ARB10 [R/W]
00000000 00000000
00C01CH
IF1MCTR0 [R/W]
00000000 00000000
Reserved
Flash-cache Noncacheable area setting
Register
CAN 0
Control
Register
CAN 0
IF 1 Register
(Continued)
DS07-16612-2E
61
MB91460D Series
(Continued)
Address
Register
+0
+1
+2
+3
00C020H
IF1DTA10 [R/W]
00000000 00000000
IF1DTA20 [R/W]
00000000 00000000
00C024H
IF1DTB10 [R/W]
00000000 00000000
IF1DTB20 [R/W]
00000000 00000000
00C028H,
00C02CH
Reserved
00C030H
IF1DTA20 [R/W]
00000000 00000000
IF1DTA10 [R/W]
00000000 00000000
00C034H
IF1DTB20 [R/W]
00000000 00000000
IF1DTB10 [R/W]
00000000 00000000
00C038H,
00C03CH
CAN 0
IF 1 Register
Reserved
00C040H
IF2CREQ0 [R/W]
00000000 00000001
IF2CMSK0 [R/W]
00000000 00000000
00C044H
IF2MSK20 [R/W]
11111111 11111111
IF2MSK10 [R/W]
11111111 11111111
00C048H
IF2ARB20 [R/W]
00000000 00000000
IF2ARB10 [R/W]
00000000 00000000
00C04CH
IF2MCTR0 [R/W]
00000000 00000000
Reserved
00C050H
IF2DTA10 [R/W]
00000000 00000000
IF2DTA20 [R/W]
00000000 00000000
00C054H
IF2DTB10 [R/W]
00000000 00000000
IF2DTB20 [R/W]
00000000 00000000
00C058H,
00C05CH
CAN 0
IF 2 Register
Reserved
00C060H
IF2DTA20 [R/W]
00000000 00000000
IF2DTA10 [R/W]
00000000 00000000
00C064H
IF2DTB20 [R/W]
00000000 00000000
IF2DTB10 [R/W]
00000000 00000000
00C068H
to
00C07CH
Block
Reserved
(Continued)
62
DS07-16612-2E
MB91460D Series
(Continued)
Address
00C080H
Register
+0
+1
TREQR20 [R]
00000000 00000000
00C084H
to
00C08CH
00C090H
Block
TREQR10 [R]
00000000 00000000
NEWDT20 [R]
00000000 00000000
NEWDT10 [R]
00000000 00000000
CAN 0
Status Flags
Reserved
INTPND20 [R]
00000000 00000000
00C0A4H
to
00C0ACH
00C0B0H
+3
Reserved
00C094H
to
00C09CH
00C0A0H
+2
INTPND10 [R]
00000000 00000000
Reserved
MSGVAL20 [R]
00000000 00000000
00C0B4H
to
00C0FCH
MSGVAL10 [R]
00000000 00000000
Reserved
Reserved
00C100H
CTRLR1 [R/W]
00000000 00000001
STATR1 [R/W]
00000000 00000000
00C104H
ERRCNT1 [R]
00000000 00000000
BTR1 [R/W]
00100011 00000001
00C108H
INTR1 [R]
00000000 00000000
TESTR1 [R/W]
00000000 X0000000
00C10CH
BRPE1 [R/W]
00000000 00000000
Reserved
00C110H
IF1CREQ1 [R/W]
00000000 00000001
IF1CMSK1 [R/W]
00000000 00000000
00C114H
IF1MSK21 [R/W]
11111111 11111111
IF1MSK11 [R/W]
11111111 11111111
00C118H
IF1ARB21 [R/W]
00000000 00000000
IF1ARB11 [R/W]
00000000 00000000
00C11CH
IF1MCTR1 [R/W]
00000000 00000000
Reserved
00C120H
IF1DTA11 [R/W]
00000000 00000000
IF1DTA21 [R/W]
00000000 00000000
00C124H
IF1DTB11 [R/W]
00000000 00000000
IF1DTB21 [R/W]
00000000 00000000
CAN 1
Control
Register
CAN 1
IF 1 Register
(Continued)
DS07-16612-2E
63
MB91460D Series
(Continued)
Address
Register
+0
+1
00C128H,
00C12CH
+2
+3
Reserved
00C130H
IF1DTA21 [R/W]
00000000 00000000
IF1DTA11 [R/W]
00000000 00000000
00C134H
IF1DTB21 [R/W]
00000000 00000000
IF1DTB11 [R/W]
00000000 00000000
00C138H,
00C13CH
IF2CREQ1 [R/W]
00000000 00000001
IF2CMSK1 [R/W]
00000000 00000000
00C144H
IF2MSK21 [R/W]
11111111 11111111
IF2MSK11 [R/W]
11111111 11111111
00C148H
IF2ARB21 [R/W]
00000000 00000000
IF2ARB11 [R/W]
00000000 00000000
00C14CH
IF2MCTR1 [R/W]
00000000 00000000
Reserved
00C150H
IF2DTA11 [R/W]
00000000 00000000
IF2DTA21 [R/W]
00000000 00000000
00C154H
IF2DTB11 [R/W]
00000000 00000000
IF2DTB21 [R/W]
00000000 00000000
00C158H,
00C15CH
IF2DTA21 [R/W]
00000000 00000000
IF2DTA11 [R/W]
00000000 00000000
00C164H
IF2DTB21 [R/W]
00000000 00000000
IF2DTB11 [R/W]
00000000 00000000
00C168H
to
00C17CH
Reserved
TREQR21 [R]
00000000 00000000
00C184H
to
00C18CH
00C194H
to
00C19CH
CAN 1
IF 2 Register
Reserved
00C160H
00C190H
CAN 1
IF 1 Register
Reserved
00C140H
00C180H
Block
TREQR11 [R]
00000000 00000000
Reserved
NEWDT21 [R]
00000000 00000000
NEWDT11 [R]
00000000 00000000
CAN 1
Status Flags
Reserved
(Continued)
64
DS07-16612-2E
MB91460D Series
(Continued)
Address
00C1A0H
Register
+0
+1
INTPND21 [R]
00000000 00000000
00C1A4H
to
00C1ACH
00C1B0H
+2
+3
INTPND11 [R]
00000000 00000000
Reserved
MSGVAL21 [R]
00000000 00000000
00C1B4H
to
00C1FCH
MSGVAL11 [R]
00000000 00000000
CAN 1
Status Flags
Reserved
00C200H
CTRLR2 [R/W]
00000000 00000001
STATR2 [R/W]
00000000 00000000
00C204H
ERRCNT2 [R]
00000000 00000000
BTR2 [R/W]
00100011 00000001
00C208H
INTR2 [R]
00000000 00000000
TESTR2 [R/W]
00000000 X0000000
00C20CH
BRPE2 [R/W]
00000000 00000000
Reserved
00C210H
IF1CREQ2 [R/W]
00000000 00000001
IF1CMSK2 [R/W]
00000000 00000000
00C214H
IF1MSK22 [R/W]
11111111 11111111
IF1MSK12 [R/W]
11111111 11111111
00C218H
IF1ARB22 [R/W]
00000000 00000000
IF1ARB12 [R/W]
00000000 00000000
00C21CH
IF1MCTR2 [R/W]
00000000 00000000
Reserved
00C220H
IF1DTA12 [R/W]
00000000 00000000
IF1DTA22 [R/W]
00000000 00000000
00C224H
IF1DTB12 [R/W]
00000000 00000000
IF1DTB22 [R/W]
00000000 00000000
00C228H,
00C22CH
CAN 2
Control
Register
CAN 2
IF 1 Register
Reserved
00C230H
IF1DTA22 [R/W]
00000000 00000000
IF1DTA12 [R/W]
00000000 00000000
00C234H
IF1DTB22 [R/W]
00000000 00000000
IF1DTB12 [R/W]
00000000 00000000
00C238H,
00C23CH
Block
Reserved
(Continued)
DS07-16612-2E
65
MB91460D Series
(Continued)
Address
Register
+0
+1
+2
+3
00C240H
IF2CREQ2 [R/W]
00000000 00000001
IF2CMSK2 [R/W]
00000000 00000000
00C244H
IF2MSK22 [R/W]
11111111 11111111
IF2MSK12 [R/W]
11111111 11111111
00C248H
IF2ARB22 [R/W]
00000000 00000000
IF2ARB12 [R/W]
00000000 00000000
00C24CH
IF2MCTR2 [R/W]
00000000 00000000
Reserved
00C250H
IF2DTA12 [R/W]
00000000 00000000
IF2DTA22 [R/W]
00000000 00000000
00C254H
IF2DTB12 [R/W]
00000000 00000000
IF2DTB22 [R/W]
00000000 00000000
00C258H,
00C25CH
IF2DTA22 [R/W]
00000000 00000000
IF2DTA12 [R/W]
00000000 00000000
00C264H
IF2DTB22 [R/W]
00000000 00000000
IF2DTB12 [R/W]
00000000 00000000
00C268H
to
00C27CH
Reserved
TREQR22 [R]
00000000 00000000
00C284H
to
00C28CH
00C290H
NEWDT22 [R]
00000000 00000000
NEWDT12 [R]
00000000 00000000
CAN 2
Status Flags
Reserved
INTPND22 [R]
00000000 00000000
00C2A4H
to
00C2ACH
00C2B0H
TREQR12 [R]
00000000 00000000
Reserved
00C294H
to
00C29CH
00C2A0H
CAN 2
IF 2 Register
Reserved
00C260H
00C280H
Block
INTPND12 [R]
00000000 00000000
Reserved
MSGVAL22 [R]
00000000 00000000
MSGVAL12 [R]
00000000 00000000
(Continued)
66
DS07-16612-2E
MB91460D Series
(Continued)
Address
Register
+0
+1
+2
00C2B4H
to
00EFFCH
Reserved
00F000H
BCTRL [R/W]
- - - - - - - - - - - - - - - - 11111100 00000000
00F004H
BSTAT [R/W]
- - - - - - - - - - - - - 000 00000000 10 - - 0000
00F008H
BIAC [R]
- - - - - - - - - - - - - - - - 00000000 00000000
00F00CH
BOAC [R]
- - - - - - - - - - - - - - - - 00000000 00000000
00F010H
BIRQ [R/W]
- - - - - - - - - - - - - - - - 00000000 00000000
+3
Block
Reserved
EDSU / MPU
00F014H
to
00F01CH
Reserved
00F020H
BCR0 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F024H
BCR1 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F028H
BCR2 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F02CH
BCR3 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F030H
to
00F07CH
Reserved
00F080H
BAD0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F084H
BAD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F088H
BAD2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F08CH
BAD3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F090H
BAD4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F094H
BAD5 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F098H
BAD6 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reserved
EDSU / MPU
(Continued)
DS07-16612-2E
67
MB91460D Series
Address
Register
+0
+1
+2
+3
Block
00F09CH
BAD7 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A0H
BAD8 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A4H
BAD9 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A8H
BAD10 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0ACH
BAD11 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B0H
BAD12 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B4H
BAD13 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B8H
BAD14 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0BCH
BAD15 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0C0H
to
01FFFCH
Reserved
Reserved
020000H
to
02FFFCH
MB91F467Dx D-RAM size is 32 Kbytes : 028000H to 02FFFCH
MB91F465DA D-RAM size is 32 Kbytes : 028000H to 02FFFCH
(data access is 0 wait cycles)
D-RAM area
030000H
to
03FFFCH
MB91F467Dx ID-RAM size is 32 Kbytes : 030000H to 037FFCH
MB91F465DA ID-RAM size is 16 Kbytes : 030000H to 033FFCH
(instruction access is 0 wait cycles, data access is 1 wait cycle)
ID-RAM area
EDSU / MPU
*1 : depends on the number of available CAN channels
*2 : ACR0 [11 : 10] depends on bus width setting in Mode vector fetch information
*3 : TCR [3 : 0] INIT value = 0000, keeps value after RST
68
DS07-16612-2E
MB91460D Series
2.
Flash memory and external bus area
32bit read/write
16bit read/write
Address
dat[31:0]
dat[31:16]
dat[31:0]
dat[15:0]
dat[31:16]
dat[15:0]
Register
+0
+1
+2
+3
+4
+5
+6
+7
Block
040000H
to
05FFF8H
SA8 (64KB, MB91F467Dx)
External bus (MB91F465DA)
SA9 (64KB, MB91F467Dx)
External bus (MB91F465DA)
ROMS0
060000H
to
07FFF8H
SA10 (64KB, MB91F467Dx)
External bus (MB91F465DA)
SA11 (64KB, MB91F467Dx)
External bus (MB91F465DA)
ROMS1
080000H
to
09FFF8H
SA12 (64KB)
SA13 (64KB)
ROMS2
0A0000H
to
0BFFF8H
SA14 (64KB)
SA15 (64KB)
ROMS3
0C0000H
to
0DFFF8H
SA16 (64KB)
SA17 (64KB)
ROMS4
0E0000H
to
0FFFF0H
SA18 (64KB)
SA19 (64KB)
0FFFF8H
FMV [R]
06 00 00 00H
FRV [R]
00 00 BF F8H
100000H
to
11FFF8H
SA20 (64KB, MB91F467Dx)
External bus (MB91F465DA)
SA21 (64KB, MB91F467Dx)
External bus (MB91F465DA)
120000H
to
13FFF8H
SA22 (64KB, MB91F467Dx)
External bus (MB91F465DA)
SA23 (64KB, MB91F467Dx)
External bus (MB91F465DA)
140000H
to
143FF8H
SA0 (8KB, MB91F467Dx)
Reserved (MB91F465DA)
SA1 (8KB, MB91F467Dx)
Reserved (MB91F465DA)
144000H
to
147FF8H
SA2 (8KB, MB91F467Dx)
Reserved (MB91F465DA)
SA3 (8KB, MB91F467Dx)
Reserved (MB91F465DA)
148000H
to
14BFF8H
SA4 (8KB, MB91F467Dx)
SA5 (8KB, MB91F467Dx)
14C000H
to
14FFF8H
SA6 (8KB, MB91F467Dx)
SA7 (8KB, MB91F467Dx)
150000H
to
17FFF8H
DS07-16612-2E
ROMS5
ROMS6
ROMS7
Reserved
69
MB91460D Series
32bit read/write
16bit read/write
Address
dat[31:0]
dat[31:16]
dat[31:0]
dat[15:0]
dat[31:16]
dat[15:0]
Register
+0
+1
+2
+3
+4
+5
+6
+7
Block
180000H
to
1BFFF8H
ROMS8
1C0000H
to
1FFFF8H
ROMS9
200000H
to
27FFF8H
ROMS10
280000H
to
2FFFF8H
ROMS11
300000H
to
37FFF8H
External Bus Area
ROMS12
380000H
to
3FFFF8H
ROMS13
400000H
to
47FFF8H
ROMS14
480000H
to
4FFFF8H
ROMS15
Notes: Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the
values shown above will be read.
On MB91F465DA, write access to the flash is only possible in 16-bit mode.
70
DS07-16612-2E
MB91460D Series
■ INTERRUPT VECTOR TABLE
Interrupt
Interrupt
number
Interrupt level *1
Interrupt vector *2
DMA
Resource
number
Decimal
Hexadecimal
Setting
Register
Register
address
Offset
Default Vector
address
Reset
0
00
⎯
⎯
3FCH
000FFFFCH
⎯
Mode vector
1
01
⎯
⎯
3F8H
000FFFF8H
⎯
System reserved
2
02
⎯
⎯
3F4H
000FFFF4H
⎯
System reserved
3
03
⎯
⎯
3F0H
000FFFF0H
⎯
System reserved
4
04
⎯
⎯
3ECH
000FFFECH
⎯
CPU supervisor mode
(INT #5 instruction) *5
5
05
⎯
⎯
3E8H
000FFFE8H
⎯
Memory Protection exception *5
6
06
⎯
⎯
3E4H
000FFFE4H
⎯
System reserved
7
07
⎯
⎯
3E0H
000FFFE0H
⎯
System reserved
8
08
⎯
⎯
3DCH
000FFFDCH
⎯
System reserved
9
09
⎯
⎯
3D8H
000FFFD8H
⎯
System reserved
10
0A
⎯
⎯
3D4H
000FFFD4H
⎯
System reserved
11
0B
⎯
⎯
3D0H
000FFFD0H
⎯
System reserved
12
0C
⎯
⎯
3CCH
000FFFCCH
⎯
System reserved
13
0D
⎯
⎯
3C8H
000FFFC8H
⎯
Undefined instruction exception
14
0E
⎯
⎯
3C4H
000FFFC4H
⎯
NMI request
15
0F
3C0H
000FFFC0H
⎯
External Interrupt 0
16
10
3BCH
000FFFBCH
0, 16
External Interrupt 1
17
11
3B8H
000FFFB8H
1, 17
External Interrupt 2
18
12
3B4H
000FFFB4H
2, 18
External Interrupt 3
19
13
3B0H
000FFFB0H
3, 19
External Interrupt 4
20
14
3ACH
000FFFACH
20
External Interrupt 5
21
15
3A8H
000FFFA8H
21
External Interrupt 6
22
16
3A4H
000FFFA4H
22
External Interrupt 7
23
17
3A0H
000FFFA0H
23
External Interrupt 8
24
18
39CH
000FFF9CH
⎯
External Interrupt 9
25
19
398H
000FFF98H
⎯
External Interrupt 10
26
1A
394H
000FFF94H
⎯
System reserved
27
1B
390H
000FFF90H
⎯
External Interrupt 12
28
1C
38CH
000FFF8CH
⎯
External Interrupt 13
29
1D
388H
000FFF88H
⎯
External Interrupt 14
30
1E
384H
000FFF84H
⎯
System reserved
31
1F
380H
000FFF80H
⎯
FH fixed
ICR00
440H
ICR01
441H
ICR02
442H
ICR03
443H
ICR04
444H
ICR05
445H
ICR06
446H
ICR07
447H
(Continued)
DS07-16612-2E
71
MB91460D Series
Interrupt
Interrupt
number
Decimal
Hexadecimal
Reload Timer 0
32
20
Reload Timer 1
33
21
Reload Timer 2
34
22
Reload Timer 3
35
23
Reload Timer 4
36
24
Reload Timer 5
37
25
Reload Timer 6
38
26
Reload Timer 7
39
27
Free Run Timer 0
40
28
Free Run Timer 1
41
29
Free Run Timer 2
42
2A
Free Run Timer 3
43
2B
Free Run Timer 4
44
2C
Free Run Timer 5
45
2D
Free Run Timer 6
46
2E
Free Run Timer 7
47
2F
CAN 0
48
30
CAN 1
49
31
CAN 2
50
32
System reserved
51
33
System reserved
52
34
System reserved
53
35
System reserved
54
36
System reserved
55
37
System reserved
56
38
System reserved
57
39
LIN-USART 2 RX
58
3A
LIN-USART 2 TX
59
3B
System reserved
60
3C
System reserved
61
3D
System reserved
62
3E
Delayed Interrupt
63
3F
Interrupt level *1
Setting
Register
Register
address
ICR08
448H
ICR09
449H
ICR10
44AH
ICR11
44BH
ICR12
44CH
ICR13
44DH
ICR14
44EH
ICR15
44FH
ICR16
450H
ICR17
451H
ICR18
452H
ICR19
453H
ICR20
454H
ICR21
455H
ICR22
456H
ICR23 *3
457H
Interrupt vector *2
DMA
Resource
number
Offset
Default Vector
address
37CH
000FFF7CH
4, 32
378H
000FFF78H
5, 33
374H
000FFF74H
34
370H
000FFF70H
35
36CH
000FFF6CH
36
368H
000FFF68H
37
364H
000FFF64H
38
360H
000FFF60H
39
35CH
000FFF5CH
40
358H
000FFF58H
41
354H
000FFF54H
42
350H
000FFF50H
43
34CH
000FFF4CH
44
348H
000FFF48H
45
344H
000FFF44H
46
340H
000FFF40H
47
33CH
000FFF3CH
⎯
338H
000FFF38H
⎯
334H
000FFF34H
⎯
330H
000FFF30H
⎯
32CH
000FFF2CH
⎯
328H
000FFF28H
⎯
324H
000FFF24H
6, 48
320H
000FFF20H
7, 49
31CH
000FFF1CH
8, 50
318H
000FFF18H
9, 51
314H
000FFF14H
52
310H
000FFF10H
53
30CH
000FFF0CH
54
308H
000FFF08H
55
304H
000FFF04H
⎯
300H
000FFF00H
⎯
(Continued)
72
DS07-16612-2E
MB91460D Series
Interrupt
Interrupt
number
Decimal
Hexadecimal
System reserved *4
64
40
System reserved *4
65
41
LIN-USART (FIFO) 4 RX
66
42
LIN-USART (FIFO) 4 TX
67
43
LIN-USART (FIFO) 5 RX
68
44
LIN-USART (FIFO) 5 TX
69
45
LIN-USART (FIFO) 6 RX
70
46
LIN-USART (FIFO) 6 TX
71
47
LIN-USART (FIFO) 7 RX
72
48
LIN-USART (FIFO) 7 TX
73
49
I2C 0 / I2C 2
74
4A
IC3
75
4B
System reserved
76
4C
System reserved
77
4D
System reserved
78
4E
System reserved
79
4F
System reserved
80
50
System reserved
81
51
System reserved
82
52
System reserved
83
53
System reserved
84
54
System reserved
85
55
System reserved
86
56
System reserved
87
57
System reserved
88
58
System reserved
89
59
System reserved
90
5A
System reserved
91
5B
Input Capture 0
92
5C
Input Capture 1
93
5D
Input Capture 2
94
5E
Input Capture 3
95
5F
2
Interrupt level *1
Setting
Register
Register
address
(ICR24)
(458H)
ICR25
459H
ICR26
45AH
ICR27
45BH
ICR28
45CH
ICR29
45DH
ICR30
45EH
ICR31
45FH
ICR32
460H
ICR33
461H
ICR34
462H
ICR35
463H
ICR36
464H
ICR37
465H
ICR38
466H
ICR39
467H
Interrupt vector *2
DMA
Resource
number
Offset
Default Vector
address
2FCH
000FFEFCH
⎯
2F8H
000FFEF8H
⎯
2F4H
000FFEF4H
10, 56
2F0H
000FFEF0H
11, 57
2ECH
000FFEECH
12, 58
2E8H
000FFEE8H
13, 59
2E4H
000FFEE4H
60
2E0H
000FFEE0H
61
2DCH
000FFEDCH
62
2D8H
000FFED8H
63
2D4H
000FFED4H
⎯
2D0H
000FFED0H
⎯
2CCH
000FFECCH
64
2C8H
000FFEC8H
65
2C4H
000FFEC4H
66
2C0H
000FFEC0H
67
2BCH
000FFEBCH
68
2B8H
000FFEB8H
69
2B4H
000FFEB4H
70
2B0H
000FFEB0H
71
2ACH
000FFEACH
72
2A8H
000FFEA8H
73
2A4H
000FFEA4H
74
2A0H
000FFEA0H
75
29CH
000FFE9CH
76
298H
000FFE98H
77
294H
000FFE94H
78
290H
000FFE90H
79
28CH
000FFE8CH
80
288H
000FFE88H
81
284H
000FFE84H
82
280H
000FFE80H
83
(Continued)
DS07-16612-2E
73
MB91460D Series
Interrupt
Interrupt
number
Decimal
Hexadecimal
Input Capture 4
96
60
Input Capture 5
97
61
Input Capture 6
98
62
Input Capture 7
99
63
Output Compare 0
100
64
Output Compare 1
101
65
Output Compare 2
102
66
Output Compare 3
103
67
System reserved
104
68
System reserved
105
69
System reserved
106
6A
System reserved
107
6B
Sound Generator
108
6C
Phase Frequency Modulator
109
6D
System reserved
110
6E
System reserved
111
6F
System reserved
112
70
System reserved
113
71
System reserved
114
72
System reserved
115
73
PPG4
116
74
PPG5
117
75
PPG6
118
76
PPG7
119
77
PPG8
120
78
PPG9
121
79
PPG10
122
7A
PPG11
123
7B
PPG12
124
7C
PPG13
125
7D
PPG14
126
7E
PPG15
127
7F
Interrupt level *1
Setting
Register
Register
address
ICR40
468H
ICR41
469H
ICR42
46AH
ICR43
46BH
ICR44
46CH
ICR45
46DH
ICR46
46EH
ICR47 *3
46FH
ICR48
470H
ICR49
471H
ICR50
472H
ICR51
473H
ICR52
474H
ICR53
475H
ICR54
476H
ICR55
477H
Interrupt vector *2
DMA
Resource
number
Offset
Default Vector
address
27CH
000FFE7CH
84
278H
000FFE78H
85
274H
000FFE74H
86
270H
000FFE70H
87
26CH
000FFE6CH
88
268H
000FFE68H
89
264H
000FFE64H
90
260H
000FFE60H
91
25CH
000FFE5CH
92
258H
000FFE58H
93
254H
000FFE54H
94
250H
000FFE50H
95
24CH
000FFE4CH
⎯
248H
000FFE48H
⎯
244H
000FFE44H
⎯
240H
000FFE40H
⎯
23CH
000FFE3CH
15, 96
238H
000FFE38H
97
234H
000FFE34H
98
230H
000FFE30H
99
22CH
000FFE2CH
100
228H
000FFE28H
101
224H
000FFE24H
102
220H
000FFE20H
103
21CH
000FFE1CH
104
218H
000FFE18H
105
214H
000FFE14H
106
210H
000FFE10H
107
20CH
000FFE0CH
108
208H
000FFE08H
109
204H
000FFE04H
110
200H
000FFE00H
111
(Continued)
74
DS07-16612-2E
MB91460D Series
(Continued)
Interrupt
Interrupt
number
Decimal
Hexadecimal
Up/Down Counter 0
128
80
System reserved
129
81
Up/Down Counter 2
130
82
Up/Down Counter 3
131
83
Real Time Clock
132
84
Calibration Unit
133
85
A/D Converter 0
134
86
System reserved
135
87
Alarm Comparator 0
136
88
System reserved
137
89
Low Voltage Detection
138
8A
SMC Comparator 0 to 5
139
8B
Timebase Overflow
140
8C
PLL Clock Gear
141
8D
DMA Controller
142
8E
Main/Sub OSC stability wait
143
8F
Security vector
144
Used by the INT instruction.
145
to
255
Interrupt level *1
Setting
Register
Register
address
ICR56
478H
ICR57
479H
ICR58
47AH
ICR59
47BH
ICR60
47CH
ICR61
47DH
ICR62
47EH
ICR63
47FH
90
⎯
91
to
FF
⎯
Interrupt vector *2
DMA
Resource
number
Offset
Default Vector
address
1FCH
000FFDFCH
⎯
1F8H
000FFDF8H
⎯
1F4H
000FFDF4H
⎯
1F0H
000FFDF0H
⎯
1ECH
000FFDECH
⎯
1E8H
000FFDE8H
⎯
1E4H
000FFDE4H
14, 112
1E0H
000FFDE0H
⎯
1DCH
000FFDDCH
⎯
1D8H
000FFDD8H
⎯
1D4H
000FFDD4H
⎯
1D0H
000FFDD0H
⎯
1CCH
000FFDCCH
⎯
1C8H
000FFDC8H
⎯
1C4H
000FFDC4H
⎯
1C0H
000FFDC0H
⎯
⎯
1BCH
000FFDBCH
⎯
⎯
1B8H to
000H
000FFDB8H
to
000FFC00H
⎯
*1 : The Interrupt Control Registers (ICRs) are located in the interrupt controller and set the interrupt level for each
interrupt request. An ICR is provided for each interrupt request.
*2 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the
table base register value (TBR) . The TBR specifies the top of the EIT vector table. The addresses listed in the
table are for the default TBR value (000FFC00H) . The TBR is initialized to this value by a reset. The TBR is set
to 000FFC00H after the internal boot ROM is executed.
*3 : ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03H : IOS[0])
*4 : Used by REALOS
*5 : Memory Protection Unit (MPU) support
DS07-16612-2E
75
MB91460D Series
■ RECOMMENDED SETTINGS
1. PLL and Clockgear settings
Please note that for MB91F467Dx the core base clock frequencies are valid in the 1.8V operation mode of the
Main regulator and Flash.
Recommended PLL divider and clockgear settings
PLL
Input (CLK)
[MHz]
Frequency Parameter
Clockgear Parameter
PLL
Core Base
Output (X)
Clock
[MHz]
[MHz]
DIVM
DIVN
DIVG
MULG
4
2
25
16
24
200
100
4
2
24
16
24
192
96
4
2
23
16
24
184
92
4
2
22
16
24
176
88
4
2
21
16
20
168
84
4
2
20
16
20
160
80
4
2
19
16
20
152
76
4
2
18
16
20
144
72
4
2
17
16
16
136
68
4
2
16
16
16
128
64
4
2
15
16
16
120
60
4
2
14
16
16
112
56
4
2
13
16
12
104
52
4
2
12
16
12
96
48
4
2
11
16
12
88
44
4
4
10
16
24
160
40
4
4
9
16
24
144
36
4
4
8
16
24
128
32
4
4
7
16
24
112
28
4
6
6
16
24
144
24
4
8
5
16
28
160
20
4
10
4
16
32
160
16
4
12
3
16
32
144
12
Remarks
MULG
*1
*1 This setting is not possible at MB91F467Dx
76
DS07-16612-2E
MB91460D Series
2. Clock Modulator settings
The following table shows all possible settings for the Clock Modulator in a base clock frequency range from
32MHz up to 88MHz.
The Flash access time settings need to be adjusted according to Fmax while the PLL and clockgear settings
should be set according to base clock frequency.
Clock Modulator settings, frequency range and supported supply voltage
Modulation Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
Remarks
1
3
026F
88
79.5
98.5
*1
1
3
026F
84
76.1
93.8
1
3
026F
80
72.6
89.1
1
5
02AE
80
68.7
95.8
2
3
046E
80
68.7
95.8
1
3
026F
76
69.1
84.5
1
5
02AE
76
65.3
90.8
1
7
02ED
76
62
98.1
2
3
046E
76
65.3
90.8
3
3
066D
76
62
98.1
1
3
026F
72
65.5
79.9
1
5
02AE
72
62
85.8
1
7
02ED
72
58.8
92.7
2
3
046E
72
62
85.8
3
3
066D
72
58.8
92.7
1
3
026F
68
62
75.3
1
5
02AE
68
58.7
80.9
1
7
02ED
68
55.7
87.3
1
9
032C
68
53
95
2
3
046E
68
58.7
80.9
2
5
04AC
68
53
95
3
3
066D
68
55.7
87.3
4
3
086C
68
53
95
1
3
026F
64
58.5
70.7
1
5
02AE
64
55.3
75.9
1
7
02ED
64
52.5
82
1
9
032C
64
49.9
89.1
1
11
036B
64
47.6
97.6
2
3
046E
64
55.3
75.9
2
5
04AC
64
49.9
89.1
DS07-16612-2E
*1
*1
*1
77
MB91460D Series
(Continued)
(Continued)
Modulation Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
3
3
066D
64
52.5
82
4
3
086C
64
49.9
89.1
5
3
0A6B
64
47.6
97.6
1
3
026F
60
54.9
66.1
1
5
02AE
60
51.9
71
1
7
02ED
60
49.3
76.7
1
9
032C
60
46.9
83.3
1
11
036B
60
44.7
91.3
2
3
046E
60
51.9
71
2
5
04AC
60
46.9
83.3
3
3
066D
60
49.3
76.7
4
3
086C
60
46.9
83.3
5
3
0A6B
60
44.7
91.3
1
3
026F
56
51.4
61.6
1
5
02AE
56
48.6
66.1
1
7
02ED
56
46.1
71.4
1
9
032C
56
43.8
77.6
1
11
036B
56
41.8
84.9
1
13
03AA
56
39.9
93.8
2
3
046E
56
48.6
66.1
2
5
04AC
56
43.8
77.6
2
7
04EA
56
39.9
93.8
3
3
066D
56
46.1
71.4
3
5
06AA
56
39.9
93.8
4
3
086C
56
43.8
77.6
5
3
0A6B
56
41.8
84.9
6
3
0C6A
56
39.9
93.8
1
3
026F
52
47.8
57
1
5
02AE
52
45.2
61.2
1
7
02ED
52
42.9
66.1
1
9
032C
52
40.8
71.8
1
11
036B
52
38.8
78.6
1
13
03AA
52
37.1
86.8
1
15
03E9
52
35.5
96.9
2
3
046E
52
45.2
61.2
Remarks
*1
(Continued)
78
DS07-16612-2E
MB91460D Series
(Continued)
Modulation Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
2
5
04AC
52
40.8
71.8
2
7
04EA
52
37.1
86.8
3
3
066D
52
42.9
66.1
3
5
06AA
52
37.1
86.8
4
3
086C
52
40.8
71.8
5
3
0A6B
52
38.8
78.6
6
3
0C6A
52
37.1
86.8
7
3
0E69
52
35.5
96.9
1
3
026F
48
44.2
52.5
1
5
02AE
48
41.8
56.4
1
7
02ED
48
39.6
60.9
1
9
032C
48
37.7
66.1
1
11
036B
48
35.9
72.3
1
13
03AA
48
34.3
79.9
1
15
03E9
48
32.8
89.1
2
3
046E
48
41.8
56.4
2
5
04AC
48
37.7
66.1
2
7
04EA
48
34.3
79.9
3
3
066D
48
39.6
60.9
3
5
06AA
48
34.3
79.9
4
3
086C
48
37.7
66.1
5
3
0A6B
48
35.9
72.3
6
3
0C6A
48
34.3
79.9
7
3
0E69
48
32.8
89.1
1
3
026F
44
40.6
48.1
1
5
02AE
44
38.4
51.6
1
7
02ED
44
36.4
55.7
1
9
032C
44
34.6
60.4
1
11
036B
44
33
66.1
1
13
03AA
44
31.5
73
1
15
03E9
44
30.1
81.4
2
3
046E
44
38.4
51.6
2
5
04AC
44
34.6
60.4
2
7
04EA
44
31.5
73
2
9
0528
44
28.9
92.1
Remarks
*1
(Continued)
DS07-16612-2E
79
MB91460D Series
(Continued)
Modulation Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
3
3
066D
44
36.4
55.7
3
5
06AA
44
31.5
73
4
3
086C
44
34.6
60.4
4
5
08A8
44
28.9
92.1
5
3
0A6B
44
33
66.1
6
3
0C6A
44
31.5
73
7
3
0E69
44
30.1
81.4
8
3
1068
44
28.9
92.1
1
3
026F
40
37
43.6
1
5
02AE
40
34.9
46.8
1
7
02ED
40
33.1
50.5
1
9
032C
40
31.5
54.8
1
11
036B
40
30
59.9
1
13
03AA
40
28.7
66.1
1
15
03E9
40
27.4
73.7
2
3
046E
40
34.9
46.8
2
5
04AC
40
31.5
54.8
2
7
04EA
40
28.7
66.1
2
9
0528
40
26.3
83.3
3
3
066D
40
33.1
50.5
3
5
06AA
40
28.7
66.1
3
7
06E7
40
25.3
95.8
4
3
086C
40
31.5
54.8
4
5
08A8
40
26.3
83.3
5
3
0A6B
40
30
59.9
6
3
0C6A
40
28.7
66.1
7
3
0E69
40
27.4
73.7
8
3
1068
40
26.3
83.3
9
3
1267
40
25.3
95.8
1
3
026F
36
33.3
39.2
1
5
02AE
36
31.5
42
1
7
02ED
36
29.9
45.3
1
9
032C
36
28.4
49.2
1
11
036B
36
27.1
53.8
1
13
03AA
36
25.8
59.3
Remarks
(Continued)
80
DS07-16612-2E
MB91460D Series
(Continued)
Modulation Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
1
15
03E9
36
24.7
66.1
2
3
046E
36
31.5
42
2
5
04AC
36
28.4
49.2
2
7
04EA
36
25.8
59.3
2
9
0528
36
23.7
74.7
3
3
066D
36
29.9
45.3
3
5
06AA
36
25.8
59.3
3
7
06E7
36
22.8
85.8
4
3
086C
36
28.4
49.2
4
5
08A8
36
23.7
74.7
5
3
0A6B
36
27.1
53.8
6
3
0C6A
36
25.8
59.3
7
3
0E69
36
24.7
66.1
8
3
1068
36
23.7
74.7
9
3
1267
36
22.8
85.8
1
3
026F
32
29.7
34.7
1
5
02AE
32
28
37.3
1
7
02ED
32
26.6
40.2
1
9
032C
32
25.3
43.6
1
11
036B
32
24.1
47.7
1
13
03AA
32
23
52.5
1
15
03E9
32
22
58.6
2
3
046E
32
28
37.3
2
5
04AC
32
25.3
43.6
2
7
04EA
32
23
52.5
2
9
0528
32
21.1
66.1
2
11
0566
32
19.5
89.1
3
3
066D
32
26.6
40.2
3
5
06AA
32
23
52.5
3
7
06E7
32
20.3
75.9
4
3
086C
32
25.3
43.6
4
5
08A8
32
21.1
66.1
5
3
0A6B
32
24.1
47.7
5
5
0AA6
32
19.5
89.1
6
3
0C6A
32
23
52.5
Remarks
(Continued)
DS07-16612-2E
81
MB91460D Series
(Continued)
Modulation Degree
(k)
Random No
(N)
CMPR
[hex]
Baseclk
[MHz]
Fmin
[MHz]
Fmax
[MHz]
7
3
0E69
32
22
58.6
8
3
1068
32
21.1
66.1
9
3
1267
32
20.3
75.9
10
3
1466
32
19.5
89.1
Remarks
*1 These settings are not possible at MB91F467Dx
82
DS07-16612-2E
MB91460D Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute maximum ratings
Parameter
Symbol
Rating
Unit
Remarks
Min
Max
⎯
⎯
50
V/ms
Power supply voltage 1*
VDD5R
− 0.3
+ 6.0
V
Power supply voltage 2*1
VDD5
− 0.3
+ 6.0
V
Power supply voltage 3*1
HVDD5
− 0.3
+ 6.0
V
Power supply voltage 4*1
VDD35
− 0.3
+ 6.0
V
VDD5-0.3
VDD5+0.3
V
SMC mode
VSS5-0.3
VDD5+0.3
V
General purpose port
mode
Power supply slew rate
1
HVDD5
Relationship of the supply voltages
VDD5-0.3
VDD5+0.3
V
At least one pin of the
Ports 25 to 29 (SMC,
ANn) is used as digital
input or output.
VSS5-0.3
VDD5+0.3
V
All pins of the Ports 25 to
29 (SMC, ANn) follow the
condition of VIA
AVCC5
Analog power supply voltage*1
AVCC5
− 0.3
+ 6.0
V
*2
Analog reference
power supply voltage*1
AVRH5
− 0.3
+ 6.0
V
*2
Input voltage 1*1
VI1
Vss5 − 0.3
VDD5 + 0.3
V
Input voltage 2*1
VI2
Vss5 − 0.3
VDD35 + 0.3
V
External bus
VI3
HVss5 − 0.3
HVDD5 + 0.3
V
Stepper motor controller
Input voltage 3*
1
VIA
AVss5 − 0.3
AVcc5 + 0.3
V
Output voltage 1*
1
VO1
Vss5 − 0.3
VDD5 + 0.3
V
Output voltage 2*
1
VO2
Vss5 − 0.3
VDD35 + 0.3
V
External bus
Output voltage 3*
1
VO3
HVss5 − 0.3
HVDD5 + 0.3
V
Stepper motor controller
ICLAMP
− 4.0
+ 4.0
mA
*3
Σ |ICLAMP|
⎯
20
mA
*3
⎯
10
mA
⎯
40
mA
⎯
8
mA
⎯
30
mA
⎯
100
mA
⎯
360
mA
⎯
50
mA
⎯
230
mA
Analog pin input voltage*
1
Maximum clamp current
Total maximum clamp current
“L” level maximum
output current*4
IOL
“L” level average
output current*5
IOLAV
“L” level total maximum
output current
ΣIOL
“L” level total average
output current*6
DS07-16612-2E
ΣIOLAV
Stepper motor controller
Stepper motor controller
Stepper motor controller
Stepper motor controller
83
MB91460D Series
Parameter
“H” level maximum
output current*4
Symbol
IOH
“H” level average
output current*5
IOHAV
“H” level total maximum
output current
ΣIOH
“H” level total average output
current*6
ΣIOHAV
Rating
Unit
Max
⎯
− 10
mA
⎯
− 40
mA
⎯
−4
mA
⎯
− 30
mA
⎯
− 100
mA
⎯
− 360
mA
⎯
− 25
mA
⎯
− 230
mA
Stepper motor controller
at TA = 105 °C
Power consumption
PD
⎯
1000
mW
Operating temperature
TA
− 40
+ 105
°C
Tstg
− 55
+ 150
°C
Storage temperature
Remarks
Min
Stepper motor controller
Stepper motor controller
Stepper motor controller
*1 : The parameter is based on VSS5 = HVSS5 = AVSS5 = 0.0 V.
*2 : AVCC5 and AVRH5 must not exceed VDD5 + 0.3 V.
*3 :
84
• Use within recommended operating conditions.
• Use with DC voltage (current).
• +B signals are input signals that exceed the VDD5 voltage. +B signals should always be applied by
connecting a limiting resistor between the +B signal and the microcontroller.
• The value of the limiting resistor should be set so that the current input to the microcontroller pin does not
exceed the rated value at any time, either instantaneously or for an extended period, when the +B signal
is input.
• Note that when the microcontroller drive current is low, such as in the low power consumption modes, the
+B input potential can increase the potential at the power supply pin via a protective diode, possibly affecting
other devices.
• Note that if the +B signal is input when the microcontroller is off (not fixed at 0 V), power is supplied through
the +B input pin; therefore, the microcontroller may partially operate.
• Note that if the +B signal is input at power-on, since the power is supplied through the pin, the power-on reset
may not function in the power supply voltage.
DS07-16612-2E
MB91460D Series
• Do not leave +B input pins open.
• Example of recommended circuit :
• Input/output equivalent circuit
Protective diode
VCC
Limiting
resistor
P-ch
+B input (0 V to 16 V)
N-ch
R
*4 : Maximum output current is defined as the value of the peak current flowing through any one of the corresponding
pins.
*5 : Average output current is defined as the value of the average current flowing through any one of the
corresponding pins for a 100 ms period.
*6 : Total average output current is defined as the value of the average current flowing through all of the
corresponding pins for a 100 ms period.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
DS07-16612-2E
85
MB91460D Series
2. Recommended operating conditions
(VSS5 = AVSS5 = 0.0 V)
Parameter
Symbol
Max
VDD5
3.0
⎯
5.5
V
VDD5R
3.0
⎯
5.5
V
Internal regulator
VDD35
3.0
⎯
5.5
V
External bus
4.5
⎯
5.5
V
Stepper motor controller
3.0
⎯
5.5
V
Stepper motor controller
(when all pins are used as general-purpose ports)
AVCC5
3.0
⎯
5.5
V
A/D converter
CS
⎯
4.7
⎯
μF
Use a X7R ceramic capacitor or
a capacitor that has similar frequency characteristics.
⎯
⎯
50
V/ms
− 40
⎯
+ 105
°C
Power supply slew rate
TA
Stepper motor control
slew rate
40
Main Oscillation
stabilisation time
RC Oscillator
ns
10
Cload = 0 pF
ms
Look-up time PLL
(4 MHz ->16 ...100MHz)
ESD Protection
(Human body model)
Remarks
Typ
HVDD5
Operating temperature
Unit
Min
Power supply voltage
Smoothing capacitor at
VCC18C pin
Value
0.6
ms
Vsurge
2
fRC100kHz
50
100
200
kHz
fRC2MHz
1
2
4
MHz
kV
Rdischarge = 1.5kΩ
Cdischarge = 100pF
VDDCORE ≥ 1.65V
WARNING: The recommended operating conditions are required in order to ensure the normal operation of
the semiconductor device. All of the device's electrical characteristics are warranted when the
device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges.
Operation outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented
on the data sheet. Users considering application outside the listed conditions are advised to contact
their representatives beforehand.
86
DS07-16612-2E
MB91460D Series
VCC18C
VSS5
AVSS5
CS
DS07-16612-2E
87
MB91460D Series
3. DC characteristics
Note: In the following tables, “VDD” means VDD35 for pins of ext. bus or HVDD5 for SMC pins or VDD5 for other pins.
In the following tables, “VSS” means Hvss5 for ground Pins of the stepper motor and VSS5 for the other pins.
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter Symbol
Pin name
Min
Unit
Remarks
Typ
Max
⎯
VDD + 0.3
V
CMOS
hysteresis
input
⎯
VDD + 0.3
V
4.5 V ≤ VDD ≤ 5.5 V
⎯
VDD + 0.3
V
3 V ≤ VDD < 4.5 V
Port inputs if CMOS
Hysteresis 0.8/0.2 0.8 × VDD
input is selected
⎯
Port inputs if CMOS 0.7 × VDD
Hysteresis 0.7/0.3
0.74 × VDD
input is selected
⎯
AUTOMOTIVE
Hysteresis input is
selected
0.8 × VDD
⎯
VDD + 0.3
V
⎯
Port inputs if TTL
input is selected
2.0
⎯
VDD + 0.3
V
VIHR
INITX
⎯
0.8 × VDD
⎯
VDD + 0.3
V
INITX input pin
(CMOS
Hysteresis)
VIHM
MD_2 to
MD_0
⎯
VDD − 0.3
⎯
VDD + 0.3
V
Mode input pins
VIHX0S
X0, X0A
⎯
2.5
⎯
VDD + 0.3
V
External clock in
“Oscillation mode”
VIHX0F
X0
⎯
0.8 × VDD
⎯
VDD + 0.3
V
External clock in
“Fast Clock Input
mode”
⎯
Port inputs if CMOS
Hysteresis 0.8/0.2
input is selected
VSS − 0.3
⎯
0.2 × VDD
V
⎯
Port inputs if CMOS
Hysteresis 0.7/0.3
input is selected
VSS − 0.3
⎯
0.3 × VDD
V
VSS − 0.3
⎯
0.5 × VDD
V
4.5 V ≤ VDD ≤ 5.5 V
⎯
Port inputs if
AUTOMOTIVE
Hysteresis input is
selected
VSS − 0.3
⎯
0.46 × VDD
V
3 V ≤ VDD < 4.5 V
⎯
Port inputs if TTL
input is selected
VSS − 0.3
⎯
0.8
V
VIL
Input “L”
voltage
88
Value
⎯
VIH
Input “H”
voltage
Condition
VILR
INITX
⎯
VSS − 0.3
⎯
0.2 × VDD
V
INITX input pin
(CMOS
Hysteresis)
VILM
MD_2 to
MD_0
⎯
VSS − 0.3
⎯
VSS + 0.3
V
Mode input pins
VILXDS
X0, X0A
⎯
VSS − 0.3
⎯
0.5
V
External clock in
“Oscillation mode”
DS07-16612-2E
MB91460D Series
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter Symbol
Input “L”
voltage
Output “H”
voltage
Pin
name
Condition
X0
⎯
Value
Unit
Remarks
0.2 × VDD
V
External clock in
“Fast Clock Input
mode”
⎯
⎯
V
Driving strength
set to 2 mA
VDD − 0.5
⎯
⎯
V
Driving strength
set to 5 mA
VDD − 0.5
⎯
⎯
V
See note *1
V
Driving strength
set to 30mA
Min
Typ
Max
VSS − 0.3
⎯
VOH2
4.5V ≤ VDD ≤ 5.5V,
Normal IOH = − 2mA
outputs 3.0V ≤ VDD ≤ 4.5V,
IOH = − 1.6mA
VDD − 0.5
VOH5
4.5V ≤ VDD ≤ 5.5V,
I
Normal OH = − 5mA
outputs 3.0V ≤ VDD ≤ 4.5V,
IOH = − 3mA
VOH3
I2C
3.0V ≤ VDD ≤ 5.5V,
outputs IOH = − 3mA
VILXDF
VOH30
4.5V ≤ VDD ≤ 5.5V,
TA = -40 °C,
High IOH = -40mA
current 4.5V ≤ VDD ≤ 5.5V,
outputs IOH = -30mA
VDD − 0.5
3.0V ≤ VDD ≤ 4.5V,
⎯
⎯
0.4
V
Driving strength
set to 2 mA
VOL5
4.5V ≤ VDD ≤ 5.5V,
Normal IOH = + 5mA
outputs 3.0V ≤ VDD ≤ 4.5V,
IOH = + 3mA
⎯
⎯
0.4
V
Driving strength
set to 5 mA
VOL3
I2C
3.0V ≤ VDD ≤ 5.5V,
outputs IOH = + 3mA
⎯
⎯
0.4
V
See note *2
0.5
V
VOL2
Output “L“
voltage
IOH = -20mA
4.5V ≤ VDD ≤ 5.5V,
Normal IOH = + 2mA
outputs 3.0V ≤ VDD ≤ 4.5V,
IOH = + 1.6mA
4.5V ≤ VDD ≤ 5.5V,
TA = -40 °C,
IOH = +40mA
VOL30
High
current 4.5V ≤ VDD ≤ 5.5V,
outputs IOH = +30mA
Driving strength
set to 30mA
3.0V ≤ VDD ≤ 4.5V,
IOH = +20mA
DS07-16612-2E
89
MB91460D Series
Parameter Symbol
Pin
name
Input leakage current
3.0V ≤ VDD ≤ 5.5V
VSS5 < VI < VDD
Pnn_m TA=25 °C
*3
3.0V ≤ VDD ≤ 5.5V
VSS5 < VI < VDD
TA=105 °C
IIL
Analog input leakage current
IAIN
Pull-up
resistance
RUP
Pnn_m
*5
INITX
Pull-down
resistance
RDOWN
Pnn_m
*6
Input
capacitance
Power
supply
current
ANn *
4
Min
Typ
Max
−1
⎯
+1
Unit
Remarks
μA
⎯
+3
3.0V ≤ VDD ≤ 5.5V
TA=25 °C
−1
⎯
+1
μA
3.0V ≤ VDD ≤ 5.5V
TA=105 °C
−3
⎯
+3
μA
3.0V ≤ VDD ≤ 3.6V
40
100
160
4.5V ≤ VDD ≤ 5.5V
25
50
100
3.0V ≤ VDD ≤ 3.6V
40
100
180
4.5V ≤ VDD ≤ 5.5V
25
50
100
-
5
15
pF
⎯
120
150
mA
Code fetch from
Flash
TA = + 25 °C
⎯
30
150
μA
At stop mode *7
TA = + 105 °C
⎯
400
2000
μA
TA = + 25 °C
⎯
100
500
μA
⎯
500
2400
μA
TA = + 25 °C
⎯
50
250
μA
TA = + 105 °C
⎯
450
2200
μA
CIN
ICC
MB91F467Dx:
CLKB:
96 MHz
VDD5R CLKP:
48 MHz
CLKT:
48 MHz
CLKCAN: 48 MHz
ICCH
Value
−3
All except
VDD5,
VDD5R,
f = 1 MHz
VSS5,
AVCC5,
AVSS,
AVRH5
VDD5R TA = + 105 °C
MB91F467Dx
kΩ
kΩ
*8
RTC :
4 MHz mode *7
*8
RTC :
100 kHz mode *7
*8
ILVE
VDD5
⎯
⎯
70
150
μA
External low voltage detection
ILVI
VDD5R
⎯
⎯
50
100
μA
Internal low voltage detection
⎯
⎯
250
500
μA
Main clock
(4 MHz)
⎯
⎯
20
40
μA
Sub clock
(32 kHz)
IOSC
90
Condition
VDD5
DS07-16612-2E
MB91460D Series
Parameter Symbol
ICC
Power
supply
current
ICCH
MB91F465DA
6.
7.
8.
Condition
Unit
Remarks
140
mA
Code fetch from
Flash
30
150
μA
-
300
2000
μA
TA = + 25 °C
-
100
500
μA
TA = + 105 °C
-
500
2400
μA
TA = + 25 °C
-
50
250
μA
TA = + 105 °C
-
400
2200
μA
RTC :
100 kHz mode *7
Min
Typ
Max
-
110
TA = + 25 °C
-
TA = + 105 °C
MB91F465DA:
CLKB:
100 MHz
VDD5R CLKP:
50 MHz
CLKT:
50 MHz
CLKCAN: 50 MHz
VDD5R
Value
At stop mode *7
RTC :
4 MHz mode *7
ILVE
VDD5
-
-
70
150
μA
External low voltage detection
ILVI
VDD5R
-
-
50
100
μA
Internal low voltage detection
-
-
250
500
μA
Main clock
(4 MHz)
-
-
20
40
μA
Sub clock
(32 kHz)
IOSC
1.
2.
3.
4.
5.
Pin
name
VDD5
I2C Spec on MB91F467Dx only guaranteed for 4.5 V < VDD5 < 5.5 V.
I2C Spec on MB91F467Dx only guaranteed for 4.5 V < VDD5 < 5.5 V.
Pnn_m includes all GPIO pins. Analog (AN) channels and PullUp/PullDown are disabled.
ANn includes all pins where AN channels are enabled.
Pnn_m includes all GPIO pins. The pull up resistors must be enabled by PPER/PPCR setting and
the pins must be in input direction.
Pnn_m includes all GPIO pins. The pull down resistors must be enabled by PPER/PPCR setting and
the pins must be in input direction.
Main regulator OFF, sub regulator set to 1.2V, Low voltage detection disabled.
On MB91F467Dx, the I2C pin consumes typical 200 μA and maximal 400 μA when “L” level is output,
even if there is no load condition. When entering the standby mode while I2C outputs “L”, the abovementioned current is added to ICCH. The I2C pins are recommended to use for port input or external
interrupt in standby mode.
DS07-16612-2E
91
MB91460D Series
4. A/D converter characteristics
(VDD5 = AVCC5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol Pin name
Value
Min
Typ
Max
Unit
Remarks
Resolution
⎯
⎯
⎯
⎯
10
bit
Total error
⎯
⎯
−3
⎯
+3
LSB
Nonlinearity error
⎯
⎯
− 2.5
⎯
+ 2.5
LSB
Differential nonlinearity
error
⎯
⎯
− 1.9
⎯
+ 1.9
LSB
Zero reading voltage
VOT
ANn
AVRL−
1.5 LSB
AVRL +
0.5 LSB
AVRL +
2.5 LSB
V
Full scale reading voltage
VFST
ANn
AVRH−
3.5 LSB
AVRH−
1.5 LSB
AVRH +
0.5 LSB
V
0.6
⎯
16,500
μs
4.5 V ≤ AVCC5 ≤
5.5 V
2.0
⎯
⎯
μs
3.0 V ≤ AVCC5 ≤
4.5 V
0.4
⎯
⎯
μs
4.5 V ≤ AVCC5 ≤
5.5 V,
REXT < 2 kΩ
1.0
⎯
⎯
μs
3.0 V ≤ AVCC5 ≤
4.5 V,
REXT < 1 kΩ
1.0
⎯
⎯
μs
4.5 V ≤ AVCC5 ≤
5.5 V
3.0
⎯
⎯
μs
3.0 V ≤ AVCC5 ≤
4.5 V
⎯
⎯
11
pF
⎯
⎯
2.6
kΩ
4.5 V ≤ AVCC5 ≤
5.5 V
⎯
⎯
12.1
kΩ
3.0 V ≤ AVCC5 ≤
4.5 V
−1
⎯
+1
μA
TA = + 25 °C
−3
⎯
+3
μA
TA = + 105 °C
Compare time
Sampling time
Conversion time
Input capacitance
Input resistance
Tcomp
Tsamp
Tconv
CIN
RIN
⎯
⎯
⎯
ANn
ANn
Analog input leakage
current
IAIN
ANn
Analog input voltage range
VAIN
ANn
AVRL
⎯
AVRH
V
Offset between input channels
⎯
ANn
⎯
⎯
4
LSB
(Continued)
Note : The accuracy gets worse as AVRH - AVRL becomes smaller
92
DS07-16612-2E
MB91460D Series
(Continued)
Parameter
Symbol Pin name
Value
Min
Typ
Max
Unit
Remarks
AVRH
AVRH5
0.75 ×
AVCC5
⎯
AVCC5
V
AVRL
AVSS5
AVSS5
⎯
AVCC5 ×
0.25
V
IA
AVCC5
⎯
2.5
5
mA
A/D Converter
active
IAH
AVCC5
⎯
⎯
5
μA
A/D Converter
not operated *1
IR
AVRH5
⎯
0.7
1
mA
A/D Converter
active
IRH
AVRH5
⎯
⎯
5
μA
A/D Converter
not operated *2
Reference voltage range
Power supply current
Reference voltage current
*1 : Supply current at AVCC5, if A/D converter and ALARM comparator are not operating,
(VDD5 = AVCC5 = AVRH = 5.0 V)
*2 : Input current at AVRH5, if A/D converter is not operating, (VDD5 = AVCC5 = AVRH = 5.0 V)
Sampling Time Calculation
Tsamp = ( 2.6 kOhm + REXT) × 11pF × 7; for 4.5V ≤ AVCC5 ≤ 5.5V
Tsamp = (12.1 kOhm + REXT) × 11pF × 7; for 3.0V ≤ AVCC5 ≤ 4.5V
Conversion Time Calculation
Tconv = Tsamp + Tcomp
Definition of A/D converter terms
• Resolution
Analog variation that is recognizable by the A/D converter.
• Nonlinearity error
Deviation between actual conversion characteristics and a straight line connecting the zero transition point
(00 0000 0000B ↔ 00 0000 0001B) and the full scale transition point (11 1111 1110B ↔ 11 1111 1111B).
• Differential nonlinearity error
Deviation of the input voltage from the ideal value that is required to change the output code by 1 LSB.
• Total error
This error indicates the difference between actual and theoretical values, including the zero transition error,
full scale transition error, and nonlinearity error.
DS07-16612-2E
93
MB91460D Series
Total error
3FFH
1.5 LSB’
3FEH
Actual conversion
characteristics
Digital output
3FDH
{1 LSB’ (N - 1) + 0.5 LSB’}
004H
VNT
003H
(measurement value)
Actual conversion
characteristics
002H
Ideal characteristics
001H
0.5 LSB'
AVSS5
AVRH
Analog input
1LSB' (ideal value) = AVRH − AVSS5 [V]
1024
Total error of digital output N = VNT − {1 LSB' × (N − 1) + 0.5 LSB'}
1 LSB'
N : A/D converter digital output value
VOT' (ideal value) = AVSS5 + 0.5 LSB' [V]
VFST' (ideal value) = AVRH − 1.5 LSB' [V]
VNT : Voltage at which the digital output changes from (N + 1) H to NH
(Continued)
94
DS07-16612-2E
MB91460D Series
(Continued)
Nonlinearity error
3FFH
Differential nonlinearity error
Actual conversion characteristics
Actual conversion characteristics
(N+1)H
3FEH
{1 LSB (N - 1) + VOT}
VFST
004H
VNT
(measurement value)
003H
002H
Ideal
characteristics
(measurement value)
Digital output
Digital output
3FDH
NH
(N-1)H
VFST
Actual conversion
characteristics
VNT
(measurement value)
Ideal characteristics
(N-2)H
001H
Actual conversion
characteristics
VTO (measurement value)
AVSS5
AVSS5
AVRH
Analog input
Nonlinearity error of digital output N =
VFST − VOT
1022
AVRH
Analog input
VNT − {1LSB × (N − 1) + VOT} [LSB]
1LSB
Differential nonlinearity error of digital output N =
1LSB =
(measurement value)
V (N + 1) T − VNT
1LSB
− 1 [LSB]
[V]
N
: A/D converter digital output value
VOT : Voltage at which the digital output changes from 000H to 001H.
VFST : Voltage at which the digital output changes from 3FEH to 3FFH.
DS07-16612-2E
95
MB91460D Series
5. Alarm comparator characteristics
Parameter
Symbol
Pin name
Min
⎯
IA5ALMF
Power supply
current
Value
Typ
25
Max
40
Unit
Remarks
μA
Alarm comparator enabled in
fast mode (per
channel) *1
AVCC5
⎯
IA5ALMS
7
10
μA
Alarm comparator enabled in
normal mode
(per channel)
*1
IA5ALMH
⎯
⎯
5
μA
Alarm comparator disabled
−1
⎯
+1
μA
TA=25 °C
−3
⎯
+3
μA
TA=105 °C
ALARM pin input current
IALIN
ALARM pin input voltage
range
VALIN
0
⎯
AVCC5
V
Alarm upper
limit
voltage
VIAH
AVCC5 × 0.78
− 3%
AVCC5 × 0.78
AVCC5 × 0.78
+ 3%
V
Alarm lower
limit
voltage
VIAL
AVCC5 × 0.36
− 5%
AVCC5 × 0.36
AVCC5 × 0.36
+ 5%
V
VIAHYS
50
⎯
250
mV
RIN
5
⎯
⎯
MΩ
tCOMPF
⎯
0.1
0.2
μs
Alarm hysteresis
voltage
Alarm input
resistance
ALARM_n
Comparison
time
tCOMPS
⎯
1
2
μs
Alarm comparator enabled in
fast mode *1
Alarm comparator enabled in
normal mode
*1
Note: *1 :
96
The fast Alarm Comparator mode is enabled by setting ACSR.MD=1
Setting ACSR.MD=0 sets the normal mode.
DS07-16612-2E
MB91460D Series
6. FLASH memory program/erase characteristics
6.1.
MB91F465DA
(TA = 25oC, Vcc = 5.0V)
Parameter
Value
Unit
Remarks
3.6
s
Erasure programming time not
included
n*0.9
n*3.6
s
n is the number of Flash sector
of the device
23
370
μs
System overhead time not included
Min
Typ
Max
Sector erase time
-
0.9
Chip erase time
-
Word (16-bit width) programming time
-
Programme/Erase cycle 10 000
cycle
Flash data retention time
year
20
*1
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius
equation to convert high temperature measurements into normalized value at 85oC)
6.2.
MB91F467Dx
(TA = 25oC, Vcc = 5.0V)
Parameter
Value
Unit
Remarks
2.0
s
Erasure programming time not
included
n*0.5
n*2.0
s
n is the number of Flash sector
of the device
6
100
μs
System overhead time not included
Min
Typ
Max
Sector erase time
-
0.5
Chip erase time
-
Word (16 or 32-bit width)
programming time
-
Programme/Erase cycle 10 000
cycle
Flash data retention time
year
20
*1
*1: This value was converted from the results of evaluating the reliability of the technology (using Arrhenius
equation to convert high temperature measurements into normalized value at 85oC)
DS07-16612-2E
97
MB91460D Series
7. AC characteristics
7.1.
Clock timing
(VDD5 = 3.0 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Clock frequency
Symbol Pin name
fC
Value
Unit
Condition
16
MHz
Opposite phase external
supply or crystal
100
kHz
Min
Typ
Max
X0
X1
3.5
4
X0A
X1A
32
32.768
• Clock timing condition
tC
X0,
X1,
X0A,
X1A
0.8 VCC
0.2 VCC
PWH
98
PWL
DS07-16612-2E
MB91460D Series
7.2.
Reset input ratings
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
INITX input time
(at power-on)
INITX input time
(other than the above)
Symbol
tINTL
Pin name
Condition
Value
Unit
Min
Max
8
⎯
ms
20
⎯
μs
⎯
INITX
tINTL
INITX
DS07-16612-2E
0.2 VCC
99
MB91460D Series
7.3.
LIN-USART Timings at VDD5 = 3.0 to 5.5 V
• Conditions during AC measurements
• All AC tests were measured under the following conditions:
• - IOdrive = 5 mA
• - VDD5 = 3.0 V to 5.5 V, Iload = 3 mA
• - VSS5 = 0 V
• - Ta = -40 °C to +105 °C
• - Cl = 50 pF (load capacity value of pins when testing)
• - VOL = 0.2 x VDD5
• - VOH = 0.8 x VDD5
• - EPILR = 0, PILR = 1 (Automotive Level = worst case)
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
Serial clock
cycle time
tSCYCI
SCKn
SCK ↓ → SOT
delay time
tSLOVI
SCKn
SOTn
SOT → SCK ↓
delay time
tOVSHI
SCKn
SOTn
Valid SIN →
SCK ↑ setup time
tIVSHI
SCKn
SINn
SCK ↑ → valid
SIN hold time
tSHIXI
Serial clock
“H” pulse width
Condition
VDD5 = 3.0 V to 4.5 V VDD5 = 4.5 V to 5.5 V
Unit
Min
Max
Min
Max
4 tCLKP
⎯
4 tCLKP
⎯
ns
− 30
30
− 20
20
ns
m×
tCLKP − 30*
⎯
m×
tCLKP − 20*
⎯
ns
tCLKP + 55
⎯
tCLKP + 45
⎯
ns
SCKn
SINn
0
⎯
0
⎯
ns
tSHSLE
SCKn
tCLKP + 10
⎯
tCLKP + 10
⎯
ns
Serial clock
“L” pulse width
tSLSHE
SCKn
tCLKP + 10
⎯
tCLKP + 10
⎯
ns
SCK ↓ → SOT
delay time
tSLOVE
SCKn
SOTn
⎯
2 tCLKP + 55
⎯
2 tCLKP + 45
ns
Valid SIN →
SCK ↑ setup time
tIVSHE
SCKn
SINn
10
⎯
10
⎯
ns
SCK ↑ → valid
SIN hold time
tSHIXE
SCKn
SINn
tCLKP + 10
⎯
tCLKP + 10
⎯
ns
SCK rising time
tFE
SCKn
⎯
20
⎯
20
ns
SCK falling time
tRE
SCKn
⎯
20
⎯
20
ns
Internal
clock
operation
(master
mode)
External
clock
operation
(slave
mode)
* : Parameter m depends on tSCYCI and can be calculated as :
• if tSCYCI = 2*k*tCLKP, then m = k, where k is an integer > 2
• if tSCYCI = (2*k + 1)*tCLKP, then m = k + 1, where k is an integer > 1
Notes :
100
• The above values are AC characteristics for CLK synchronous mode.
• tCLKP is the cycle time of the peripheral clock.
DS07-16612-2E
MB91460D Series
• Internal clock mode (master mode)
tSCYCI
SCKn
for ESCR:SCES = 0
VOH
VOL
VOL
VOH
SCKn
for ESCR:SCES = 1
VOH
VOL
tSLOVI
tOVSHI
VOH
VOL
SOTn
tIVSHI
tSHIXI
VOH
VOL
SINn
VOH
VOL
• External clock mode (slave mode)
tSLSHE
SCKn
for ESCR:SCES = 0
VOH
SCKn
for ESCR:SCES = 1
VOL
tSHSLE
VOH
VOL
VOL
VOH
VOH
VOL
VOH
VOL
tRE
tFE
tSLOVE
SOTn
VOH
VOL
tIVSHE
SINn
DS07-16612-2E
VOH
VOL
tSHIXE
VOH
VOL
101
MB91460D Series
7.4.
I2C AC Timings at VDD5 = 3.0 to 5.5 V
• Conditions during AC measurements
All AC tests were measured under the following conditions:
- IOdrive = 3 mA
- VDD5 = 3.0 V to 5.5 V, Iload = 3 mA (VDD = 4.5 V to 5.5 V for MB91F467Dx)
- VSS5 = 0 V
- Ta = − 40 °C to + 105 °C
- Cl = 50 pF
- VOL = 0.3 × VDD5
- VOH = 0.7 × VDD5
- EPILR = 0, PILR = 0 (CMOS Hysteresis 0.3 × VDD5/0.7 × VDD5)
Fast mode:
(VDD5 = 3.5 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
fSCL
Value
Unit
Remark
Min
Max
SCLn
0
400
kHz
tHD;STA
SCLn, SDAn
0.6
⎯
μs
LOW period of the SCL clock
tLOW
SCLn
1.3
⎯
μs
HIGH period of the SCL clock
tHIGH
SCLn
0.6
⎯
μs
Setup time for a repeated START
condition
tSU;STA
SCLn, SDAn
0.6
⎯
μs
Data hold time for I2C-bus devices
tHD;DAT
SCLn, SDAn
0
0.9
μs
Data setup time
tSU;DAT
SCLn SDAn
100
⎯
ns
Rise time of both SDA and SCL
signals
tr
SCLn, SDAn
20 + 0.1Cb
300
ns
*1
Fall time of both SDA and SCL
signals
tf
SCLn, SDAn
20 + 0.1Cb
300
ns
*1
Setup time for STOP condition
tSU;STO
SCLn, SDAn
0.6
⎯
μs
Bus free time between a STOP
and START condition
tBUF
SCLn, SDAn
1.3
⎯
μs
Capacitive load for each bus line
Cb
SCLn, SDAn
⎯
400
pF
Pulse width of spike suppressed
by input filter
tSP
SCLn, SDAn
0
(1..1.5) ×
tCLKP
ns
SCL clock frequency
Hold time (repeated) START
condition. After this period, the first
clock pulse is generated
*2
*1 On MB91F467Dx only guaranteed for 4.5 V < VDD5 < 5.5 V.
*2 The noise filter will suppress single spikes with a pulse width of 0ns and between (1 to 1.5) cycles
of peripheral clock, depending on the phase relationship between I2C signals (SDA, SCL) and peripheral clock.
Note: tCLKP is the cycle time of the peripheral clock.
102
DS07-16612-2E
DS07-16612-2E
SCL
SDA
tHD;STA
tf
S
tr
tHD;DAT
tLOW
tHIGH
tSU;DAT
tSU;STA
Sr
tHD;STA
tSP
tr
P
tSU;ST0
tBUF
S
tf
MB91460D Series
103
MB91460D Series
7.5.
Free-run timer clock
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Input pulse width
Symbol
Pin name
Condition
tTIWH
tTIWL
CKn
⎯
Value
Min
Max
4tCLKP
⎯
Unit
ns
Note : tCLKP is the cycle time of the peripheral clock.
CKn
VIH
VIH
tTIWH
7.6.
VIL
VIL
tTIWL
Trigger input timing
(VDD5 = 3.0 V to 5.5 V, VSS5 = AVSS5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Input capture input trigger
A/D converter trigger
Symbol
Pin name
Condition
tINP
ICUn
tATGX
ATGX
Value
Unit
Min
Max
⎯
5tCLKP
⎯
ns
⎯
5tCLKP
⎯
ns
Note : tCLKP is the cycle time of the peripheral clock.
tATGX, tINP
ICUn,
ATGX
104
DS07-16612-2E
MB91460D Series
7.7.
External Bus AC Timings at VDD35 = 4.5 to 5.5 V
• Conditions during AC measurements
All AC tests were measured under the following conditions:
- IOdrive = 5 mA
- VDD35 = 4.5 V to 5.5 V, Iload = 5 mA
- VSS5 = 0 V
- Ta = − 40 °C to + 105 °C
- Cl = 50 pF
- VOL = 0.2 × VDD35
- VOH = 0.8 × VDD35
- EPILR = 0, PILR = 1 (Automotive Level = worst case)
7.7.1.
Basic Timing
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
MCLKO
MCLKO ↓ to CSXn delay time
MCLKO ↑ to CSXn delay time
(Addr → CS delay)
MCLKO ↓ to ASX delay time
MCLKO ↓ to BAAX delay time
MCLKO ↓ to Address valid delay time
Symbol
tCLCH
tCHCL
Pin name
Max
1/2 x tCLKT − 7
1/2 × tCLKT + 7
ns
1/2 × tCLKT − 7
1/2 × tCLKT + 7
ns
⎯
9
ns
⎯
8
ns
−5
+2
ns
⎯
8
ns
⎯
8
ns
MCLKO
BAAX
⎯
5
ns
1
⎯
ns
MCLKO
A25 to A0
⎯
11
ns
MCLKO
MCLKO
CSXn
tCHCSL
tCLASL
tCLASH
tCLBAL
tCLBAH
tCLAV
Unit
Min
tCLCSL
tCLCSH
Value
MCLKO
ASX
Note : tCLKT is the cycle time of the external bus clock.
DS07-16612-2E
105
MB91460D Series
tCLCH
tCHCL
tCYC
MCLKO
tCLCSL
tCLCSH
CSXn
tCHCSL
delaved CSXn
tCLASH
tCLASL
ASX
tCLAV
ADDRESS
tCLBAH
tCLBAL
BAAX
106
DS07-16612-2E
MB91460D Series
7.7.2.
Synchronous/Asynchronous read access with external MCLKI input
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
tCHRL
Value
Unit
Min
Max
MCLKO
RDX
−5
2
ns
tCHRH
MCLKI
RDX
8
16
ns
Data valid to RDX ↑ setup time
tDSRH
RDX
D31 to D0
19
⎯
ns
RDX ↑ to Data valid hold time
(external MCLKI input)
tRHDX
RDX
D31 to D0
0
⎯
ns
Data valid to MCLKI ↑ setup time
tDSCH
MCLKI
D31 to D0
3
⎯
ns
MCLKI ↑ to Data valid hold time
tCHDX
MCLKI
D31 to D0
1
⎯
ns
MCLKO ↓ to WRXn (as byte enable)
delay time
tCLWRL
⎯
9
ns
−1
⎯
ns
⎯
9
ns
⎯
8
ns
MCLKO ↑ /MCLKI ↑ to RDX delay
time
MCLKO ↓ to CSXn delay time
tCLWRH
tCLCSL
tCLCSH
MCLKO
WRXn
MCLKO
CSXn
Note: The usage of the external feedback from MCLKO to MCLKI is not recommended.
DS07-16612-2E
107
MB91460D Series
MCLKO
MCLKI
tCLCSH
tCLCSL
CSXn
tCLWRH
tCLWRL
WRXn
(as byte enable)
tCHRH
tCHRL
RDX
tDSRH
tDSCH
tRHDX
tCHDX
DATA IN
108
DS07-16612-2E
MB91460D Series
7.7.3.
Synchronous/Asynchronous read access with internal MCLKO --> MCLKI feedback
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
MCLKO ↑ to RDX delay time
Symbol
TCHRL
TCHRH
Pin name
MCLKO RDX
Value
Unit
Min
Max
−5
2
ns
−5
2
ns
Data valid to RDX ↑ setup time
TDSRH
RDX
D31 to D0
20
⎯
ns
RDX ↑ to Data valid hold time
(internal MCLKO → MCLKI /
/MCLKI feedback)
TRHDX
RDX
D31 to D0
0
⎯
ns
⎯
9
ns
−1
⎯
ns
⎯
9
ns
⎯
8
ns
MCLKO ↓ to WRXn
(as byte enable) delay time
MCLKO ↓ to CSXn delay time
TCLWRL
TCLWRH
TCLCSL
TCLCSH
MCLKO
WRXn
MCLKO
CSXn
MCLKO
TCLCSL
TCLCSH
CSXn
TCLWRL
TCLWRH
WRXn
(as byte enable)
TCHRH
TCHRL
RDX
TDSRH
TRHDX
DATA IN
DS07-16612-2E
109
MB91460D Series
7.7.4.
Synchronous write access - byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
MCLKO ↓ to WEX delay time
Symbol
Pin name
TCLWL
TCLWH
Value
Unit
Min
Max
MCLKO
WEX
⎯
9
ns
2
⎯
ns
Data valid to WEX ↓ setup time
TDSWL
WEX
D31 to D0
− 11
⎯
ns
WEX ↑ to Data valid hold time
TWHDH
WEX
D31 to D0
tCLKT − 10
⎯
ns
MCLKO ↓ to WRXn (as byte enable)
delay time
TCLWRL
MCLKO
WRXn
⎯
9
ns
−1
⎯
ns
⎯
9
ns
⎯
8
ns
MCLKO ↓ to CSXn delay time
TCLWRH
TCLCSL
MCLKO
CSXn
TCLCSH
MCLKO
TCLCSH
TCLCSL
CSXn
TCLWRH
TCLWRL
WRXn
(as byte enable)
TCLWH
TCLWL
WEX
TDSWL
TWHDH
DATA OUT
110
DS07-16612-2E
MB91460D Series
7.7.5.
Synchronous write access - no byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
MCLKO ↓ to WRXn delay time
Symbol
Pin name
TCLWRL
MCLKO
WRXn
TCLWRH
Value
Unit
Min
Max
⎯
9
ns
−1
⎯
ns
Data valid to WRXn ↓ setup time
TDSWRL
WRXn
D31 to D0
− 12
⎯
ns
WRXn ↑ to Data valid hold time
TWRHDH
WRXn
D31 to D0
tCLKT − 8
⎯
ns
MCLKO
CSXn
⎯
9
ns
⎯
8
ns
MCLKO ↓ to CSXn delay time
TCLCSL
TCLCSH
MCLKO
TCLCSH
TCLCSL
CSXn
TCLWRH
TCLWRL
WRXn
TDSWRL
TWRHDH
DATA OUT
DS07-16612-2E
111
MB91460D Series
7.7.6.
Asynchronous write access - byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
WEX ↓ to WEX ↑ pulse width
TWLWH
Data valid to WEX ↓ setup time
WEX ↑ to Data valid hold time
WEX to WRXn delay time
WEX to CSXn delay time
Value
Unit
Min
Max
WEX
tCLKT − 2
⎯
ns
TDSWL
WEX
D31 to D0
1/2 × tCLKT − 13
⎯
ns
TWHDH
WEX
D31 to D0
1/2 × tCLKT − 10
⎯
ns
WEX
WRXn
⎯
1/2 × tCLKT + 2
ns
1/2 × tCLKT − 4
⎯
ns
⎯
1/2 × tCLKT
ns
1/2 × tCLKT − 5
⎯
ns
TWRLWL
TWHWRH
TCLWL
TWHCH
WEX
CSXn
CSXn
TCLWL
TWHCH
WRXn
(as byte enable)
TWHWRH
TWRLWL
TWLWH
WEX
TDSWL
TWHDH
DATA OUT
112
DS07-16612-2E
MB91460D Series
7.7.7.
Asynchronous write access - no byte control type
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
WRXn ↓ to WRXn ↑ pulse width
TWRLWRH
Data valid to WRXn ↓ setup time
WRXn ↑ to Data valid hold time
WRXn to CSXn delay time
Value
Unit
Min
Max
WRXn
tCLKT − 1
⎯
ns
TDSWRL
WRXn
D31 to D0
1/2 × tCLKT − 14
⎯
ns
TWRHDH
WRXn
D31 to D0
1/2 × tCLKT − 7
⎯
ns
WRXn
CSXn
⎯
1/2 × tCLKT − 1
ns
1/2 × tCLKT − 3
⎯
ns
TCLWRL
TWRHCH
CSXn
TWRHCH
TCLWRL
TWRLWRH
WRXn
TDSWRL
TWRHDH
DATA OUT
DS07-16612-2E
113
MB91460D Series
7.7.8.
RDY waitcycle insertion
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
RDY setup time
TRDYS
RDY hold time
TRDYH
Value
Unit
Min
Max
MCLKO
RDY
21
⎯
ns
MCLKO
RDY
0
⎯
ns
MCLKO
TRDYS
TRDYH
RDY
114
DS07-16612-2E
MB91460D Series
7.7.9.
Bus hold timing
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
MCLKO ↓ to BGRNTX delay time
Symbol
Pin name
TCLBGL
TCLBGH
Bus HIZ to BGRNTX ↓
TAXBGL
BGRNTX ↑ to Bus drive
TBGHAV
Value
Unit
Min
Max
MCLKO
BGRNTX
⎯
2 × tCLKT + 5
ns
⎯
2 × tCLKT + 2
ns
BGRNTX
MCLK*
A0 to An
RDX, ASX
WRXn,WEX
CSXn,BAAX
tCLKT − 6
⎯
ns
tCLKT + 8
⎯
ns
Note : BRQ must be kept High until the bus is granted (this is acknowledged by the falling edge of BGRNTX).
It must be kept High as long as the bus shall be hold.
After releasing the bus (BRQ set to Low) this is acknowledged by the rising edge of BGRNTX.
MCLKO
BRQ
TCLBGL
TCLBGH
TAXBGL
TBGHAV
BGRNTX
ADDR,RDX,WRX,
WEX,CSXn,ASX,
MCLKE,MCLKI,
BAAX
DS07-16612-2E
115
MB91460D Series
7.7.10. Clock relationships
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
MCLKO ↓ to MCLKE (in sleep mode)
Symbol
Pin name
TCLML
MCLKO
MCLKE
TCLMH
Value
Unit
Min
Max
⎯
7
ns
−1
⎯
ns
MCLKO
TCLML
TCLMH
MCLKE(sleep)
116
DS07-16612-2E
MB91460D Series
7.7.11. DMA transfer
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
MCLKO ↓ to DACKX delay time
MCLKO ↓ to DEOP delay time
Symbol
Pin name
TCLDAL
TCLDAH
TCLDEL
TCLDEH
Value
Unit
Min
Max
MCLKO
DACKXn
⎯
9
ns
⎯
6
ns
MCLKO
DEOPn
⎯
8
ns
⎯
9
ns
MCLKO ↑ to DACKX delay time
(ADDR → delayed CS)
TCHDAL
MCLKO
DACKXn
−4
3
ns
MCLKO ↑ to DEOP delay time
(ADDR → delayed CS)
TCHDEL
MCLKO
DEOPn
−4
3
ns
DREQ setup time
TDRQS
MCLKO
DREQn
23
⎯
ns
DREQ hold time
TDRQH
MCLKO
DREQn
0
⎯
ns
DEOTXn setup time
TDTXS
MCLKO
DEOTXn
24
⎯
ns
DEOTXn hold time
TDTXH
MCLKO
DEOTXn
0
⎯
ns
Note : DREQ and DEOTX must be applied for at least 5 × tCLKT to ensure that they are really sampled and evaluated.
Under best case conditions (DMA not busy) only setup and hold times are required.
DS07-16612-2E
117
MB91460D Series
MCLKO
TCLDAL
TCLDAH
TCLDEL
TCLDEH
DACKX
DEOP
TCHDAL
delayed DACKX
TCHDEL
delayed DEOP
TDRQS
TDRQH
TDTXS
TDTXH
DREQ
DEOTX
118
DS07-16612-2E
MB91460D Series
7.8.
External Bus AC Timings at VDD35 = 3.0 to 4.5 V
• Conditions during AC measurements
All AC tests were measured under the following conditions:
- IOdrive = 5 mA
- VDD35 = 3.0 V to 4.5 V, Iload = 3 mA
- VSS5 = 0 V
- Ta = − 40 °C to + 105 °C
- Cl = 50 pF
- VOL = 0.2 × VDD35
- VOH = 0.8 × VDD35
- EPILR = 0, PILR = 1 (Automotive Level = worst case)
7.8.1.
Basic Timing
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
MCLKO
MCLKO ↓ to CSXn delay time
MCLKO ↑ to CSXn delay time
(Addr → CS delay)
MCLKO ↓ to ASX delay time
MCLKO ↓ to BAAX delay time
MCLKO ↓ to Address valid delay time
DS07-16612-2E
Symbol
TCLCH
TCHCL
Pin name
Max
1/2 × tCLKT − 13
1/2 × tCLKT + 13
ns
1/2 × tCLKT − 13
1/2 × tCLKT + 13
ns
⎯
6
ns
⎯
7
ns
− 11
0
ns
MCLKO
ASX
⎯
6
ns
⎯
9
ns
MCLKO
BAAX
⎯
3
ns
1
⎯
ns
MCLKO
A25 to A0
⎯
13
ns
MCLKO
MCLKO
CSXn
TCHCSL
TCLASL
TCLASH
TCLBAL
TCLBAH
TCLAV
Unit
Min
TCLCSL
TCLCSH
Value
119
MB91460D Series
TCLCH
TCHCL
TCYC
MCLKO
TCLCSL
TCLCSH
CSXn
TCHCSL
delayed CSXn
TCLASH
TCLASL
ASX
TCLAV
ADDRESS
TCLBAH
TCLBAL
BAAX
120
DS07-16612-2E
MB91460D Series
7.8.2.
Synchronous/Asynchronous read access with external MCLKI input
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
TCHRL
Value
Unit
Min
Max
MCLKO
RDX
− 12
0
ns
TCHRH
MCLKI
RDX
12
26
ns
Data valid to RDX ↑ setup time
TDSRH
RDX
D31 to D0
28
⎯
ns
RDX ↑ to Data valid hold time
(external MCLKI input)
TRHDX
RDX
D31 to D0
0
⎯
ns
Data valid to MCLKI ↑ setup time
TDSCH
MCLKI
D31 to D0
3
⎯
ns
MCLKI ↑ to Data valid hold time
TCHDX
MCLKI
D31 to D0
1
⎯
ns
MCLKO
WRXn
⎯
6
ns
0
⎯
ns
MCLKO
CSXn
⎯
6
ns
⎯
7
ns
MCLKO ↑/MCLKI ↑ to RDX
delay time
MCLKO ↓ to WRXn
(as byte enable) delay time
MCLKO ↓ to CSXn delay time
TCLWRL
TCLWRH
TCLCSL
TCLCSH
Note: The usage of the external feedback from MCLKO to MCLKI is not recommended.
DS07-16612-2E
121
MB91460D Series
MCLKO
MCLKI
TCLCSH
TCLCSL
CSXn
TCLWRH
TCLWRL
WRXn
(as byte enable)
TCHRH
TCHRL
RDX
TDSRH
TRHDX
TDSCH
TCHDX
DATA IN
122
DS07-16612-2E
MB91460D Series
7.8.3.
Synchronous/Asynchronous read access with internal MCLKO --> MCLKI feedback
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
TCHRL
MCLKO ↑ to RDX delay time
TCHRH
Pin name
MCLKO RDX
Value
Unit
Min
Max
− 12
0
ns
−9
1
ns
Data valid to RDX ↑ setup time
TDSRH
RDX
D31 to D0
29
⎯
ns
RDX ↑ to Data valid hold time
(internal MCLKO → MCLKI /
/MCLKI feedback)
TRHDX
RDX
D31 to D0
0
⎯
ns
MCLKO
WRXn
⎯
6
ns
0
⎯
ns
MCLKO
CSXn
⎯
6
ns
⎯
7
ns
TCLWRL
MCLKO ↓ to WRXn
(as byte enable) delay time
TCLWRH
TCLCSL
MCLKO ↓ to CSXn delay time
TCLCSH
MCLKO
TCLCSL
TCLCSH
CSXn
TCLWRL
TCLWRH
WRXn
(as byte enable)
TCHRH
TCHRL
RDX
TDSRH
TRHDX
DATA IN
DS07-16612-2E
123
MB91460D Series
7.8.4.
Synchronous write access - byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
MCLKO ↓ to WEX delay time
Symbol
Pin name
TCLWL
TCLWH
Value
Unit
Min
Max
MCLKO
WEX
⎯
7
ns
1
⎯
ns
Data valid to WEX ↓ setup time
TDSWL
WEX
D31 to D0
− 20
⎯
ns
WEX ↑ to Data valid hold time
TWHDH
WEX
D31 to D0
tCLKT − 19
⎯
ns
MCLKO ↓ to WRXn (as byte enable)
delay time
TCLWRL
MCLKO
WRXn
⎯
6
ns
0
⎯
ns
MCLKO
CSXn
⎯
6
ns
⎯
7
ns
MCLKO ↓ to CSXn delay time
TCLWRH
TCLCSL
TCLCSH
MCLKO
TCLCSH
TCLCSL
CSXn
TCLWRH
TCLWRL
WRXn
(as byte enable)
TCLWH
TCLWL
WEX
TDSWL
DATA OUT
TWHDH
MB91460D Series
7.8.5.
Synchronous write access - no byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
MCLKO ↓ to WRXn delay time
Symbol
Pin name
TCLWRL
TCLWRH
Value
Unit
Min
Max
MCLKO
WRXn
⎯
6
ns
0
⎯
ns
Data valid to WRXn ↓ setup time
TDSWRL
WRXn
D31 to D0
− 20
⎯
ns
WRXn ↑ to Data valid hold time
TWRHDH
WRXn
D31 to D0
tCLKT − 14
⎯
ns
MCLKO
CSXn
⎯
6
ns
⎯
7
ns
MCLKO ↓ to CSXn delay time
TCLCSL
TCLCSH
MCLKO
TCLCSH
TCLCSL
CSXn
TCLWRH
TCLWRL
WRXn
TDSWRL
TWRHDH
DATA OUT
DS07-16612-2E
125
MB91460D Series
7.8.6.
Asynchronous write access - byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
WEX ↓ to WEX ↑ pulse width
TWLWH
Data valid to WEX ↓ setup time
WEX ↑ to Data valid hold time
WEX to WRXn delay time
WEX to CSXn delay time
Value
Unit
Min
Max
WEX
tCLKT − 2
⎯
ns
TDSWL
WEX
D31 to D0
1/2 × tCLKT − 20
⎯
ns
TWHDH
WEX
D31 to D0
1/2 × tCLKT − 20
⎯
ns
WEX
WRXn
⎯
1/2 × tCLKT + 3
ns
1/2 × tCLKT − 7
⎯
ns
⎯
1/2 × tCLKT − 1
ns
1/2 × tCLKT − 4
⎯
ns
TWRLWL
TWHWRH
TCLWL
TWHCH
WEX
CSXn
CSXn
TCLWL
TWHCH
WRXn
(as byte enable)
TWHWRH
TWRLWL
TWLWH
WEX
TDSWL
TWHDH
DATA OUT
126
DS07-16612-2E
MB91460D Series
7.8.7.
Asynchronous write access - no byte control type
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
WRXn ↓ to WRXn ↑ pulse width
TWRLWRH
Data valid to WRXn ↓ setup time
WRXn ↑ to Data valid hold time
WRXn to CSXn delay time
Value
Unit
Min
Max
WRXn
tCLKT − 2
⎯
ns
TDSWRL
WRXn
D31 to D0
1/2 × tCLKT − 21
⎯
ns
TWRHDH
WRXn
D31 to D0
1/2 × tCLKT − 18
⎯
ns
WRXn
CSXn
⎯
1/2 × tCLKT − 1
ns
1/2 × tCLKT − 4
⎯
ns
TCLWRL
TWRHCH
CSXn
TWRHCH
TCLWRL
TWRLWRH
WRXn
TDSWRL
TWRHDH
DATA OUT
DS07-16612-2E
127
MB91460D Series
7.8.8.
RDY waitcycle insertion
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
Symbol
Pin name
RDY setup time
TRDYS
RDY hold time
TRDYH
Value
Unit
Min
Max
MCLKO
RDY
37
⎯
ns
MCLKO
RDY
0
⎯
ns
MCLKO
TRDYS
TRDYH
RDY
128
DS07-16612-2E
MB91460D Series
7.8.9.
Bus hold timing
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
MCLKO ↓ to BGRNTX delay time
Symbol
Pin name
TCLBGL
TCLBGH
Bus HIZ to BGRNTX ↓
TAXBGL
BGRNTX ↑ to Bus drive
TBGHAV
Value
Unit
Min
Max
MCLKO
BGRNTX
⎯
2 × tCLKT + 16
ns
⎯
2 × tCLKT + 3
ns
BGRNTX
MCLK*
A0 to An
RDX, ASX
WRXn,WEX
CSXn,BAAX
tCLKT + 1
⎯
ns
tCLKT + 1
⎯
ns
Note : BRQ must be kept High until the bus is granted (this is acknowledged by the falling edge of BGRNTX).
It must be kept High as long as the bus shall be hold.
After releasing the bus (BRQ set to Low) this is acknowledged by the rising edge of BGRNTX.
MCLKO
BRQ
TCLBGL
TCLBGH
TAXBGL
TBGHAV
BGRNTX
ADDR,RDX,WRX,
WEX,CSXn,ASX,
MCLKE,MCLKI,
BAAX
DS07-16612-2E
129
MB91460D Series
7.8.10. Clock relationships
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
MCLKO ↓ to MCLKE
(in sleep mode)
Symbol
Pin name
TCLML
MCLKO
MCLKE
TCLMH
Value
Unit
Min
Max
⎯
3
ns
0
⎯
ns
MCLKO
TCLML
TCLMH
MCLKE(sleep)
130
DS07-16612-2E
MB91460D Series
7.8.11. DMA transfer
(VDD35 = 3.0 V to 4.5 V, Vss5 = AVss5 = 0 V, TA = −40 °C to + 105 °C)
Parameter
MCLKO ↓ to DACKX delay time
MCLKO ↓ to DEOP delay time
Symbol
Pin name
TCLDAL
TCLDAH
TCLDEL
TCLDEH
Value
Unit
Min
Max
MCLKO
DACKXn
⎯
7
ns
⎯
8
ns
MCLKO
DEOPn
⎯
7
ns
⎯
11
ns
MCLKO ↑ to DACKX delay time
(ADDR → delayed CS)
TCHDAL
MCLKO
DACKXn
− 10
2
ns
MCLKO ↑ to DEOP delay time
(ADDR → delayed CS)
TCHDEL
MCLKO
DEOPn
− 10
1
ns
DREQ setup time
TDRQS
MCLKO
DREQn
38
⎯
ns
DREQ hold time
TDRQH
MCLKO
DREQn
0
⎯
ns
DEOTXn setup time
TDTXS
MCLKO
DEOTXn
39
⎯
ns
DEOTXn hold time
TDTXH
MCLKO
DEOTXn
0
⎯
ns
Note : DREQ and DEOTX must be applied for at least 5 × tCLKT to ensure that they are really sampled and evaluated.
Under best case conditions (DMA not busy) only setup and hold times are required.
DS07-16612-2E
131
MB91460D Series
MCLKO
TCLDAL
TCLDAH
TCLDEL
TCLDEH
DACKX
DEOP
TCHDAL
delayed DACKX
TCHDEL
delayed DEOP
TDRQS
TDRQH
TDTXS
TDTXH
DREQ
DEOTX
132
DS07-16612-2E
MB91460D Series
■ ORDERING INFORMATION
Part number
Package
MB91F467DAPFVS-GSE2
MB91F467DBPFVS-GSE2
MB91F467DAPVS-GSE2
MB91F467DBPVS-GSE2
DS07-16612-2E
Remarks
not recommended
208-pin plastic QFP
(FPT-208P-M04)
not recommended
not recommended
Lead-free package
133
MB91460D Series
■ PACKAGE DIMENSION
208-pin plastic QFP
(FPT-208P-M04)
208-pin plastic QFP
(FPT -208P-M04)
Lead pitch
0.50 mm
Pa ckage width ×
package length
28.0 × 28.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.95 mm MAX
We ight
5.71g
Remar k
Low heat resistance type
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
30.60±0.20(1.205±.008)SQ
* 28.00±0.10(1.102±.004)SQ
0.17
156
.007
105
157
+0.03
–0.08
+.001
–.003
104
0.08(.003)
Details of "A" par t
3.75
.148
+0.20
–0.30
+.008
–.012
(Mounting height)
0.40
INDEX
0 ˚ ~8 ˚
208
LEAD No .
53
1
52
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
"A"
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
+0.10
–0.15
+.004
–.006
.016
(Stand off)
0.25(.010)
M
2003-2008 FUJITSU MICROELECTRONICS LIMITED F208020S-c-3-5
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
134
DS07-16612-2E
MB91460D Series
■ REVISION HISTORY
Version
Date
2.0
2007-09-04
Initial version
2007-10-08
Revision history table added
Fixed PDF generation problem before section “AD converter characteristics”
Absolute maximum ratings:
Smoothing capacitor size at VCC18C changed to “typ 4.7uF”
Output voltage 2 is max. VDD35
Recommended operating conditions: Power supply slew rate fixed
Exchanged the sequence of device names into
“MB91F465DA, MB91F467DA” where they appeare on one line
2.1
2.2
2007-10-16
Remark
Moved revision history to the end of file
Features: Added Clock Monitor
Corrected VCC18C pin number in table “Power supply/Ground pins” pg.14
Electrical characteristics: Added section
7.FLASH memory program/erase characteristics
2.3
2.4
2007-10-22
DC characterisitcs: Corrected ICCH in STOP + RTC 100kHz mode
and ILV (Icc of low volt detection) max. value
2007-10-25
FLASH memory program/erase characteristics: Typo fixed in note *1
Recommended operating conditions: Corrected text for smoothing
capacitor at VCC18C pin
Naming inconsistency AVSS / AVSS5 fixed
Features: added Up/Down counter
Product lineup: fixed number of interrupt channels
Handling devices: changed the notes about external clock supply
and removed section “Single phase clock supply”
Clock timing: removed “Single phase clock supply” from freq. table
DC characterisitcs: IIL = +/- 3 uA at 105 deg.C
IO CIRCUIT TYPE: Corrected oscillator pin block diagrams
ELECTRICAL CHARACTERISTICS: re-arranged section sequence
Fixed typos in ALARM comparator spec.
Added MB91F467DB (called F467Dx if the text item is for bot revisions)
Corrected IO-MAP according to latest proofread on F460G series
Various corrections after proofread by FJ
2.5
2008-1-11
2.6
2008-02-04
Added MEMO and DISCLAIMER
2.7
2008-02-18
AC-Characteristics: Replaced “rising”/”falling” with arrow-up/arrow-down
DS07-16612-2E
135
MB91460D Series
Version
Date
Remark
2.8
2008-06-20
Corrected missing bullets on PDF pages 2+3
Pin Assignment, Block Diagram:
Corrected naming and assignments of TTG inputs, SGO and DACKX0
Notes on PS register: Re-formatted for better understanding
ADC Characteristics: Offset between ADC channels is max. 4 LSB
DC Characteristics: Added ILVI (ICC of internal low voltage detection),
renamed ILV into ILVE (for external low voltage detection)
AC Characteristics for external bus: Added notes that the usage of external
feedback MCLKO --> MCLKI is not recommended.
Flash parallel programming mode:
Added notes about the pins to be set fix-0 / fix-1 (MD_2:0,...)
Added section about the wait times after power on
Flash operation modes:
Added note about the BootROM fuction entry address for operation
mode switch.
Package Dimension: Updated package drawing
All pages: Corrected typos and formatting bugs found by FJ proofread
2.9
2008-06-30
EMBEDDED PROGRAM/DATA MEMORY (FLASH): Corrected "The operation mode of the flash memory ..." instead of "of the MCU"
2.10
2008-08-04
Resources,Product lineup: Added Supply Supervisor (Low voltage detection)
DC Characteristics: Updated pull-up/pull-down resistance values,
updated and re-numbered the table footnotes
2008-08-18
Interrupt Vector Table: corrected the footnotes
Flash Security: Corrected the sector assignments of FSV1/FSV2 bits
Electrical Characteristics: removed the note that analog input/output
pins cannot accept +B signal input.
Ordering information: updated the part numbers
All pages: Kilobytes are now written with "K"
2.11
136
DS07-16612-2E
MB91460D Series
■ MEMO AND DISCLAIMER
MEMO
DS07-16612-2E
137
MB91460D Series
MEMO
138
DS07-16612-2E
MB91460D Series
MEMO
DS07-16612-2E
139
MB91460D Series
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg., 7-1, Nishishinjuku 2-chome,
Shinjuku-ku, Tokyo 163-0722, Japan
Tel: +81-3-5322-3329
http://jp.fujitsu.com/fml/en/
For further information please contact:
North and South America
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#05-08 New Tech Park 556741 Singapore
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Europe
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http://emea.fujitsu.com/microelectronics/
FUJITSU MICROELECTRONICS SHANGHAI CO., LTD.
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Shanghai 200002, China
Tel : +86-21-6146-3688 Fax : +86-21-6335-1605
http://cn.fujitsu.com/fmc/
Korea
FUJITSU MICROELECTRONICS KOREA LTD.
206 Kosmo Tower Building, 1002 Daechi-Dong,
Gangnam-Gu, Seoul 135-280, Republic of Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://kr.fujitsu.com/fmk/
FUJITSU MICROELECTRONICS PACIFIC ASIA LTD.
10/F., World Commerce Centre, 11 Canton Road,
Tsimshatsui, Kowloon, Hong Kong
Tel : +852-2377-0226 Fax : +852-2376-3269
http://cn.fujitsu.com/fmc/en/
Specifications are subject to change without notice. For further information please contact each office.
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating
the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
or exercise of any intellectual property right, such as patent right or copyright, or any other right of FUJITSU MICROELECTRONICS
or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU MICROELECTRONICS assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to
the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear
facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current
levels and other abnormal operating conditions.
Exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of
the Foreign Exchange and Foreign Trade Control Law of Japan and/or US export control laws.
The company names and brand names herein are the trademarks or registered trademarks of their respective owners.
Edited: Sales Promotion Department