FAIRCHILD FAN5019B

www.fairchildsemi.com
FAN5019B
6-Bit VID Controller 2-4 Phase VR10.X Controller
Features
General Description
•
•
•
•
The FAN5019B is a multi-phase DC-DC controller for
implementing high-current, low-voltage, CPU core power
regulation circuits. It is part of a chipset that includes external MOSFET drivers and power MOSFETS. The
FAN5019B drives up to four synchronous-rectified buck
channels in parallel. The multi-phase buck converter architecture uses interleaved switching to multiply ripple frequency by the number of phases and reduce input and output
ripple currents. Lower ripple results in fewer components,
lower component cost, reduced power dissipation, and
smaller board area.
•
•
•
•
•
•
•
•
•
•
•
•
•
Improved Noise Immunity
Improved Load Line Accuracy
TTL Compatible VID Inputs
Fully Pin and Function compatible with existing
FAN5019 and ADP3188 Controllers
Precision Multi-Phase DC-DC Core Voltage Regulation
– ±10mV Output Voltage Accuracy Over Temperature
Differential Remote Voltage Sensing
Selectable 2-, 3-, or 4-Phase Operation
Selectable VRM9 or VRM10 Operation
Up to 1MHz per Phase Operation (4MHz ripple
Frequency)
Lossless Inductor Current Sensing for Loadline
Compensation
– External Temperature Compensation
Accurate Loadline Programming (Meets Intel®
VRM/VRD10.x CPU Specifications)
Accurate Channel-Current Balancing for Thermal
Optimization and Layout Compensation
Convenient 12V Supply Biasing
6-bit Voltage Identification (VID) Input
– .8375V to 1.600V in 12.5mV Steps
– Dynamic VID Capability with Fault-Blanking for
glitch-less Output voltage Changes
Adjustable Over Current Protection with Programmable
Latch-Off Delay. Latch-Off Function may be Disabled
Over-Voltage Protection – Internal OVP Crowbar
Protection
Package: 28L-TSSOP
Applications
• VRM/VRD 9.x and 10.x Computer DC/DC Converter
• High-Current, Low-Voltage DC/DC Rail
The FAN5019B features a high-bandwidth control loop to
provide optimal response to load transients. The FAN5019B
senses current using lossless techniques: Phase current is
measured through each of the output inductors. This current
information is summed, averaged and used to set the loadline
of the output via programmable "droop." The droop is temperature compensated to achieve precise loadline characteristics over the entire operating range. Additionally,
individual phase current is measured using the RDS(ON) of
the low-side MOSFETs. This information is used to dynamically balance/steer per-phase current. The phase currents
are also summed and averaged for over-current detection.
Dynamic-VID technology allows on-the-fly VID changes
with controlled, glitch-less output. Additionally, short-circuit
protection, adjustable current limiting, over-voltage protection and power-good circuitry combine to ensure reliable and
safe operation. FAN5019B is specified over the commercial
temperature range of 0°C to +85°C and operates from a single +12V supply which simplifies design. FAN5019B is
available in a 28L-TSSOP package.
Block Diagram
VIN
Φ1
FAN5009
Φ2
FAN5019B
VIN
VOUT
Φ3
Φ4
FAN5009
REV. 1.0.0 Jul/15/05
FAN5019B
PRODUCT SPECIFICATION
Pin Assignments
VID4
1
28
VCC
VID3
2
27
PWM1
VID2
3
26
PWM2
VID1
4
25
PWM3
VID0
5
24
PWM4
VID5/SEL
6
23
SW1
FBRTN
7
22
SW2
FB
8
FAN5019B
TSSOP-28
21
SW3
COMP
9
20
SW4
PWRGD
10
19
GND
EN
11
18
CSCOMP
DELAY
12
17
CSSUM
RT
13
16
CSREF
RAMPADJ
14
15
ILIMIT
Pin Definitions
Pin Number
Pin Name
Pin Function Description
1–5
VID [4:0]
VID inputs. Determines the output voltage via the internal DAC. These inputs
comply to VRM10/VRD10 specifications for static and dynamic operation. All have
internal pull-ups (1.25V for VRM10 and 2.5V for VRM9) so leaving them open
results in logic high. Leaving VID[4:0] open results in a "No CPU" condition
disabling the PWM outputs.
6
VID5/SEL
VID5 Input/DAC Select. Dual function pin that is either the 12.5mV DAC LSB for
VRM10 or selects the VRM9 DAC codes when forced higher than Vtblsel(VRM9)
voltage. The truth table is as follows:
VVID5/SEL held > Vtblsel(VRM9); VRM9 DAC table is selected (See Table 3)
VViD5/SEL < Vtblsel(VRM10); VRM10 DAC table is selected (See Table 2) and
VViD5/SEL pin is used as VID5 input.
2
7
FBRTN
Feedback Return. Error Amp and DAC reference point.
8
FB
9
COMP
10
PWRGD
11
EN
12
DELAY
13
RT
14
RAMPADJ
PWM Current Ramp Adjust. An external resistor to Vcc will adjust the amplitude of
the internal PWM ramp.
15
ILIMIT
Current Limit Adjust. An external resistor sets the current limit threshold for the
regulator circuit. This pin is internally pulled low when EN is low or the UVLO circuit
is active. It is also used to enable the drivers.
Feedback Input. Inverting input for Error Amp this pin is used for external
compensation. This pin can also be used to introduce DC offset voltage to the
output.
Error Amp output. This pin is used for external compensation.
Power Good output. This is an open-drain output that asserts when the output
voltage is within the specified tolerance. It is expected to be pulled up to an external
voltage rail.
Enable. Logic signal that enables the controller when logic high.
Soft-start and Current Limit Delay. An external resistor and capacitor sets the
softstart ramp rate and the over-current latch off delay.
Switching Frequency Adjust. This pin adjusts the output PWM switching
frequency via an external resistor.
REV. 1.0.0 Jul/15/05
PRODUCT SPECIFICATION
FAN5019B
Pin Definitions (continued)
Pin Number
Pin Name
16
CSREF
Current Sense Reference. Non-Inverting input of the current sense amp. Sense
point for the output voltage used for OVP and PWRGD.
17
CSSUM
Current Sense Summing node. Inverting input of the current sense amp.
18
CSCOMP
19
GND
20–23
SW[4:1]
24–27
PWM[4:1]
PWM outputs. CMOS outputs for driving external gate driver such as the FAN5009.
Unused phases should be connected to Ground.
28
VCC
Chip Power. Bias supply for the chip. Connect directly to a +12V supply. Bypass
with a 1µF MLCC capacitor.
REV. 1.0.0 Jul/15/05
Pin Function Description
Current Sense Compensation node. Output of the current sense amplifier. This
pin is used, in conjunction with CSSUM to set the output droop compensation and
current loop response.
Ground. Signal ground for the device.
Phase Current Sense/Balance inputs. Phase-to-phase current sense and
balancing inputs. Unused phases should be left open.
3
FAN5019B
PRODUCT SPECIFICATION
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.
Parameter
Min.
Max.
Units
Supply Voltage: VCC to GND
-0.3
+15
V
Voltage on FBRTN pin
-0.3
+0.3
V
Voltage on SW1-SW4 (<250ns duration)
-5
+25
V
Voltage on SW1-SW4 (>=250ns duration)
-0.3
+15
V
Voltage on RAMPADJ, CSSUM
-0.3
VCC+0.3
V
Voltage on any other pin
-0.3
+5.5
V
Thermal Information
Parameter
Min.
Max.
Units
0
+150
°C
–65
+150
°C
Lead Soldering Temperature, 10 seconds
+300
°C
Vapor Phase, 60 seconds
+215
°C
Infrared, 15 seconds
+220
°C
2
W
Operating Junction Temperature (TJ)
Storage Temperature
Typ
Power Dissipation (PD) @ TA = 25°C
Thermal Resistance (θJA) (See Note 1)
50
°C/W
Recommended Operating Conditions (See Figure 8)
Parameter
Conditions
Min.
Typ.
Max.
Units
Supply Voltage VCC
VCC to GND
10.2
12
13.8
V
°C
Ambient Operating Temperature
0
+85
Operating Junction Temperature (TJ)
0
+125
Note:
1: θJA is defined as 1 oz. copper PCB with 1 in2 pad.
4
REV. 1.0.0 Jul/15/05
PRODUCT SPECIFICATION
FAN5019B
Electrical Specifications
(VCC = 12V, TA = 0°C to +85°C and FBRTN=GND, using circuit in Figure 1, unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Error Amplifier
•
0.5
3.5
V
•
•
-10
-12
+10
+12
mV
IFB
•
-17
-15
-13
µA
FBRTN Current
IFBRTN
•
150
180
µA
Output Current
IO(ERR)
FB forced to VOUT – 3%
Gain Bandwidth Product
GBW
Output Voltage Range
VCOMP
Accuracy
VFB
Relative to DAC Setting,
referenced to FBRTN,
CSSUM = CSCOMP,
Test Circuit 3
Line Regulation
ΔVFB
VCC=10V to 14V
Input Bias Current
DC Gain
VRM10
VRM9
0.05
300
%
500
µA
COMP = FB ( See Note 2)
20
MHz
CCOMP = 10pF ( See Note 2)
77
dB
VID Inputs
Input Low Voltage
VIL(VID)
VRM10
VRM9
•
•
Input High Voltage
VIH(VID)
VRM10
VRM9
•
•
0.8
2.0
Input Current, VID Low
IIL(VID)
VID(X) = 0V
•
-30
Input Current, VID High
IIH(VID)
VID(X) = 1.15V
•
-2
2
µA
Pull-up Resistance
RVID
Internal
•
35
60
115
kΩ
Internal Pull-up Voltage
VRM10
VRM9
•
•
1.0
2.2
1.15
2.4
1.26
2.6
V
V
VID Transition Delay
Time2
VID Code Change to FB Change
•
400
ns
“No CPU” Detection
Turn-off Delay Time2
VID Code Change to 11111X to PWM
going low
•
400
ns
To select VRM9 table
To select VRM10 table (becomes VID5)
•
•
4
•
200
VID Table Select
Vtblsel
0.4
0.8
V
V
V
V
-20
µA
3.5
V
V
4000
kHz
Oscillator
Frequency
fOSC
Frequency Variation
fPHASE
TA = +25°C, RT = 250kΩ, 4-Phase
TA = +25°C, RT = 115kΩ, 4-Phase
TA = +25°C, RT = 75kΩ, 4-Phase
•
155
200
400
600
245
kHz
kHz
kHz
Output Voltage
VRT
RT = 100kΩ to GND
•
1.9
2.0
2.1
V
RAMPADJ Pin Accuracy
VRAMPADJ
VRAMPADJ = Vdac = +2K • (Vin–Vdac)/
(Rr+2k) @ 20µA
•
-50
+50
mV
RAMPADJ Input Current
IRAMPADJ
Current into RAMPADJ pin
0
100
µA
Offset Voltage
VOS(CSA)
CSSUM–CSREF, Test Circuit 1
•
-1.5
+1.5
mV
Input Bias Current
IBIAS(CSA)
•
-50
+50
nA
Gain Bandwidth Product
GBW
Current Sense Amplifier
COMP = FB ( See Note 2)
10
MHz
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. Guaranteed by design – NOT tested in production.
REV. 1.0.0 Jul/15/05
5
FAN5019B
PRODUCT SPECIFICATION
Electrical Specifications (continued)
(VCC = 12V, TA = 0°C to +85°C and FBRTN=GND, using circuit in Figure 1, unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter
Symbol
Conditions
Min.
DC Gain
( See Note 2)
Input Common Mode
Range
CSSUM and CSREF
•
0
COMP = FB, Test Circuit 2
•
-84
ICSCOMP = ±100µA
•
Positioning Accuracy
ΔVFB
Output Voltage Range
Output Current
IO(CSA)
Typ.
Max.
77
FB forced to VOUT – 3% Source/Sink
dB
-80
0.1
300
Units
3
V
-76
mV
3.3
375
V
µA
Current Balance Circuit
Input Operating Range
•
VSW(X)CM
-600
+200
mV
Input Resistance
RSW(X)
SW(X) = 0V
•
20
30
40
kΩ
Input Current
ISW(X)
SW(X) = 0V
•
-10
-7
-4
µA
Input Current Matching
ΔISW(X)
SW(X) = 0V
•
-5
+5
%
VILIMIT(NM)
VILIMIT(SD)
RILIMIT = 250kΩ
IILIMIT = -100µA
•
•
2.9
3.1
400
V
mV
IILIMIT(NM)
RILIMIT = 250kΩ
Current Limit Comparator
ILIMIT Output Voltage
Normal Mode
In Shutdown
Output Current, Normal
Mode
12
VIILIMIT = 3V
•
60
VCL
VCSREF–VCSCOMP, RILIMIT = 250kΩ
•
105
Latch-off Delay Threshold
VDELAY
In Current Limit
•
1.7
Latch-off Delay Time
tDELAY
RDELAY = 250kΩ, CDELAY = 4.7nF
Output Current,
Soft start Mode
IDELAY(SS)
During Start-up, DELAY < 2.8V
Soft Start Delay Time
TDELAY(SS)
RDELAY = 250kΩ, CDELAY = 4.7nF,
VID = 011111 (1.475V)
Maximum Output Current
Current Limit Threshold
Voltage
Current Limit Setting Ratio
3
VCL/IILIMIT
µA
µA
125
150
10.4
1.8
mV
mV/µA
1.9
600
V
µs
Soft Start
•
-25
-20
-15
400
µA
µs
Enable Input
Input Low Voltage
VIL(EN)
•
Input High Voltage
VIH(EN)
•
0.8
Input Current, EN Low
IIL(EN)
EN = 0V
•
-1
Input Current, EN High
IIH(EN)
EN = 1.25V
•
Under voltage Threshold
VPWRGD(UV)
Relative to DAC Output
•
Over voltage Threshold
VPWRGD(OV)
Relative to DAC Output
•
Output Low Voltage
VOL(PWRGD)
IPWRGD(SINK) = 4mA
•
0.4
V
V
1
µA
10
25
µA
-325
-250
-200
mV
90
150
200
mV
225
400
mV
Power Good Comparator
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. Guaranteed by design – NOT tested in production.
6
REV. 1.0.0 Jul/15/05
PRODUCT SPECIFICATION
FAN5019B
Electrical Specifications (continued)
(VCC = 12V, TA = 0°C to +85°C and FBRTN=GND, using circuit in Figure 1, unless otherwise noted.)
The • denotes specifications which apply over the full operating temperature range.
Parameter
Symbol
Conditions
1
100
VCROWBAR
Crowbar Reset Point
Crowbar Delay Time
VID Code Changing
VID Code Static
Typ.
Max.
Units
10
ms
µs
ns
•
Power Good Delay Time
Initial Start Up
VID Code Changing
VID Code Static
Crowbar Trip Point
Min.
250
200
Relative to Nominal DAC Output
•
90
150
200
mV
Relative to FBRTN
•
450
550
650
mV
Over voltage to PWM Going Low
•
100
250
400
500
600
µs
ns
160
500
mV
5
5.5
V
5
10
mA
6.9
7.8
V
tCROWBAR
PWM Outputs
Output Voltage Low
VOL(PWM)
IPWM(SINK) = 400µA
•
Output Voltage High
VOH(PWM)
IPWM(SOURCE) = 400µA
•
EN = Logic High
•
Vcc Rising (Vcc = 12V input)
•
6.5
•
0.7
•
5.6
4
Input Supply
DC Supply Current
UVLO Threshold
VUVLO
UVLO Hysteresis
UVLO Threshold
Falling
V
7.0
Notes:
1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control
2. Guaranteed by design – NOT tested in production.
REV. 1.0.0 Jul/15/05
7
FAN5019B
PRODUCT SPECIFICATION
Internal Block Diagram
VCC
RT
RAMPADJ
28
14
13
UVLO
Shutdown
& Bias
EN 11
2K
Oscillator
GND 19
CMP
SET
DAC
+150mV
EN
RESET
27 PWM1
RESET
26 PWM2
CMP
CSREF
CMP
DAC
-250mV
Phase
Current
Balancing
Circuit
2/3/4 Phase Driver
Logic
CMP
25 PWM3
RESET
CMP
CMP
24 PWM4
RESET
CROWBAR
CURRENT
LIMIT
23 SW1
22 SW2
PWRGD 10
Delay
21 SW3
20 SW4
ILIMIT 15
17 CSSUM
Current
Limit
Circuit
EN
16 CSREF
CSA
18 CSCOMP
DELAY 12
Soft
Start
COMP
8
Error
Amp
9
FB
+
-
Sel VRM9 Table
VID
DAC
3.75V
REF
7
FBRTN
8
1
2
3
VID4 VID3 VID2
4
5
6
VID1 VID0 VID5
REV. 1.0.0 Jul/15/05
PRODUCT SPECIFICATION
FAN5019B
4
5.3
3.5
5.2
SUPPLY CURRENT (mA)
MASTER CLOCK FREQUENCY (MHz)
Typical Characteristics
3
2.5
2
1.5
1
TA = 25 C
4-Phase Operation
5.1
5.0
4.9
4.8
4.7
0.5
0
4.6
100
0
200
300
400
0
0.5
RESISTOR’S RT VALUE (kΩ)
TPC 1. Master Clock Frequency
1.0
1.5
2.0
2.5
3.0
3.5
4.0
MASTER CLOCK FREQUENCY (MHz)
TPC 2. Supply Current vs. Master Clock Frequency
Test Circuits
28
+12V
18
39kΩ
100nF
VCC
FAN5019B
CSCOMP
VID4
CSA
17 CSSUM
VID3
1kΩ
16 CSREF
1V
19
VID2
GND
VOS
CSCOMP–1V
=
40
VID1
VID0
VID5
Test Circuit 1. Current Sense Amplifier VOS
28 VCC
+12V
200kΩ
200kΩ
3 VID2
PWM2 26
4 VID1
PWM3 25
5 VID0
PWM4 24
6 VID5
SW1 23
7 FBRTN
SW2 22
8 FB
SW3 21
9 COMP
SW4 20
10 PWRGD
GND 19
12 DELAY
CSSUM 17
13 RT
CSREF 16
16
1μF
CSCOMP 18
20kΩ
CSA
CSSUM
4.7nF
100nF
250kΩ
CSREF
14 RAMPADJ ILIMIT 15
GND
ΔVFB = FB − VVID
Test Circuit 2. Voltage Positioning
REV. 1.0.0 Jul/15/05
PWM1 27
18 CSCOMP
19
1V
2 VID3
11 EN
17
+12V
100nF
9 COMP
100nF
80mV
VCC 28
1kΩ
8 FB
10kΩ
1 VID4
250kΩ
Test Circuit 3. Closed Loop Output Voltage Accuracy
9
10
RDLY
CDLY
R5
RT
RR
ILIMIT 15
PWM3 25
PWM2 26
CSSUM 17
SW4 20
SW3 21
SW2 22
SW1 23
7 FBRTN
19 GND
13 RT
FB 8
COMP 9
CSREF 16
12 DELAY CSCOMP 18
5 VID0
4 VID1
3 VID2
2 VID3
1 VID4
6 VID5/SEL PWM4 24
11 EN
10 PWRGD
14 RAMPADJ PWM1 27
28 VCC
U4 FAN5019B
CFB
CCS
RA
RPH3
RSW3
RLIM
RB
RCS2
RB1
RPH1
CB
CA
RTH*
RCS1
RPH2
RSW2
RSW1
L4
C6
+12V
C5
+12V
C4
+12V
LDRV
HDRV
LDRV
SW
2
PWM
LDRV
SW
OD
3
HDRV
PGND BOOT
VCC
U3 FAN5009
PWM
OD
PGND BOOT
VCC
U2 FAN5009
PWM
6
4
2
3
6
4
2
SW
OD
3
HDRV
PGND BOOT
VCC
6
4
U1 FAN5009
5
7
1
8
5
7
1
8
5
7
1
8
C10
C9
C8
Q8
Q3
Q6
Q2
Q4
Q1
VIN
VIN
C3
C2
C1
Q9
Q7
Q5
L2
R21
C14
L3
R20
C13
R19
C12
L1
VIN
CIN
CX
CZ
Vcc CORE
0.8375V - 1.600V
74A DC, 93A Peak
Figure 1. Typical Application – 3-phase, 65A (DC), 74A (Peak) VRD/VRM10 Design
Note:
The design shown in this datasheet should be used as a reference only. Please contact your Fairchild sales representative for the latest information.
EN
PWRGD
C7
R1
+12V
FAN5019B
PRODUCT SPECIFICATION
Application Circuit
REV. 1.0.0 Jul/15/05
PRODUCT SPECIFICATION
FAN5019B
Bill of Materials
Table 1. FAN5019B VRM/VRD10 Application Bill of Materials for Figure 1
Ref
Qty
Description
Manufacturer/Number
U4
1
VR10, Multi-Phase Controller
Fairchild FAN5019B
U1–3
3
Sync MOSFET Driver, 12V/12V
Fairchild FAN5009
Q1–3
3
N-MOSFET, 30V, 50A, 8mΩ
Fairchild FDD6696
Q4–9
6
N-MOSFET, 30V, 75A, 5mΩ
Fairchild FDD6682
L1–3
3
Inductor, 650nH, 26A, 1.6mΩ
Micrometals T50-8B/90, 5T, 16AWG
L4
1
Inductor, 630nH, 15A, 1.7mΩ
Inter-Technical AK1418160052A-R63M
R1
1
10Ω, 5%
RR RDLY, RT
3
301kΩ, 1%
R5
1
15.0kΩ, 1%
RPH1–3
3
100kΩ, 1%
RA, RCS2
2
24.9kΩ, 1%
RB1
1
10Ω, 1%
RB
1
1.33kΩ, 1%
RSW1–3
3
0Ω, 5%
RCS1
1
37.4kΩ, 1%
RLIM
1
200kΩ, 1%
R19–21
3
1.5Ω, 5%
RTH
1
NTC Thermistor, 100kΩ, 5%
C1–7
7
1.0µF, 25V, 10% X7R
C8–10
3
0.1µF, 50V, 10% X7R
C12–14, CCS
4
4700pF, 25V, 10% X7R
CDLY
1
0.047µF, 25V, 10% X7R
CB
1
2200pF, 25V, 10% X7R
CA
1
470pF, 50V, 10% X7R
CFB
1
100pF, 50V, 5% NPO
CX
8
820µF, 2.5V, 20% 7mΩ, POLY
CZ
22
10µF, 6.3V, 20% X5R
CIN
6
470µF, 16V, 20%, 36mΩ, Alum-Elec
Panasonic ERT-J1V V104J
Fujitsu FP-2R5RE821M
Rubycon 16MBZ470M
Note:
The design shown in this datasheet should be used as a reference only. Please contact your Fairchild sales representative
for the latest information.
REV. 1.0.0 Jul/15/05
11
FAN5019B
PRODUCT SPECIFICATION
Table 2. VRM10 VID Codes
12
VID4
VID3
VID2
VID1
VID0
VID5
VOUT (nominal)
1
1
1
1
1
X
No CPU
0
1
0
1
0
0
0.8375 V
0
1
0
0
1
1
0.8500 V
0
1
0
0
1
0
0.8625 V
0
1
0
0
0
1
0.8750 V
0
1
0
0
0
0
0.8875 V
0
0
1
1
1
1
0.9000 V
0
0
1
1
1
0
0.9125 V
0
0
1
1
0
1
0.9250 V
0
0
1
1
0
0
0.9375 V
0
0
1
0
1
1
0.9500 V
0
0
1
0
1
0
0.9625 V
0
0
1
0
0
1
0.9750 V
0
0
1
0
0
0
0.9875 V
0
0
0
1
1
1
1.0000 V
0
0
0
1
1
0
1.0125 V
0
0
0
1
0
1
1.0250 V
0
0
0
1
0
0
1.0375 V
0
0
0
0
1
1
1.0500 V
0
0
0
0
1
0
1.0625 V
0
0
0
0
0
1
1.0750 V
0
0
0
0
0
0
1.0875 V
1
1
1
1
0
1
1.1000 V
1
1
1
1
0
0
1.1125 V
1
1
1
0
1
1
1.1250 V
1
1
1
0
1
0
1.1375 V
1
1
1
0
0
1
1.1500 V
1
1
1
0
0
0
1.1625 V
1
1
0
1
1
1
1.1750 V
1
1
0
1
1
0
1.1875 V
1
1
0
1
0
1
1.2000 V
1
1
0
1
0
0
1.2125 V
1
1
0
0
1
1
1.2250 V
1
1
0
0
1
0
1.2375 V
1
1
0
0
0
1
1.2500 V
1
1
0
0
0
0
1.2625 V
1
0
1
1
1
1
1.2750 V
1
0
1
1
1
0
1.2875 V
1
0
1
1
0
1
1.3000 V
1
0
1
1
0
0
1.3125 V
1
0
1
0
1
1
1.3250 V
REV. 1.0.0 Jul/15/05
PRODUCT SPECIFICATION
FAN5019B
Table 2. VRM10 VID Codes (continued)
VID4
VID3
VID2
VID1
VID0
VID5
VOUT (nominal)
1
0
1
0
1
0
1.3375 V
1
0
1
0
0
1
1.3500 V
1
0
1
0
0
0
1.3625 V
1
0
0
1
1
1
1.3750 V
1
0
0
1
1
0
1.3875 V
1
0
0
1
0
1
1.4000 V
1
0
0
1
0
0
1.4125 V
1
0
0
0
1
1
1.4250 V
1
0
0
0
1
0
1.4375 V
1
0
0
0
0
1
1.4500 V
1
0
0
0
0
0
1.4625 V
0
1
1
1
1
1
1.4750 V
0
1
1
1
1
0
1.4875 V
0
1
1
1
0
1
1.5000 V
0
1
1
1
0
0
1.5125 V
0
1
1
0
1
1
1.5250 V
0
1
1
0
1
0
1.5375 V
0
1
1
0
0
1
1.5500 V
0
1
1
0
0
0
1.5625 V
0
1
0
1
1
1
1.5750 V
0
1
0
1
1
0
1.5875 V
0
1
0
1
0
1
1.6000 V
REV. 1.0.0 Jul/15/05
13
FAN5019B
PRODUCT SPECIFICATION
Table 3. VRM9 VID Codes
14
VID4
VID3
VID2
VID1
VID0
VOUT (nominal)
1
1
1
1
1
No CPU
1
1
1
1
0
1.100 V
1
1
1
0
1
1.125 V
1
1
1
0
0
1.150 V
1
1
0
1
1
1.175 V
1
1
0
1
0
1.200 V
1
1
0
0
1
1.225 V
1
1
0
0
0
1.250 V
1
0
1
1
1
1.275 V
1
0
1
1
0
1.300 V
1
0
1
0
1
1.325 V
1
0
1
0
0
1.350 V
1
0
0
1
1
1.375 V
1
0
0
1
0
1.400 V
1
0
0
0
1
1.425 V
1
0
0
0
0
1.450 V
0
1
1
1
1
1.475 V
0
1
1
1
0
1.500 V
0
1
1
0
1
1.525 V
0
1
1
0
0
1.550 V
0
1
0
1
1
1.575 V
0
1
0
1
0
1.600 V
0
1
0
0
1
1.625V
0
1
0
0
0
1.650V
0
0
1
1
1
1.675V
0
0
1
1
0
1.700V
0
0
1
0
1
1.725V
0
0
1
0
0
1.750V
0
0
0
1
1
1.775V
0
0
0
1
0
1.800V
0
0
0
0
1
1.825V
0
0
0
0
0
1.850V
REV. 1.0.0 Jul/15/05
PRODUCT SPECIFICATION
FAN5019B
General Description
Note: The information in this section is intended to assist
users in their design and understanding of the FAN5019B
functionality. For clarity and ease of understanding, device
parameters have been included in the text. In the event there
are discrepancies between values stated in this section and
the actual specification tables, the specification tables shall
be deemed correct.
Theory of Operation
The FAN5019B combines a multi-mode, fixed-frequency
PWM control with multi-phase logic outputs for use in 2, 3
and 4 phase synchronous buck CPU core supply power converters. If VID5 is pulled up to a voltage greater than
VTBLSEL, then the DAC code corresponds to VRM9.
Multi-phase operation is important for producing the high
currents and low voltages demanded by today’s microprocessors. Handling the high currents in a single-phase converter would place high thermal demands on the components
in the system, such as the inductors and MOSFETs. The
internal 6-bit VID DAC conforms to Intel’s VRD/VRM 10
specifications.
The multi-mode control of the FAN5019B ensures a stable,
high-performance topology for:
• Balancing currents and thermals between phases
• High speed response at the lowest possible switching
frequency and output decoupling
• Minimizing thermal switching losses due to lower
frequency operation
• Tight load line regulation and accuracy
• High current output from having up to 4 phase operation
• Reducing output ripple due to multi-phase cancellation
• PC board layout noise immunity
• Ease of use and design due to independent component
selection
• Flexibility in operation for tailoring design to low cost or
high performance
Number of Phases
The number of operational phases and their phase relationship is determined by internal circuitry which monitors the
PWM outputs. Normally, the FAN5019B operates as a 4phase PWM controller. Grounding the PWM4 pin programs
a 3-phase operation; grounding the PWM3 and PWM4 pins
programs a 2-phase operation.
When the FAN5019B is initially enabled, the controller outputs a voltage on PWM3 and PWM4 of approximately
550mV. An internal comparator checks each pin’s voltage
versus a threshold of 400mV. If the pin is grounded, then it
will be below the threshold and the phase will be disabled.
The output impedance of the PWM pin is approximately
5kΩ. Any external pull-down resistance connected to the
PWM pin should not be less than 25kΩ to ensure proper
operation. The phase detection is made prior to starting norREV. 1.0.0 Jul/15/05
mal operation. After this time, if the PWM output was not
grounded, then it will operate normally. If the PWM output
was grounded, then it will remain off.
The PWM outputs become logic-level output devices once
normal operation starts, and are intended for driving external
gate drivers. Since each phase is monitored independently,
operation approaching 100% duty cycle is possible. Also,
more than one output can be on at a time for overlapping
phases.
Master Clock Frequency
The clock frequency of the FAN5019B is set with an external resistor connected from the RT pin to ground. The frequency follows the graph shown in TPC 1. To determine the
frequency per phase, the clock is divided by the number of
phases in use. If PWM4 is grounded, then divide the master
clock by 3 and if both PWM3 and 4 are grounded, then
divide by 2. If all phases are in use, divide by 4.
Output Voltage Differential Sensing
The FAN5019B provides a high accuracy VID DAC and
error-amplifier to maintain a ±10 mV output setpoint tolerance over temperature. Output voltage is differentially
sensed between the FB and FBRTN pins. FB should be connected through a resistor to the regulation point, usually the
remote sense pin of the microprocessor. FBRTN should be
connected directly to the remote sense ground point. The
internal VID DAC and precision reference are referenced to
FBRTN, which has a typical current of 150µA, to allow
accurate remote sensing. The internal error amplifier compares the output of the DAC to the FB pin to regulate the output voltage.
Output Current Sensing
The FAN5019B provides a dedicated current sense amplifier
(CSA) to monitor the total output current for proper voltage
positioning versus load current and for current limit detection. Sensing the load current at the output gives the total
average current being delivered to the load, which is an
inherently more accurate method than peak current detection
or sampling the current across a sense element such as the
low side MOSFET. There are several ways of configuring
this amplifier depending on the objectives of the system:
• Output inductor DCR sensing without thermistor for
lowest cost
• Output inductor DCR sensing with thermistor for
improved accuracy with tracking of inductor temperature
• Sense resistors for highest accuracy measurements
The positive input of the CSA is connected to the CSREF
pin, which is connected to the output voltage. The inputs to
the amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback
resistor between CSCOMP and CSSUM sets the gain of the
15
FAN5019B
amplifier, and a filter capacitor is placed in parallel with this
resistor. The amplifier’s gain is programmable by adjusting
the feedback resistor to set the load line required by the
microprocessor. The current information is then given as the
difference of CSREF –CSCOMP. This difference signal is
used internally to offset the VID DAC for voltage positioning and as a differential input for the current limit comparator.
To provide the best accuracy for the current sensing, the
CSA is designed to have a low offset input voltage. Also,
external resistors determine the sensing gain so that it can be
made extremely accurate and flexible.
Active Impedance Control Mode
For controlling the output voltage droop as a function of
output current, the current sense amplifier (CSA) creates a
voltage signal proportional to the total inductor currents.
External components determine the ratio of this voltage to
the output current to allow it to be adjusted to set the
required load line. Inside the chip the CSA output voltage is
subtracted from the DAC voltage which then is used for the
reference to the error amplifier. As the output current
increases the reference to the error amp decreases causing
the output voltage to decrease accordingly.
Current Control Mode and Thermal Balance
The FAN5019B has individual inputs for each phase which
are used for monitoring the current in each phase. This information is combined with an internal ramp to create a current
balancing feedback system that is optimized for initial current balance accuracy and dynamic thermal balancing during
operation. This current balance information is independent
of the average output current information used for positioning described previously.
The magnitude of the internal ramp can be set to optimize
the transient response of the system. It also monitors the supply voltage for feed-forward control for changes in the supply. A resistor connected from the power input voltage to the
RAMPADJ pin determines the slope of the internal PWM
ramp. Detailed information about programming the ramp is
given in the Application Information section.
External resistors can be placed in series with individual
phases to create an intentional current imbalance if desired,
such as when one phase may have better cooling and can
support higher currents. Resistors RSW1 through RSW4
(see the typical application circuit in Figure 4) can be used
for adjusting FET thermal and current balance. Zero ohm
placeholder resistors should be provided in the initial layout
to allow the phase balance to be adjusted during design fine
tuning.
To increase the current in any given phase, make RSW for
that phase larger (make RSW = 0 for the hottest phase and do
16
PRODUCT SPECIFICATION
not change during balancing). Increasing RSW to only 500Ω
will substantially increase the phase current. Increase each
RSW value by small amounts to achieve balance,
starting with the coolest phase first.
Voltage Control Mode
The voltage-mode control loop uses a high gain-bandwidth
voltage mode error amplifier. The control input voltage to
the positive input is set via the VID 6-bit logic code, according to the voltages listed in Table 1. This voltage is also offset by the droop voltage for active positioning of the output
voltage as a function of current, commonly known as active
voltage positioning. The output of the amplifier is the COMP
pin, which sets the termination voltage for the internal PWM
ramps.
The negative input (FB) is tied to the output sense location
with a resistor RB and is used for sensing and controlling the
output voltage at this point. A current source from the FB pin
flowing through RB is used for setting the no-load offset
voltage from the VID voltage. The no-load voltage will be
negative with respect to the VID DAC. The main loop compensation is incorporated in the feedback network between
FB and COMP.
Soft-Start
The power-on ramp up time of the output voltage is set with
a capacitor and resistor in parallel from the DELAY pin to
ground. The RC time constant also determines the current
limit latch off time as explained in the following section. In
UVLO or when EN is a logic low, the DELAY pin is held at
ground. After the UVLO threshold is reached and EN is a
logic high, the DELAY cap is charged up with an internal
20µA current source. The output voltage follows the ramping voltage on the DELAY pin, limiting the inrush current.
The soft-start time depends on the value of VID DAC and
CDLY, with a secondary effect from RDLY. Refer to the Application Information section for detailed information on setting CDLY.
If EN is taken low or VCC drops below UVLO, the DELAY
cap is reset to ground to be ready for another soft start cycle.
Figure 1 shows a typical start-up sequence for the
FAN5019B.
Over Current Limit and Latch-off Protection
The FAN5019B compares a programmable current limit set
point to the voltage from the output of the current sense
amplifier. The level of current limit is set with the resistor
from the ILIMIT pin to ground. During normal operation,
the voltage on ILIMIT is 3V. The current through the external resistor is internally scaled to give a current limit threshold of approximately 10.4mV/µA. If the difference in
voltage between CSREF and CSCOMP rises above the current limit threshold, the internal current limit amplifier will
control the internal COMP voltage to maintain the average
output current at the limit.
REV. 1.0.0 Jul/15/05
PRODUCT SPECIFICATION
Figure 2. Start-Up Waveforms
FAN5019B
Figure 3. Overcurent Latch Off Waveform
Circuit of Figure 5Circuit of Figure 5
Channel 1 – Vout, Channel 2 – VccChannel 1 – Vcc, Channel 2 – Vout
Channel 3 – OD, Channel 4 – Delay pinChannel 3 – OD, Channel 4 – Delay pin
After the limit is reached, the 3V pull-up on the DELAY pin
is disconnected, and the external delay capacitor is discharged through the external resistor. A comparator monitors
the DELAY voltage and shuts off the controller when the
voltage drops below 1.8V. Therefore, the RC time constant
discharging from 3V to 1.8V sets the current limit latch off
delay time. The Application Information section discusses
the selection of CDLY and RDLY.
Because the controller continues to cycle the phases during
the latch-off delay time, if the short is removed before the
1.8V threshold is reached, the controller will return to normal operation. The recovery characteristic depends on the
state of PWRGD. If the output voltage is within the PWRGD
window, the controller resumes normal operation. However,
if a short circuit has caused the output voltage to drop below
the PWRGD threshold, then a soft-start cycle is initiated.
The latch-off function can be reset by either cycling VCC to
the FAN5019B, or by cycling the Enable pin low for a short
time. To disable the short circuit latch off function, the
external resistor to ground should be left open, and a 1MΩ
resistor should be connected from VCC to the DELAY pin.
This prevents the DELAY capacitor from discharging, so the
1.8V threshold is never reached. The resistor will have an
impact on the soft-start time because the current through it
will add to the internal 20µA current source.
Dynamic VID
The FAN5019B incorporates the ability to dynamically
change the VID input while the controller is running. This
allows the output voltage to change while the supply is running and supplying current to the load. This is commonly
referred to as VID-on-the-fly (OTF). A VID-OTF can occur
under either light load or heavy load conditions. The processor signals the controller by changing the VID inputs in multiple steps from the start code to the finish code. This change
can be either positive or negative.
When a VID input changes state, the FAN5019B detects the
change and ignores the DAC inputs for a minimum of 400ns.
This time is to prevent a false code due to logic skew while
the six VID inputs are changing. Additionally, the first VID
change initiates the PWRGD and CROWBAR blanking
functions for a minimum of 250µs to prevent a false
PWRGD or CROWBAR event. Each VID change will reset
the internal timer. Figure 4 shows the VID on-the-fly performance when the output voltage is stepping up and the output
current is switching between minimum and maximum values
which is the worst-case situation.
During start-up when the output voltage is below 200mV, a
secondary current limit is active. This is necessary because
the voltage swing of CSCOMP cannot go below ground.
This secondary current limit controls the internal COMP
voltage to the PWM comparators to 2V. This will limit the
voltage drop across the low-side MOSFETs through the
current balance circuitry.
There is also an inherent per phase current limit that will protect individual phases if one or more phases stops functioning because of a faulty component. This limit is based on the
maximum normal-mode COMP voltage.
REV. 1.0.0 Jul/15/05
Figure 4. VID On-the-Fly Waveforms, Circuit of Figure 5,
VID Change = 5mV, 5µs, 50 steps, IOUT Change = 5A to 65A
17
FAN5019B
Power Good Monitoring
The Power Good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open drain output
whose high level (when connected to a pull-up resistor) indicates that the output voltage is within the nominal limits
specified in the specifications table based on the VID voltage
setting. PWRGD will go low if the output voltage is outside
of this specified range. PWRGD is blanked during a VID
OTF event for a period of 250µs to prevent false signals during the time the output is changing.
Output Crowbar
As part of the protection for the load and output components
of the supply, the PWM outputs will be driven low (turning
on the low-side MOSFETs) when the output voltage exceeds
the upper Power Good threshold. This crowbar action will
stop once the output voltage has fallen below the release
threshold of approximately 550mV.
Turning on the low-side MOSFETs pulls down the output
voltage as the reverse current builds up in the inductors.
If the output overvoltage is due to a short of the high-side
MOSFET, this action will current limit the input supply
or blow its fuse, protecting the microprocessor from
destruction.
Output Enable and UVLO
The input supply (VCC) to the controller must be higher than
the UVLO threshold and the EN pin must be higher then its
logic threshold for the FAN5019B to begin switching. If
UVLO is less than the threshold or the EN pin is a logic low,
the FAN5019B is disabled. This holds the PWM outputs at
ground, shorts the DELAY capacitor to ground, and holds
the ILIMIT pin at ground.
In the application circuit, the ILIMIT pin should be connected to the output disable pins of the FAN5009 drivers.
Because ILIMIT is grounded, this disables the drivers such
that both DRVH and DRVL are grounded. This feature is
important to prevent discharging of the output capacitors
when the controller is shut off. If the driver outputs were not
disabled, then a negative voltage could be generated on the
output due to the high current discharge of the output
capacitors through the inductors.
18
PRODUCT SPECIFICATION
Application Information
The design parameters for a typical Intel VRD10.x-compliant CPU application are as follows:
•
•
•
•
•
•
•
•
•
•
•
Input voltage (VIN) = 12V
VID setting voltage (VVID) = 1.500V
Duty cycle (D) = 0.125
Nominal output voltage at no load (VONL) = 1.480V
Nominal output voltage at 65A load (VOFL) = 1.3955V
Static output voltage drop based on a 1.3 mΩ load line
(RO) from no load to full load
(VD) = VONL – VOFL = 1.480V – 1.3955V = 84.5mV
Maximum output current (IO) = 65A
Maximum output current step (ΔIO) = 60A
Number of phases (n) = 3
Switching frequency per phase (fSW) = 228 kHz
Setting the Clock Frequency
The FAN5019B uses a fixed-frequency control architecture
with the frequency being set by an external timing resistor
(RT). The clock frequency and the number of phases determine the switching frequency per phase, which relates
directly to switching losses and the sizes of the inductors and
input and output capacitors. With n = 3 for three phases, a
clock frequency of 684kHz sets the switching frequency of
each phase, fSW, to 228kHz, which represents a practical
trade-off between the switching losses and the sizes of the
output filter components. TPC 1 shows that to achieve a
684kHz oscillator frequency, the correct value for RT is
301kΩ. Alternatively, the value for RT can be calculated
using:
RT =
(n × f SW
1
× 5 pF ) − 110nS
(1)
where 5.0pF and 110nS are internal IC component values.
For good initial accuracy and frequency stability, it is recommended to use a 1% resistor.
Soft-Start and Current Limit Latch-Off Delay
Times
Because the soft-start and current limit latch off delay
functions share the DELAY pin, these two parameters must
be considered together. The first step is to set CDLY for the
soft-start ramp. This ramp is generated with a 20µA internal
current source. The value of RDLY will have a second order
impact on the soft-start time because it sinks part of the current source to ground. However, as long as RDLY is kept
greater than 200kΩ, this effect is minor. The value for CDLY
can be approximated using:
REV. 1.0.0 Jul/15/05
PRODUCT SPECIFICATION
⎧
VVID ⎫ t SS
= ⎨20μA −
⎬×
RDLY ⎭ VVID
2
×
⎩
C DLY
FAN5019B
(2)
where tSS is the desired soft-start time. Assuming an RDLY of
301kΩ and a desired a soft-start time of 3ms, CDLY is 35nF.
A close standard value for CDLY is 47nF. Once CDLY has
been chosen, RDLY can be calculated for the current limit
latch-off time using:
RDLY =
1.96 × t DELAY
C DLY
(3)
If the result for RDLY is less than 200kΩ, then a smaller softstart time should be considered by recalculating the equation
for CDLY or a longer latch-off time should be used. RDLY
should never be less than 200kΩ. In this example, a delay
time of 8ms gives RDLY = 334kΩ. A close
standard 1% value is 301kΩ.
Inductor Selection
The choice of inductance value for the inductor determines
the ripple current in the inductor. Less inductance leads to
more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs, but allows the
use of smaller-size inductors and, for a specified peak-topeak transient deviation, less total output capacitance. Conversely, a higher inductance means lower ripple current and
reduced conduction losses, but requires larger inductors and
more output capacitance for the same peak-to-peak transient
deviation. In any multi-phase converter, a practical value for
the peak-to-peak inductor ripple current is less than 50% of
the maximum DC current in the same inductor. Equation 4
shows the relationship between the inductance, oscillator
frequency, and peak-to-peak ripple current in the inductor.
Equation 5 can be used to determine the minimum inductance based on a given output ripple voltage:
IR =
VO × (1 − D )
f SW × L
(4)
L ≥
VVID × RO × (1 − (n × D ))
f SW × VRIPPLE
(5)
Solving Equation 5 for a 10 mVp-p output ripple voltage
yields:
L ≥
1.5V × 1.3m Ω × (1 − 0.375 )
= 534 nH
228 kHz × 10 mV
The smallest possible inductor should be used to minimize
the number of output capacitors. Choosing a 650nH inductor
is a good choice for a starting point and gives a calculated
ripple current of 8.86A. The inductor should not saturate at
the peak current of 26.1A and should be able to handle the
sum of the power dissipation caused by the average current
of 21.7A in the winding and core loss.
Another important factor in the inductor design is the DC
Resistance (DCR), which is used for measuring the phase
currents. A large DCR will cause excessive power losses,
while too small a value will lead to increased measurement
error. A good rule of thumb is to have the DCR be about
1 to 1 1/2 times the droop resistance (RO). For our example,
we are using an inductor with a DCR of 1.6 mΩ.
Designing an Inductor
Once the inductance and Direct-Current resistance (DCR)
are known, the next step is either to design an inductor or
find a standard inductor that comes as close as possible to
meeting the overall design goals. It is also important to have
the inductance and DCR tolerance specified to keep the
accuracy of the system controlled. Using 15% for the inductance and 8% for the DCR (at room temperature) are reasonable tolerances that most manufacturers can meet.
The first decision in designing the inductor is to choose the
core material. There are several possibilities for providing
low core loss at high frequencies. Two examples are the
powder cores (e.g., Kool-Mm® from Magnetics, Inc. or
Micrometals) and the gapped soft ferrite cores (e.g., 3F3
or 3F4 from Philips). Low-frequency powdered iron cores
should be avoided due to their high core loss, especially
when the inductor value is relatively low and the ripple
current is high.
The best choice for a core geometry is a closed-loop type,
such as pot cores, PQ, U, and E cores, or toroids. A good
compromise between price and performance are cores with a
toroidal shape.
There are many useful references for quickly designing a
power inductor, such as:
Magnetics Design References
1. Magnetic Designer Software: Intusoft
(www.intusoft.com)
2.
Designing Magnetic Components for High-Frequency
DC-DC Converters, by William T. McLyman,
Kg Magnetics, Inc. ISBN 1883107008
If the ripple voltage ends up less than that designed for, the
inductor can be made smaller until the ripple value is met.
This will allow optimal transient response and minimum
output decoupling.
REV. 1.0.0 Jul/15/05
19
FAN5019B
PRODUCT SPECIFICATION
Selecting a Standard Inductor
The companies listed below can provide design consultation
and deliver power inductors optimized for high power
applications upon request.
Power Inductor Manufacturers
• Coilcraft
(847)639-6400
www.coilcraft.com
It is best to have a dual location for CCS in the layout so standard values can be used in parallel to get as close to the value
desired. For this example, choosing CCS to be 4.7nF is a
good choice. For best accuracy, CCS should be a 5% or 10%
NPO capacitor. A close standard 1% value for RPH(X) is
100kΩ.
Inductor DCR Temperature Correction
With the inductor’s DCR being used as the sense element,
and copper wire being the source of the DCR, one needs to
compensate for temperature changes of the inductor’s winding. Fortunately, copper has a well-known temperature coefficient (TC) of 0.39%/°C.
• Coiltronics
(561)752-5000
www.coiltronics.com
• Sumida Electric Company
(510) 668-0660
www.sumida.com
If RCS is designed to have an opposite and equal percentage
change in resistance to that of the wire, it will cancel the
temperature variation of the inductor’s DCR. Due to the nonlinear nature of NTC thermistors, resistors RCS1 and RCS2
are needed (see Figure 5) to linearize the NTC and produce
the desired temperature tracking.
• Vishay Intertechnology
(402) 563-6866
www.vishay.com
To VOUT
sense
Output Droop Resistance
RTH
The design requires that the regulator output voltage
measured at the CPU pins drops when the output current
increases. The specified voltage drop corresponds to a DC
output resistance (RO).
The output current is measured by summing together the
voltage across each inductor and then passing the signal
through a low-pass filter. This summer-filter is the CS
amplifier configured with resistors RPH(X) (summers), and
RCS and CCS (filter). The output resistance of the regulator is
set by the following equations, where RL is the DCR of the
output inductors:
RO =
RCS
× RL
RPH ( X )
CCS =
L
RL × RCS
RPH ( X )
RPH3
650nH
= 4.06nF
1.6 mΩ × 100kΩ
RCS2
CCS
1.8nF
17
16
CSCOMP
CSSUM
CSA
CSREF
Figure 5. Temperature Compensation Circuit
The following procedure and expressions will yield values to
use for RCS1, RCS2, and RTH (the thermistor value at 25°C)
for a given RCS value.
1.
Select an NTC to be used based on type and value. Since
we do not have a value yet, start with a thermistor with a
value close to RCS. The NTC should also have an initial
tolerance of better than 5%.
2.
Based on the type of NTC, find its relative resistance
value at two temperatures. The temperatures to use that
work well are 50°C and 90°C. We will call these resistance values A (RTH(50°C))/RTH(25°C)) and B (RTH(90°C)/
RTH(25°C)). Note that the NTC’s relative value is always
1 at 25°C.
3.
Next, find the relative value of RCS required for each of
these temperatures. This is based on the percentage
change needed, which we will initially make 0.39%/°C.
We will call these r1 and r2 where:
(7)
r1 =
1
(1 + TC × (T1 − 25))
1
r2 =
(1 + TC × (T2 − 25))
20
RCS1
18
Next, use Equation 7 to solve for CCS:
CCS =
RPH1
Keep this path as
short as possible
and well away from
Switch Node lines
RL
× RCS
RO
1.6mΩ
=
× 100 kΩ = 123kΩ
1.3mΩ
RPH2
Place as close as
possible to nearest
inductor or low-side
MOSFET
(6)
One has the flexibility of choosing either RCS or RPH(X).
It is best to select RCS equal to 100kΩ, and then solve for
RPH(X) by rearranging Equation 6.
RPH ( X ) =
To Switch Nodes
TC = 0.0039
T1 = 50°C
T2 = 90°C
REV. 1.0.0 Jul/15/05
PRODUCT SPECIFICATION
4.
Compute the relative values for RCS1, RCS2, and RTH
using:
rCS2 =
rCS 1 =
rTH =
5.
( A − B) × r1 × r2 − A × (1− B) × r2 + B × (1− A) × r1
A × (1− B) × r1 − B × (1 − A) × r2 − ( A − B)
(1 − A)
1
A
−
1 − rCS 2 r1 − rCS 2
(8)
1
1
1 − rCS
−
2
1
rCS 1
Calculate RTH = rTH x RCS, then select the closest value
of thermistor available. Also compute a scaling factor k
based on the ratio of the actual thermistor value used
relative to the computed one:
k=
6.
FAN5019B
RTH ( ACTUAL )
(9)
RTH ( CALCULATED )
Finally, calculate values for RCS1 and RCS2 using the
following:
RCS 1 = RCS × k × rCS 1
(10)
RCS 2 = RCS × ((1 − k ) + (k × rCS 2 ))
Output Offset
Intel’s specification requires that at no load the nominal output voltage of the regulator be offset to a lower value than
the nominal voltage corresponding to the VID code. The offset is set by a constant current source flowing out of the FB
pin (IFB) and flowing through RB. The value of RB can be
found using Equation 11:
VVID − VONL
I FB
RB =
1.5V − 1.480V
= 1.33kΩ
15μA
The first step is to select the total amount of ceramic capacitance. This is based on the number and type of capacitor to
be used. The best location for ceramics is inside the socket,
with 12 to 18 of size 1206 being the physical limit. Others
can be placed along the outer edge of the socket as well.
Combined ceramic values of 200µF–300µF are recommended, usually made up of multiple 10µF or 22µF
capacitors. Select the number of ceramics and find the total
ceramic capacitance (CZ).
Next, there is an upper limit imposed on the total amount of
bulk capacitance (CX) when one considers the VID on-thefly voltage stepping of the output (voltage step VV in time tV
with error VERR) and a lower limit based on meeting the critical capacitance for load release for a given maximum load
step ΔIO:
⎞
⎛ L × ΔIO
− CZ ⎟⎟
CX ( MIN ) ≥ ⎜⎜
⎝ n × RO ×VVID
⎠
CX ( MAX ) ≤
For this example, RCS has been chosen to be 100kΩ, so we
start with a thermistor value of 100kΩ. Looking through
available 0603 size thermistors, we find a Panasonic
ERT-J1VV104J NTC thermistor with A = 0.2954 and
B = 0.05684. From these we compute RCS1 = 0.3304,
RCS2 = 0.7426 and RTH = 1.165. Solving for RTH yields
116.5 kΩ, so we choose 100kΩ, making k = 0.8585. Finally,
we find RCS1 and RCS2 to be 28.4kΩ and 77.9kΩ. Choosing
the closest 1% resistor values yields a choice of 35.7kΩ and
73.2kΩ.
RB =
COUT Selection
The required output decoupling for the regulator is typically
recommended by Intel for various processors and platforms.
There are also some simple design guidelines to determine
what is required. These guidelines are based on having both
bulk and ceramic capacitors in the system.
2
⎛
⎞
⎛ VVID nKRO ⎞
L
VV
⎜
⎟
⎜
⎟
−
×
×
1
+
×
1
t
⎜V V
⎟⎟ − CZ
nK 2 RO2 VVID ⎜⎜
L ⎟⎠
⎝
V
⎝
⎠
(12)
(13)
where
⎞
⎛V
K = − ln ⎜⎜ VERR ⎟⎟
⎝ VV ⎠
To meet the conditions of these expressions and transient
response, the ESR of the bulk capacitor bank (RX) should be
less than two times the droop resistance, RO. If the CX(MIN)
is larger than CX(MAX), the system will not meet the VID
on-the-fly specification and may require the use of a smaller
inductor or more phases (and may have to increase the
switching frequency to keep the output ripple the same).
For our example, 22 10µF 1206 MLC capacitors (CZ =
220µF) were used. The VID on-the-fly step change is
250mV in 150µs with a setting error of 2.5mV. Solving for
the bulk capacitance yields:
(11)
The closest standard 1% resistor value is 1.33 kΩ.
REV. 1.0.0 Jul/15/05
21
FAN5019B
C X ( MAX) ≤
PRODUCT SPECIFICATION
2
⎛
⎞
⎜ 1 + ⎛⎜150μs ×1.5V × 3 × 4.6 ×1.3mΩ ⎞⎟ −1⎟ − 220μF = 23.9mF
×
2
2
⎟
250mV × 650nH
3× 4.6 × (1.3mΩ) ×1.5V ⎜
⎝
⎠
⎝
⎠
650nH × 250mV
⎞
⎛ 650nH × 60A
C X ( MIN ) ≥ ⎜
− 220μF ⎟ = 6.45mF
3
1
.
3
m
1
.
5
V
×
Ω
×
⎠
⎝
where K=4.6
Using eight 820µF A1-Polys with a typical ESR of 8mΩ,
each yields CX = 6.56µF with an RX = 1.0mΩ. One last
check should be made to ensure that the ESL of the bulk
capacitors (LX) is low enough to limit the initial highfrequency transient spike. This can be tested using:
LX ≤ CZ × R O
2
(14)
LX ≤ 220 μF × (1.3mΩ ) = 372 pH
2
In this example, LX is 375pH for the eight A1-Poly capacitors, which satisfies this limitation. If the LX of the chosen
bulk capacitor bank is too large, the number of MLC capacitors must be increased.
Note: For this multi-mode control technique, “allceramic” designs can be used as long as the conditions of
Equations 11, 12 and 13 are satisfied.
Power MOSFETs
For this example, the N-channel power MOSFETs have been
selected for one high-side switch and two low-side switches
per phase. The main selection parameters for the power
MOSFETs are VGS(TH), QG, CISS, CRSS and RDS(ON).
The minimum gate drive voltage (the supply voltage to the
FAN5009) dictates whether standard threshold or logic-level
threshold MOSFETs must be used. With VGATE ~10V,
logic-level threshold MOSFETs (VGS(TH) < 2.5V) are
recommended. The maximum output current IO determines
the RDS(ON) requirement for the low-side (synchronous)
MOSFETs. With the FAN5019B, currents are balanced
between phases, thus the current in each low-side MOSFET
is the output current divided by the total number of
MOSFETs (nSF). With conduction losses being dominant,
the following expression shows the total power being
dissipated in each synchronous MOSFET in terms of the
ripple current per phase (IR) and average total output
current (IO):
⎡⎛ I ⎞2 1 ⎛ n × I ⎞2 ⎤
R
⎟⎟ ⎥ × RDS ( SF )
PSF = (1 − D ) × ⎢⎜⎜ O ⎟⎟ + × ⎜⎜
n
n
12
⎝ SF ⎠ ⎥⎦
⎣⎢⎝ SF ⎠
(15)
Knowing the maximum output current being designed for
and the maximum allowed power dissipation, one can find
the required RDS(ON) for the MOSFET. For D-PAK
MOSFETs up to an ambient temperature of 50ºC, a safe limit
for PSF is 1W–1.5W at 125ºC junction temperature. Thus,
22
for our example (65A maximum), we find RDS(SF)
(per MOSFET) < 8.7mΩ. This RDS(SF) is also at a junction
temperature of about 125ºC, so we need to make sure we
account for this when making this selection. For our example, we selected two lower side MOSFETs at 8.6mΩ each at
room temperature, which gives 8.4mΩ at high temperature.
Another important factor for the synchronous MOSFET is
the input capacitance and feedback capacitance. The ratio
of the feedback to input needs to be small (less than 10% is
recommended), to prevent accidental turn-on of the synchronous MOSFETs when the switch node goes high.
Also, the time to switch the synchronous MOSFETs off
should not exceed the non-overlap dead time of the
MOSFET driver (40ns typical for the FAN5009). The
output impedance of the driver is about 2Ω and the typical
MOSFET input gate resistances are about 1Ω–2Ω, so a total
gate capacitance should be less than 6000pF. Since there are
two MOSFETs in parallel, we should limit the input capacitance for each synchronous MOSFET to 3000pF.
The high-side (main) MOSFET has to be able to handle two
main power dissipation components; conduction and switching losses. The switching loss is related to the amount of
time it takes for the main MOSFET to turn on and off, and to
the current and voltage that are being switched. Basing the
switching speed on the rise and fall time of the gate driver
impedance and MOSFET input capacitance, the following
expression provides an approximate value for the switching
loss per main MOSFET, where nMF is the total number of
main MOSFETs:
PS ( MF ) = 2 × f SW ×
VCC × I O
n MF
n MF × RG × n × C ISS
(16)
Here, RG is the total gate resistance (2Ω for the FAN5009
and about 1Ω for typical high speed switching MOSFETs,
making RG = 3Ω) and CISS is the input capacitance of the
main MOSFET. Adding more main MOSFETs (nMF) does
not significantly help the switching loss per MOSFET since
the additional gate capacitance slows down switching. The
best way to reduce switching loss is to use lower gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following, where RDS(MF) is the ON-resistance of the
MOSFET:
⎡⎛ I
PC ( MF ) = D × ⎢⎜⎜ O
⎢⎣⎝ nMF
2
⎞
1 ⎛ n × IR ⎞
⎟⎟
⎟⎟ + × ⎜⎜
12
⎝ nMF ⎠
⎠
2
⎤
⎥ × RDS ( MF )
⎥⎦
(17)
REV. 1.0.0 Jul/15/05
PRODUCT SPECIFICATION
FAN5019B
Typically, for main MOSFETs, one wants the highest
speed (low CISS) device, but these usually have higher
ON-resistance. Select a device that meets the total power
dissipation (about 1.5 W for a single D-PAK) when combining the switching and conduction losses.
For our example, we have selected a Fairchild FD6696 as the
main MOSFET (three total; nMF = 3), with a Ciss = 2058 pF
(max) and RDS(MF) = 15m (max at TJ = 125ºC) and a
Fairchild FDD6682 as the synchronous MOSFET (six total;
nSF = 6), with Ciss = 2880pF (max) and RDS(SF) = 11.9mΩ
(max at TJ = 125ºC). The synchronous MOSFET Ciss is less
than 3000 pF, satisfying that requirement. Solving for the
power dissipation per MOSFET at IO = 65A and IR = 8.86A
yields 1.24W for each synchronous MOSFET and 1.62W for
each main MOSFET. These numbers work well considering
there is usually more PCB area available for each main
MOSFET versus each synchronous MOSFET.
One last item to look at is the power dissipation in the driver
for each phase. This is best described in terms of the QG for
the MOSFETs and is given by the following, where QGMF is
the total gate charge for each main MOSFET and QGSF is the
total gate charge for each synchronous MOSFET:
⎡ f
⎤
PDRV = ⎢ SW × (nMF × QGMF + nSF × QGSF ) + I CC ⎥ ×VCC
⎣2×n
⎦
(18)
Also shown is the standby dissipation factor (ICC times the
VCC) for the driver. For the FAN5009, the maximum dissipation should be less than 400 mW. For our example, with
ICC = 7 mA, QGMF = 24nC (max) and QGSF = 31nC (max),
we find 202 mW in each driver, which is below the 400 mW
dissipation limit. See the FAN5009 data sheet for more
details.
Ramp Resistor Selection
The ramp resistor (RR) is used for setting the size of the
internal PWM ramp. This resistor’s value is chosen to provide the best combination of thermal balance, stability, and
transient response. The following expression is used for
determining the optimum value:
RR =
AR × L
3 × AD × RDS × C R
RR =
0.2 × 650nH
= 291kΩ
3 × 5 × 5.95mΩ × 5 pF
(19)
where AR is the internal ramp amplifier gain, AD is the
current balancing amplifier gain, RDS is the total low-side
MOSFET ON-resistance, and CR is the internal ramp
capacitor value. A close standard 1% resistor value is 301kΩ.
The internal ramp voltage magnitude can be calculated
using:
REV. 1.0.0 Jul/15/05
VR =
AR × (1 − D ) × VVID
RR × CR × f SW
VR =
0.2 × (1 − 0.125) × 1.5V
= 0.765V
301kΩ × 5 pF × 228kHz
(20)
The size of the internal ramp can be made larger or smaller.
If it is made larger, stability and transient response will
improve, but thermal balance will degrade. Likewise, if the
ramp is made smaller, thermal balance will improve at the
sacrifice of transient response and stability. The factor of
three in the denominator of equation 19 sets a ramp size that
gives an optimal balance for good stability, transient
response, and thermal balance.
COMP Pin Ramp
There is a ramp signal on the COMP pin due to the droop
voltage and output voltage ramps. This ramp amplitude adds
to the internal ramp to produce the following overall ramp
signal at the PWM input.
VRT =
VR
⎛
2 × (1 − n × D ) ⎞
⎟⎟
⎜⎜1 −
⎝ n × f SW × C X × RO ⎠
(21)
For this example, the overall ramp signal is found to be
0.974V.
Current Limit Set Point
To select the current limit set point, we need to find the
resistor value for RLIM. The current limit threshold for the
FAN5019B is set with a 3V source (VLIM) across RLIM with
a gain of 10.4mV/mA (ALIM). RLIM can be found using the
following:
RLIM =
ALIM × VLIM
I LIM × RO
(22)
For RLIM values greater than 500kΩ, the current limit may be
lower than expected, so some adjustment of RLIM may be
needed. Here, ILIM is the average current limit for the output
of the supply. For our example, choosing 120A for ILIM, we
find RLIM to be 200kΩ, for which we chose 200kΩ as the
nearest 1% value.
The per phase current limit described earlier has its limit
determined by the following:
I PHLIM ≅
VCOMP ( MAX ) − VR − VBIAS I R
−
2
AD × RDS ( MAX )
(23)
For the FAN5019B, the maximum COMP voltage
(VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS)
is 1.2V, and the current balancing amplifier gain (AD) is 5.
Using VR of 0.765V, and RDS(MAX) of 5.95mΩ (low-side
ON-resistance at 125°C), we find a per-phase limit of 40.44A.
23
FAN5019B
PRODUCT SPECIFICATION
This limit can be adjusted by changing the ramp voltage VR.
Do not set the per-phase limit lower than the average perphase current (ILIM/n).
There is also a per phase initial duty cycle limit determined
by:
DMAX = D ×
VCOMP ( MAX ) − VBIAS
(24)
VRT
For this example, the maximum duty cycle is found to be
0.2696.
Feedback Loop Compensation Design
Optimized compensation of the FAN5019B allows the best
possible response of the regulator’s output to a load change.
The basis for determining the optimum compensation is to
make the regulator and output decoupling appear as an
output impedance that is entirely resistive over the widest
possible frequency range, including DC, and equal to the
droop resistance (RO). With the resistive output impedance,
the output voltage will droop in proportion with the load
current at any load current slew rate; this ensures the optimal
positioning and allows the minimization of the output
decoupling.
With the multimode feedback structure of the FAN5019B,
the feedback compensation should be set to make the converter’s output impedance work in conjunction with the output decoupling to meet this goal. The output inductor and
decoupling capacitors (output filter) create several poles and
zeros that require compensation.
A type-III compensator on the voltage feedback is adequate
for proper compensation of the output filter. The expressions
given in Equations 25–29 are intended to yield an optimal
starting point for the design; some adjustments may be necessary to account for PCB and component parasitic effects
(see the Tuning Procedure for the FAN5019B section).
RL ×VRT 2 × L × (1− n × D) ×VRT
+
VVID
n ×CX × RO ×VVID
RE = 3 × 1.3mΩ + 5 × 5.95m Ω +
TA = C X × (RO − R' ) +
TB = (RX + R'− RO ) × C X
24
⎞
⎟⎟
⎠
(28)
5 × 6.95mΩ ⎞
⎛
0.974V × ⎜ 650nH −
⎟
2 × 228kHz ⎠
⎝
= 6.86 μs
TC =
1.5V × 55.3mΩ
TD =
C X × C Z × R O2
C X × (RO − R' ) + C Z × RO
TD =
6.56mF × 220 μF × (1.3mΩ )
= 500ns
6.56mF × (1.3mΩ − 0.6mΩ ) + 220μF × 1.3mΩ
(29)
2
where, for the FAN5019B, R' is the PCB resistance from the
bulk capacitors to the ceramics and where RDS is approximately the total low-side MOSFET ON resistance per phase
at 25ºC. For this example, AD is 5, VRT equals 0.974V, R' is
approximately 0.6mΩ (assuming a 4-layer motherboard) and
LX is 375pH for the eight Al-Poly capacitors.
The compensation values can then be solved using the following equations:
CA =
n × RO × TA
RE × RB
CA =
3 × 1.3mΩ × 4.79μs
= 253 pF
55.3mΩ × 1.33kΩ
RA =
TC 6.86μs
=
= 27.1kΩ
C A 253 pF
CB =
TB 1.97 μs
=
= 1.48nF
RB 1.33kΩ
TD
500ns
=
= 18.5 pF
RA 27.1kΩ
(30)
(31)
(32)
(33)
(25)
1.6m Ω × 0.974V 2 × 650 nH × (1 − 0.375 ) × 0.974V
+
= 55 .3mΩ
1.5V
3 × 6.56 mF × 1.3mΩ × 1.5V
LX RO − R'
×
RO
RX
TA = 6.56mF × (1.3mΩ − 0.6mΩ ) +
⎛
A × RDS
VRT × ⎜⎜ L − D
2 × f SW
⎝
TC =
VVID × RE
C FB =
The first step is to compute the time constants for all of the
poles and zeros in the system:
RE = n × RO + AD × RDS +
TB = (1.0mΩ + 0.6mΩ − 1.3mΩ ) × 6.56mF = 1.97μs
(26)
375 pH 1.3mΩ − 0.6mΩ
×
= 4.79 μs
1.3mΩ
1.0mΩ
(27)
REV. 1.0.0 Jul/15/05
PRODUCT SPECIFICATION
FAN5019B
Choosing the closest standard values for these components
yields: CA = 390pF, RA = 16.9kΩ, CB = 1.5nF, and CFB =
33pF.
CIN Selection and Input Current di/dt Reduction
In continuous inductor-current mode, the source current of
the high-side MOSFET is approximately a square wave with
a duty ratio equal to n (VOUT/VIN) and an amplitude of onenth of the maximum output current. To prevent large voltage
transients, use a low ESR input capacitor sized for the maximum rms current. The maximum rms capacitor current is
given by:
Tuning Procedure for the FAN5019B
DC Load Line Setting
1.
Build a circuit based on compensation values computed
from the design spreadsheet.
2.
Hook up DC load to circuit, turn on and verify operation. Also check for jitter at no-load and full-load.
3.
Measure output voltage at no-load (VNL). Verify it is
within tolerance.
100
EFFICIENCY (%)
80
60
40
20
0
0
10
20
30
40
50
60
OUTPUT CURRENT (A)
Figure 7. Efficiency vs. Output Current
(Circuit of Figure 5)
Figure 6. Typical Transient Response for Design Example
I CRMS = D × I O ×
1
−1
n×D
I CRMS = 0.125 × 65 A ×
Note that the capacitor manufacturer’s ripple current ratings
are often based on only 2000 hours of life. This makes it
advisable to further derate the capacitor, or to choose a
capacitor rated at a higher temperature than required. Several
capacitors may be placed in parallel to meet size or height
requirements in the design. In this example, the input
capacitor bank is formed by three 2200µF, 16V Nichicon
capacitors with a ripple current rating of 3.5A each.
To reduce the input-current di/dt to below the recommended
maximum of 0.1A/µs, insert an additional small inductor (L
> 1µH @ 15A) between the converter and the supply bus.
That inductor also acts as a filter between the converter and
the primary power source.
REV. 1.0.0 Jul/15/05
Measure output voltage at full-load cold (VFLCOLD).
Let board soak for ~10 minutes at full-load and measure
output (VFLHOT). If there is a change of more than a
couple of millivolts, adjust RCS1 and RCS2 using
Equations 35 and 37.
5.
Repeat Step 4 until cold and hot voltage measurements
remain the same.
6.
Measure output voltage from no-load to full-load using
5 Amp steps. Compute the loadline slope for each
change and then average to get overall loadline slope
(ROMEAS).
7.
If ROMEAS is off from RO by more than 0.05 mΩ,
use the following to adjust the RPH values:
(34)
1
− 1 = 10.5 A
3 × 0.125
(V − VFLCOLD )
RCS 2( NEW ) = RCS 2(OLD ) × NL
(VNL − VFLHOT )
4.
(35)
RPH ( NEW ) = RPH (OLD ) ×
ROMEAS
RO
(36)
8.
Repeat Steps 6 and 7 to check loadline and repeat
adjustments if necessary.
9.
Once the DC loadline adjustment is completed, do not
change RPH, RCS1, RCS2, or RTH for the rest of procedure.
25
FAN5019B
PRODUCT SPECIFICATION
1
RCS ( NEW ) =
RCS ( OLD) + RTH ( 25o C )
(
RCS1(OLD) × RTH ( 25o C ) + (RCS 2(OLD) − RCS 2( NEW ) )× RCS1(OLD) − RTH ( 25o C )
10. Measure the output ripple at no-load and full-load with a
scope and make sure it is within spec.
AC Loadline Setting
11. Remove DC load from circuit and hook up dynamic
load.
12. Hook up scope to output voltage and set to DC coupling
with a time scale at 100µs/div.
13. Set dynamic load for a transient step of approximately
40A at 1kHz with 50% duty cycle.
14. Measure the output waveform (may have to use DC offset on scope to see waveform). Try to use a vertical
scale of 100 mV/div or finer.
15. You will see a waveform that looks something like
Figure 8. Use the horizontal cursors to measure VACDRP
and VDCDRP as shown.
)
−
1
(37)
RTH ( 25o C )
18. Set the dynamic load step to the maximum step size (do
not use a step size larger than needed) and verify that the
output waveform is square (which means VACDRP and
VDCDRP are equal). NOTE: MAKE SURE LOAD
STEP SLEW RATE AND TURN-ON ARE SET FOR A
SLEW RATE OF ~150–250A/µs (for example, a load
step of 50A should take 200ns–300ns) WITH NO
OVERSHOOT. Some dynamic loads will have an
excessive turn-on overshoot if a minimum current is not
set properly (this is an issue if using a VTT tool).
Initial Transient Setting
19. With dynamic load still set at maximum step size,
expand the scope time scale to see 2µs/div to 5µs/div.
You will see a waveform that may have two overshoots
and one minor undershoot (see Figure 9). Here, VDROOP
is the final desired value.
NOTE: DO NOT MEASURE THE UNDERSHOOT OR
OVERSHOOT THAT HAPPENS IMMEDIATELY AFTER
THE STEP.
100
EFFICIENCY (%)
80
60
40
Figure 9. Transient Setting Waveform
20
0
0
10
20
30
40
50
60
OUTPUT CURRENT (A)
Figure 8. AC Loadline Waveform
16. If the VACDRP and VDCDRP are different by more than a
couple of millivolts, use Equation 38 to adjust CCS. You
may need to parallel different values to get the right one
since there are limited standard capacitor values available (it is a good idea to have locations for two capacitors in the layout for this).
CCS ( NEW ) = CCS (OLD ) ×
VACDRP
VDCDRP
(38)
17. Repeat Steps 11 to 13 and repeat adjustments if
necessary. Once complete, do not change CCS for the
rest of the procedure.
26
20. If both overshoots are larger than desired, try making
the following adjustments in this order. (NOTE: If these
adjustments do not change the response, you are limited
by the output decoupling.) Check the output response
each time you make a change as well as the switching
nodes (to make sure it is still stable).
a. Make ramp resistor larger by 25% (RRAMP).
b. For VTRAN1, increase CB or increase switching frequency.
c. For VTRAN2, increase RA and decrease CA by 25%.
21. For load release (see Figure 10), if VTRANREL is larger
than VTRAN1 (see Figure 9), you do not have enough
output capacitance. You will either need more capacitance or need to make the inductor values smaller (if
you change inductors, you need to start the design over
using the spreadsheet and this tuning procedure).
REV. 1.0.0 Jul/15/05
PRODUCT SPECIFICATION
FAN5019B
General Recommendations
• For good results, at least a four-layer PCB is
recommended. This should allow the needed versatility
for control circuitry interconnections with optimal
placement, power planes for ground, input, and output
power, and wide interconnection traces in the rest of the
power delivery current paths. Keep in mind that each
square unit of 1 ounce copper trace has a resistance of
~0.53 mΩ at room temperature.
• Whenever high currents must be routed between PCB
layers, vias should be used liberally to create several
parallel current paths so that the resistance and inductance
introduced by these current paths is minimized and the via
current rating is not exceeded.
Figure 10. Transient Setting Waveform
Since the FAN5019B turns off all of the phases (switches
inductors to ground), there is no ripple voltage present
during load release. Thus, you do not have to add headroom
for ripple, allowing your load release VTRANREL to be larger
than VTRAN1 by that amount and still be meeting spec. If
VTRAN1 and VTRANREL are less than the desired final droop,
this implies that capacitors can be removed. When removing
capacitors, check the output ripple voltage as well to ensure
it is still within spec.
Layout and Component Placement
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
Key layout issues are illustrated in Figure 11.
• If critical signal lines (including the output voltage sense
lines of the FAN5019B) must cross through power
circuitry, it is best if a signal ground plane can be
interposed between those signal lines and the traces of the
power circuitry to serves as a shield to minimize noise
injection into the signals..
• Use an analog ground plane both around and under the
FAN5019B for ground connections to the components
associated with the controller. Tie this plane to the nearest
output decoupling capacitor ground and not to any other
power circuitry to prevent power currents from flowing in
it.
• Connect the components around the FAN5019B close to
the controller with short traces. The most important traces
to keep short and away from other traces are the FB and
CSSUM pins.
• Connect the output capacitors as close as possible to the
load (or connector) that receives the power (e.g., a
microprocessor core). If the load is distributed, the
capacitors should also be distributed, and generally in
proportion to where the load tends to be more dynamic.
Figure 11. Layout Recommendations
REV. 1.0.0 Jul/15/05
Power Circuitry
• Route the switching power path on the PCB to encompass
the shortest possible length in order to minimize radiated
switching noise energy (i.e., EMI) and conduction losses
in the board. Failure to take proper precautions often
results in EMI problems for the entire PC system as well
as noise related operational problems in the power
converter control circuitry. The switching power path is
the loop formed by the current path through the input
capacitors and the power MOSFETs including all
interconnecting PCB traces and planes. The use of short
and wide interconnection traces is especially critical in
this path for two reasons: it minimizes the inductance in
the switching loop, which can cause high-energy ringing,
and it accommodates the high current demand with
minimal voltage loss. Avoid crossing any signal lines over
the switching power path loop, described below.
27
FAN5019B
• Whenever a power dissipating component (e.g., a power
MOSFET) is soldered to a PCB, the liberal use of vias,
both directly on the mounting pad and immediately
surrounding it, is recommended. Two important reasons
for this are: improved current rating through the vias, and
improved thermal performance from vias extended to the
opposite side of the PCB where a plane can more readily
transfer the heat to the air. To achieve the best thermal
dissipation to the air around the board, make a mirror
image of any pad being used to heatsink the MOSFETs on
the opposite side of the PCB . To further improve thermal
performance, use the largest possible pad area.
PRODUCT SPECIFICATION
Signal Circuitry
• The output voltage is sensed and regulated between the
FB pin and the FBRTN pin (which connects to the signal
ground at the load). To avoid differential mode noise
pickup in the sensed signal, the loop area should be small.
Thus the FB and FBRTN traces should be routed adjacent
to each other atop the power ground plane back to the
controller.
• Connect the feedback traces from the switch nodes as
close as possible to the inductor. Connect the CSREF
signal to the output voltage at the nearest inductor to the
controller.
• Route the output power path to encompass a short
distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the
load.
• For best EMI containment, use a solid power ground
plane as one of the inner layers extending fully under all
the power components.
28
REV. 1.0.0 Jul/15/05
PRODUCT SPECIFICATION
FAN5019B
Mechanical Dimensions
28-Pin TSSOP
–A–
9.7 ± 0.1
0.51 TYP
15
28
14
7.72
1.78
3.2
6.4
4.4 ± 0.1
4.16
–B–
B A
0.2
ALL Lead Tips
0.65
0.42
PIN # 1 IDENT
LAND PATTERN RECOMMENDATION
1.2 MAX
0.1 C
ALL LEAD TIPS
+0.15
0.90 –0.10
See Detail A
0.09–0.20
–C–
0.10 ± 0.05
0.65
0.19–0.30
0.13
A B
C
12.00° Top & Botom
R0.16
GAGE PLANE
R0.31
DIMENSIONS ARE IN MILLIMETERS
.025
0°–8°
NOTES:
0.61 ± 0.1
A. Conforms to JEDEC registration MO-153, variation AB,
Ref. Note 6, dated 7/93.
B. Dimensions are in millimeters.
C. Dimensions are exclusive of burrs, mold flash, and tie bar extensions.
D Dimensions and Tolerances per ANsI Y14.5M, 1982
REV. 1.0.0 Jul/15/05
SEATING PLANE
1.00
DETAIL A
29
FAN5019B
PRODUCT SPECIFICATION
Ordering Information
Part Number
FAN5019BMTCX
Temperature Range
0°C to +85°C
Pb Free
Yes
Package
TSSOP-28
Packing
Tape and Reel
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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