MICREL KSZ8695PI

KS8695P
Integrated Multi-Port PCI Gateway Solution
Rev. 1.5
General Description
The CENTAUR KS8695P, Multi-Port PCI Gateway
Solution, delivers a new level of networking integration,
performance, and overall BOM cost savings, enabling
original equipment manufacturers (OEMs) to provide
customers with feature-rich, low-cost solutions for the
residential gateway and small office environment.
• Integration of a PCI arbiter supporting three external
masters.
– Allows incorporation of a variety of productivity
enhancing system interfaces, including the expanding
802.11 a/g/b wireless LAN.
• High-performance ARM™ CPU (ARM9) with 8KB
I-cache, 8KB D-cache, and a memory management unit
(MMU) for Linux and WinCE® support.
• XceleRouter™ technology to accelerate packet
processing.
• Proven wire-speed switching technology that includes
802.1Q tag-based VLAN and quality of service (QoS)
support.
• Five patented mixed-signal, low-powered Fast Ethernet
transceivers with corresponding media access control
(MAC) units.
• Advanced memory interface with programmable 8/16/32bit data and 22-bit address bus with up to 64MB of total
memory space for Flash, ROM, SRAM, SDRAM, and
external peripherals.
Functional Diagram
Supports
up to
3 External
PCI Masters
XceleRouter is a trademark of Micrel, Inc. AMD is a registered trademark of Advanced Micro Devices, Inc. ARM is a trademark of Advanced RISC Machines Ltd.
Intel is a registered trademark of Intel Corporation. WinCE is a registered trademark of Microsoft Corporation.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
May 2006
M9999-051806
Micrel, Inc.
KS8695P
Features
• Memory and External I/O Interfaces
– 8/16/32-bit wide shared data path for Flash, ROM,
SRAM, SDRAM, and external I/O
– Total memory space up to 64MB
– Intel®/AMD®-type Flash support
The CENTAUR KS8695P featuring XceleRouter
technology is a single-chip, multi-port PCI "gateway-ona-chip" with all the key components integrated for a highperformance and low-cost broadband gateway.
• ARM9 High-Performance CPU Core
– ARM9 core at 166MHz
– 8KB I-cache and 8KB D-cache
– Memory management unit (MMU) for Linux and WinCE
– 32-bit ARM and 16-bit thumb instruction sets for
smaller memory footprints
• Peripheral Support
– 8/16/32-bit external I/O interface supporting PCMCIA or
generic CPU/DSP host I/F
– Sixteen general purpose input/output (GPIO)
– Two 32-bit timer counters (one watchdog)
– Interrupt controller
• 33MHz 32-Bit PCI Interface
– Version PCI 2.1
– Supports bus mastership or guest-mode
– Supports normal and memory-mapped I/O
– Support for miniPCI and cardbus peripherals
• System Design
– Up to 166MHz CPU and 125MHz bus speed
– 289 PBGA package (19mm x 19mm) saving board real
estate
– Two power supplies: 1.8V core and Ethernet RX
supply, 3.3V I/O and Ethernet TX supply
– Built-in LED controls
• Integrated Ethernet Transceivers and Switch Engine
– Five 10/100 Ethernet transceivers and five MACs (1P
for WAN interface, 4P for LAN switching)
– 100BASE-FX mode option on the WAN port and one
LAN port
– Automatic MDI/MDI-X crossover on all ports
– Wire-speed, non-blocking switch
– 802.1Q tag-based VLAN (16 VLANs, full range VID)
– Port-based VLAN
– QoS/CoS packet prioritization support: per port, 802.1p,
and DiffServ-based
– 64KB on-chip frame buffer SRAM
– VLAN ID and 802.1P tag/untag option per port
– 802.1D Spanning Tree Protocol support
– Programmable rate-limiting per port: 0Mbps to
100Mbps, ingress and egress, rate options for high and
low priority
– Extensive MIB counter management support
– IGMP snooping for multicast packet filtering
– Dedicated 1K entry look-up engine
– Port mirroring/monitoring/sniffing
– Broadcast and multicast storm protection with % control
global and per port basis
– Full- and half-duplex flow control
• Debugging
– ARM9 JTAG debug interface
– UART for console port or modem back-up
• Power Management
– CPU and system clock speed step-down options
– Low-power Ethernet transceivers
– Per port power-down and Ethernet transmit disable
• Reference Hardware and Software Evaluation Kit
– Hardware evaluation board (passes class B EMI)
– Board support package including firmware source
codes, Linux kernel, and software stacks
– Complete hardware and software reference designs
available
Applications
•
•
•
•
•
•
•
•
•
•
• XceleRouter Technology
– TCP/UDP/IP packet header checksum generation to
offload CPU tasks
– IPv4 packet fi ltering on checksum errors
– Automatic error packet discard
– DMA engine with burst-mode support for efficient
WAN/LAN data transfers
– FIFOs for back-to-back packet transfers
May 2006
2
Multi-port wireless VoIP gateway
Wireless mesh network node
RG + combo 802.11 a/b/g/n access point
Multimedia gateway
Digital audio access point
Network storage element
Multi-port broadband gateway
Multi-port firewall and VPN appliances
Combination wireless and wireline gateway
Fiber-to-the-home managed CPE
M9999-051806
Micrel, Inc.
KS8695P
Ordering Information
Commercial Part Number
Standard
Pb (lead)-Free
KS8695P
KSZ8695P
Temperature
Range
0° to +70°C
Industrial Part Number
Standard
Pb (lead)-Free
KS8695PI
KSZ8695PI
Temperature
Range
–40° to +85°C
Package
289-Pin PBGA
Package
289-Pin PBGA
Revision History
Revision
Date
Summary of Changes
0.9
05/13/03
Created.
0.91
06/04/03
Corrected WRSTPLS sets WRSTO to active low when ‘1’, and active high when ‘0’.
0.92
06/10/03
Changed pin A1 to GND. Changed pin E3, H7, J7, K7, L7 to AGND. Changed Figure 5 WRSTPLS to
pull up.
0.93
07/11/03
Removed PCI 2.2 compliance. Removed TM from Centaur. Added LANFXSD1 signal description.
0.94
07/17/03
Updated DC Electrical Characteristics.
0.95
08/11/03
Added addressing description to memory controller and address pin description Table 11. Changed
PRSTN to input in Table 10.
1.0
09/02/03
Changed Figure 1. Removed old register address tables and replaced with Figure 11. Added Memory
Interface examples, Figures 7,8, and 9. Added memory interface description, section 2.5.
1.1
09/29/03
Changed Figure 2.
1.2
08/04/04
Transferred to Micrel format and updated System Clock.
1.3
01/27/05
Added recommended reset circuit.
1.4
08/18/05
Added wireless applications. Added Pb-Free and industrial specification. Edits to Pin Description Table.
1.5
05/18/06
Added Pb-Free option for industrial specification.
May 2006
3
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Micrel, Inc.
KS8695P
Contents
System Level Applications................................................................................................................................................... 5
Pin Description ...................................................................................................................................................................... 6
Pin Configuration ................................................................................................................................................................ 14
Functional Description ....................................................................................................................................................... 15
Introduction ....................................................................................................................................................................... 15
CPU Features ................................................................................................................................................................... 15
PCI to AHB Bridge Features............................................................................................................................................. 15
Switch Engine ................................................................................................................................................................... 16
Advanced Memory Controller Features............................................................................................................................ 16
Direct Memory Access (DMA) Engines ............................................................................................................................ 16
Protocol Engine and XceleRouter™ Technology ............................................................................................................. 16
Network Interface.............................................................................................................................................................. 16
Peripherals........................................................................................................................................................................ 17
Other Features.................................................................................................................................................................. 17
Signal Description............................................................................................................................................................... 18
System Level Hardware Interfaces................................................................................................................................... 18
Configuration Pins ............................................................................................................................................................ 18
Reset................................................................................................................................................................................. 19
System Clock.................................................................................................................................................................... 20
Memory Interface.............................................................................................................................................................. 21
Signal Descriptions by Group ........................................................................................................................................... 25
Address Map and Register Description............................................................................................................................ 35
Memory Map ..................................................................................................................................................................... 35
Memory Map Example...................................................................................................................................................... 35
Register Description ......................................................................................................................................................... 35
Absolute Maximum Ratings ............................................................................................................................................... 36
Operating Ratings ............................................................................................................................................................... 36
Electrical Characteristics ................................................................................................................................................... 36
Timing Diagrams ................................................................................................................................................................. 38
Package Information........................................................................................................................................................... 42
May 2006
4
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Micrel, Inc.
KS8695P
System Level Applications
Figure 1. KS8695P PCI Gateway System Options
May 2006
5
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Micrel, Inc.
KS8695P
Pin Description
Signal List Alphabetized by Name
Pin Number
U4
T4
R3
P1
P2
N1
N2
N3
N4
M1
M2
M3
U3
P3
P4
T3
U2
U1
T1
T2
R1
R2
E3
H7
J7
K7
L7
D14
A11
B9
A6
B10
U15
T15
U12
T12
Pin Name
ADDR0
ADDR1
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
ADDR16
ADDR17
ADDR18
ADDR19
ADDR2
ADDR20/BA0
ADDR2/BA1
ADDR3
ADDR4
ADDR5
ADDR6
ADDR7
ADDR8
ADDR9
AGND
AGND
AGND
AGND
AGND
CBEN0
CBEN1
CBEN2
CBEN3
CLKRUNN
DATA0
DATA1
DATA10
DATA11
Type(1)
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Gnd
Gnd
Gnd
Gnd
Gnd
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin Function
Address Bit.
Address Bit.
Address Bit.
Address Bit.
Address Bit.
Address Bit.
Address Bit.
Address Bit.
Address Bit.
Address Bit.
Address Bit.
Address Bit.
Address Bit.
Address Bit/Bank Address Bit 0 for SDRAM Interface.
Address Bit/Bank Address Bit 1 for SDRAM Interface.
Address Bit.
Address Bit.
Address Bit.
Address Bit.
Address Bit.
Address Bit.
Address Bit.
Analog Signal Ground.
Analog Signal Ground.
Analog Signal Ground.
Analog Signal Ground.
Analog Signal Ground.
PCI Commands and Byte Enable 0. Active Low.
PCI Commands and Byte Enable 1. Active Low.
PCI Commands and Byte Enable 2. Active Low.
PCI Commands and Byte Enable 3. Active Low.
Cardbus Clock Run Request Signal. Active Low.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
Note:
1. Gnd = Ground.
O = Output.
I/O = Bidirectional.
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Micrel, Inc.
KS8695P
Pin Number
R12
P12
U11
T11
R11
P11
U10
T10
U14
R10
P10
U9
T9
R9
P9
U8
T8
R8
P8
T14
R7
P7
R14
P14
U13
T13
R13
P13
C11
R16
T16
U16
T17
Pin Name
DATA12
DATA13
DATA14
DATA15
DATA16
DATA17
DATA18
DATA19
DATA2
DATA20
DATA21
DATA22
DATA23
DATA24
DATA25
DATA26
DATA27
DATA28
DATA29
DATA3
DATA30
DATA31
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DEVSELN
ECSN0
ECSN1
ECSN2
EROEN/
WRSTPLS
Type(1)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O/I
M17
ERWEN0/
TESTACK
ERWEN1/
TESTREQB
ERWEN2/
TESTREQA
O
Pin Function
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
External Data Bit.
PCI Device Select Signal. Active Low.
External I/O Device Chip Select. Active Low.
External I/O Device Chip Select. Active Low.
External I/O Device Chip Select. Active Low.
ROM/SRAM/FLASH and External I/O Output Enable. Active Low. WRSTO
Polarity Select. WRSTPLS = 0, WRSTO = Active High; WRSTPLS = 1,
Active Low.
External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
O
External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
O
External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
N17
P17
Note:
1. O = Output.
I/O = BidirectionaL.
O/I = Output in normal mode; input pin during reset.
May 2006
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Micrel, Inc.
KS8695P
Type(1)
O
P16
D10
A1
G7
G8
G9
G10
G11
H8
H9
H10
H11
J8
J9
J10
J11
K8
K9
K10
K11
L8
L9
L10
L11
C4
Pin Name
ERWEN3/
TICTESTENN
EWAITN
FRAMEN
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNT1N
C3
GNT2N
O
C2
GNT3N
O
G17
G16
K17
K16
K15
K14
L17
GPIO0/EINT0
GPIO1/EINT1
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Pin Number
R17
I
I/O
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
O
Pin Function
External I/O and ROM/SRAM/FLASH Write Byte Enable. Active Low.
External Wait. Active Low.
PCI Bus Frame Signal. Active Low.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
Signal Ground.
PCI Bus Grant 2. Active Low. Output for Host Bridge Mode and Guest
Bridge Mode.
PCI Bus Grant 2. Active Low. Output for Host Bridge Mode. Not Used in
Guest Bridge Mode.
PCI Bus Grant 3. Active Low. Output for Host Bridge Mode. Not Used in
Guest Bridge Mode.
General Purpose I/O Pin. External Interrupt Request Pin.
General Purpose I/O Pin. External Interrupt Request Pin.
General Purpose I/O Pin.
General Purpose I/O Pin.
General Purpose I/O Pin.
General Purpose I/O Pin.
General Purpose I/O Pin.
Note:
1. Gnd = Ground.
I = Input.
O = Output.
I/O = Bidirectional.
May 2006
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Micrel, Inc.
KS8695P
Pin Number
L16
H17
H16
H15
H14
J17
J16
J15
J14
D7
A9
F1
Pin Name
GPIO15
GPIO2/EINT2
GPIO3/EINT3
GPIO4/TOUT0
GPIO5/TOUT1
GPIO6
GPIO7
GPIO8
GPIO9
IDSEL
IRDYN
ISET
Type(1)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I
B17
B16
C17
C16
D17
D16
E17
E16
H4
J4
K4
L4
H3
J3
K3
L3
H2
J2
K2
L2
H1
J1
K1
L1
E4
D2
A16
L1LED0
L1LED1
L2LED0
L2LED1
L3LED0
L3LED1
L4LED0
L4LED1
LANRXM1
LANRXM2
LANRXM3
LANRXM4
LANRXP1
LANRXP2
LANRXP3
LANRXP4
LANTXM1
LANTXM2
LANTXM3
LANTXM4
LANTXP1
LANTXP2
LANTXP3
LANTXP4
M66EN
MPCIACTN
PAD0
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
I
O
I/O
Pin Function
General Purpose I/O Pin.
General Purpose I/O Pin. External Interrupt Request Pin.
General Purpose I/O Pin. External Interrupt Request Pin.
General Purpose I/O Pin. Timer 0 Output Pin.
General Purpose I/O Pin. Timer 1 Output Pin.
General Purpose I/O Pin.
General Purpose I/O Pin.
General Purpose I/O Pin.
General Purpose I/O Pin.
Initialization Device Select. Active High.
PCI Initiator Ready Signal. Active Low.
Set PHY Transmit Output Current. Connect to Ground with 3.01kΩ 1%
Resistor.
LAN Port 1 LED Programmable Indicator 0. Active Low.
LAN Port 1 LED Programmable Indicator 1. Active Low.
LAN Port 2 LED Programmable Indicator 0. Active Low.
LAN Port 2 LED Programmable Indicator 1. Active Low.
LAN Port 3 LED Programmable Indicator 0. Active Low.
LAN Port 3 LED Programmable Indicator 1. Active Low.
LAN Port 4 LED Programmable Indicator 0. Active Low.
LAN Port 4 LED Programmable Indicator 1. Active Low.
LAN Port 1 PHY Receive Signal – (differential).
LAN Port 2 PHY Receive Signal – (differential).
LAN Port 3 PHY Receive Signal – (differential).
LAN Port 4 PHY Receive Signal – (differential).
LAN Port 1 PHY Receive Signal + (differential).
LAN Port 2 PHY Receive Signal + (differential).
LAN Port 3 PHY Receive Signal + (differential).
LAN Port 4 PHY Receive Signal + (differential).
LAN Port 1 PHY Transmit Signal – (differential).
LAN Port 2 PHY Transmit Signal – (differential).
LAN Port 3 PHY Transmit Signal – (differential).
LAN Port 4 PHY Transmit Signal – (differential).
LAN Port 1 PHY Transmit Signal + (differential).
LAN Port 2 PHY Transmit Signal + (differential).
LAN Port 3 PHY Transmit Signal + (differential).
LAN Port 4 PHY Transmit Signal + (differential).
PCI 66 MHz Enable.
MiniPCI Active Signal. Active Low.
PCI Address and Data 0.
Note:
1. I = Input.
O = Output.
I/O = Bidirectional.
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Micrel, Inc.
Pin Number
A15
B13
D13
A12
C12
B12
D12
C9
A8
D9
B8
C15
D8
A7
C7
B7
C6
B6
D6
A5
C5
B5
B15
D5
A4
D15
A14
C14
B14
A13
C13
C8
D3
D4
A2
B1
C1
D1
B11
A3
KS8695P
Pin Name
PAD1
PAD10
PAD11
PAD12
PAD13
PAD14
PAD15
PAD16
PAD17
PAD18
PAD19
PAD2
PAD20
PAD21
PAD22
PAD23
PAD24
PAD25
PAD26
PAD27
PAD28
PAD29
PAD3
PAD30
PAD31
PAD4
PAD5
PAD6
PAD7
PAD8
PAD9
PAR
PBMS
PCLK
PCLKOUT0
PCLKOUT1
PCLKOUT2
PCLKOUT3
PERRN
PRSTN
Type(1)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
O
O
O
O
I/O
I
Pin Function
PCI Address and Data 1.
PCI Address and Data 10.
PCI Address and Data 11.
PCI Address and Data 12.
PCI Address and Data 13.
PCI Address and Data 14.
PCI Address and Data 15.
PCI Address and Data 16.
PCI Address and Data 17.
PCI Address and Data 18.
PCI Address and Data 19.
PCI Address and Data 2.
PCI Address and Data 20.
PCI Address and Data 21.
PCI Address and Data 22.
PCI Address and Data 23.
PCI Address and Data 24.
PCI Address and Data 25.
PCI Address and Data 26.
PCI Address and Data 27.
PCI Address and Data 28.
PCI Address and Data 29.
PCI Address and Data 3.
PCI Address and Data 30.
PCI Address and Data 31.
PCI Address and Data 4.
PCI Address and Data 5.
PCI Address and Data 6.
PCI Address and Data 7.
PCI Address and Data 8.
PCI Address and Data 9.
PCI Parity.
PCI Bridge Mode Select. ‘1’ = Host Bridge Mode. ‘0’ = Guest Bridge Mode.
PCI Bus Clock.
PCI Clock Output 0.
PCI Clock Output 1.
PCI Clock Output 2.
PCI Clock Output 3.
PCI Parity Error Signal. Active Low.
PCI Reset. Active Low.
Note:
1. I = Input.
O = Output.
I/O = Bidirectional.
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KS8695P
Pin Number
P15
R15
B4
Pin Name
RCSN0
RCSN1
REQ1N
Type(1)
O
O
I
B3
REQ2N
I
B2
REQ3N
I
A17
T5
P5
R4
T7
U7
U6
T6
R6
P6
R5
U5
A10
D11
G14
F14
F15
M4
F4
F17
RESETN
SDCASN
SDCSN0
SDCSN1
SDICLK
SDOCLK
SDQM0
SDQM1
SDQM2
SDQM3
SDRASN
SDWEN
SERRN
STOPN
TCK
TDI
TDO
TEST1
TEST2
TESTEN
I
O
O
O
I
O
O
O
O
O
O
O
O
I/O
I
I
O
I
I
I
G15
C10
F16
M14
TMS
TRDYN
TRSTN
UCTSN/
BISTEN
UDCDN/
SCANEN
UDSRN
UDTRN/
DBGENN
URIN/TSTRST
URTSN/
CPUCLKSEL
I
I/O
I
I
L15
M16
N15
L14
M15
I
I
O/I
I
O/I
Pin Function
ROM/SRAM/FLASH Chip Select. Active Low.
ROM/SRAM/FLASH Chip Select. Active Low.
PCI Bus Request 1. Active Low. Input for Host Bridge Mode and Guest
Bridge Mode.
PCI Bus Request 2. Active Low. Input for Host Bridge Mode, Not Used in
Guest Bridge Mode.
PCI Bus Request 3. Active Low. Input for Host Bridge Mode, Not Used in
Guest Mode
KS8695P Chip Reset. Active Low.
SDRAM Column Address Strobe. Active Low.
SDRAM Chip Select. Active Low Chip Select Pins for SDRAM.
SDRAM Chip Select. Active Low Chip Select Pins for SDRAM.
SDRAM Clock In.
System/SDRAM Clock Out.
SDRAM Data Input/Output Mask.
SDRAM Data Input/Output Mask.
SDRAM Data Input/Output Mask.
SDRAM Data Input/Output Mask.
SDRAM Row Address Strobe. Active Low.
SDRAM Write Enable. Active Low.
PCI System Error Signal. Active Low.
PCI Stop Signal. Active Low.
JTAG Test Clock.
JTAG Test Data In.
JTAG Test Data Out.
PHY Test Pin (factory reserved test signal).
PHY Test Pin (factory reserved test signal).
Chip Test Enable (factory reserved test signal). Must be connected to GND
for normal operation.
JTAG Test Mode Select.
PCI Target Ready Signal. Active Low.
JTAG Test Reset. Active Low.
UART Data Set Ready. Active Low. BIST Enable (factory reserved test
signal).
UART Data Carrier Detect. Scan Enable (factory reserved test signal).
UART Data Set Ready. Active Low.
UART Data Terminal Ready. Active Low. Debug Enable (factory reserved
test signal).
UART Ring Indicator/Chip Test Reset (factory reserved test signal).
UART Request to Send/CPU Clock Select.
Note:
1. I = Input.
O = Output.
I/O = Bidirectional.
O/I = Output in normal mode; input pin during reset.
May 2006
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Micrel, Inc.
Pin Number
N16
N14
E7
E8
E9
E10
F7
F8
F9
F10
M7
M8
M9
H12
H13
J12
J13
K12
K13
N7
N8
N9
E11
E12
E13
F11
F12
F13
G12
G13
L12
L13
M10
M11
M12
M13
N10
N11
N12
N13
KS8695P
Pin Name
URXD
UTXD
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD1.8
VDD3.3
VDD3.3
VDD3.3
VDD3.3
VDD3.3
VDD3.3
VDD3.3
VDD3.3
VDD3.3
VDD3.3
VDD3.3
VDD3.3
VDD3.3
VDD3.3
VDD3.3
VDD3.3
VDD3.3
VDD3.3
Type(1)
I
O
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Pin Function
UART Receive Data.
UART Transmit Data.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
1.8V Digital Core VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
3.3V Digital I/O Circuitry VDD.
Note:
1. P = Power supply.
I = Input.
O = Output.
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Type(1)
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
I
I
I
O
O
O/I
Pin Function
1.8V Analog VDD.
1.8V Analog VDD.
1.8V Analog VDD.
1.8V Analog VDD.
1.8V Analog VDD.
1.8V Analog VDD.
1.8V Analog VDD.
1.8V Analog VDD.
1.8V Analog VDD.
1.8V Analog VDD.
3.3V Analog VDD.
3.3V Analog VDD.
3.3V Analog VDD.
3.3V Analog VDD.
3.3V Analog VDD.
3.3V Analog VDD.
3.3V Analog VDD.
3.3V Analog VDD.
WAN Fiber Signal Detect.
WAN PHY Receive Signal – (differential).
WAN PHY Receive Signal + (differential).
WAN PHY Transmit Signal – (differential).
WAN PHY Transmit Signal + (differential).
WAN LED Programmable Indicator 0. Bank 0 Size Bit 0.
O/I
WAN LED Programmable Indicator 1. Bank 0 Size Bit 1.
U17
Pin Name
VDDA1.8
VDDA1.8
VDDA1.8
VDDA1.8
VDDA1.8
VDDA1.8
VDDA1.8
VDDA1.8
VDDA1.8
VDDA1.8
VDDA3.3
VDDA3.3
VDDA3.3
VDDA3.3
VDDA3.3
VDDA3.3
VDDA3.3
VDDA3.3
WANFXSD
WANRXM
WANRXP
WANTXM
WANTXP
WLED0/
B0SIZE0
WLED1/
B0SIZE1
WRSTO
O
E1
E2
XCLK1
XCLK2
I
I
Watchdog Timer Reset Output.
When EROEN/WRSTPLS = 0, Active High.
When EROEN/WRSTPLS = 1, Active Low.
External Clock In.
External Clock In (negative polarity).
Pin Number
E5
E6
F5
F6
G5
G6
H5
H6
J5
J6
K5
K6
L5
L6
M5
M6
N5
N6
F2
G4
G3
G2
G1
E15
E14
Note:
1. P = Power supply.
I = Input.
O = Output.
O/I = Output in normal mode; input pin during reset.
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Pin Configuration
Figure 2. KS8695P Pin Mapping (Top View)
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Functional Description
Introduction
Micrel's KS8695P, a member of the CENTAUR line of integrated processors, is a high-performance router-on-a-chip solution for Ethernet and 802.11 a/g/b based embedded systems. Designed for use in communication's routers, it integrates a
PCI to AHB bridge solution for interfacing with 32-bit PCI, miniPCI, and cardbus devices. The KS8695P combines a
proven third generation 5-port managed switch, an ARM9 RISC processor with MMU, and five physical layer transceivers
(PHYs) including their corresponding MAC units with Micrel's XceleRouter technology.
The KS8695P is built around the 16/32-bit ARM9 RISC processor, which is a scalable, high-performance, microprocessor
developed for highly integrated system-on-a-chip applications. It also offers a configurable 8KB I-cache and 8KB D-cache
that reduces memory access latency for high-performance applications. The simple, elegant, and fully static design of the
KS8695P is especially suitable for cost-effective, power-sensitive applications.
The KS8695P contains five 10/100 PHYs: four are for the local area network (LAN) and one is for the wide area network
(WAN). Connected to the PHYs are five corresponding MAC units with an integrated Layer 2 managed switch. The
combining of the switch and the analog PHYs make the KS8695P an extremely prudent solution for SOHO router
applications, saving both board space and BOM costs. The Layer 2 switch contains a 16Kx32 SRAM on-chip memory for
frame buffering. The embedded frame buffer memory is designed with a 1.4Gbps on-chip memory bus. This allows the
KS8695P to perform full non-blocking frame switching and/or routing on the fly for many applications.
For the media interface, the KS8695P supports 10BASE-T and 100BASE-TX, as specified by the IEEE 802.3 standard,
and 100 BASE-FX on the WAN port and on one LAN port.
The KS8695P supports two modes of operation in the PCI bus environment: host bridge mode and guest bridge mode. In
the host bridge mode, the ARM9 processor acts as the host of the entire system. It configures other PCI devices and
coordinates their transactions, including initiating transactions between the PCI devices and AHB bus subsystem. An onchip PCI arbiter is included to determine the PCI bus ownership among PCI master devices. In host bridge mode, all I/O
registers, including those for the embedded switch, are configured by the ARM9 processor through the on-chip AMBA bus
interface.
In guest bridge mode, all of the I/O registers are programmed by either the external host CPU on the PCI bus or the local
ARM9 host processor through the AMBA bus. The KS8695P functions as a slave on the PCI bus with the on-chip PCI
arbiter disabled. The KS8695PX can be configured by either the ARM9 CPU or the PCI host CPU. In both cases, the
KS8695P memory subsystem is accessible from either the PCI host or the ARM9 CPU. Communications between the
external host CPU and the ARM9 is accomplished through message passing or through shared memory.
CPU Features
•
•
•
•
•
•
•
166MHz ARM9 RISC processor core
On-chip AMBA bus 2.0 interfaces
16-bit thumb programming to relax memory requirement
8KB I-cache and 8KB D-cache
Little-endian mode supported
Configurable memory management unit
Supports reduced CPU and system clock speed for power savings
PCI to AHB Bridge Features
•
•
•
•
•
•
•
•
•
•
•
•
Support 33MHz, 32-bit data PCI bus
Integrated PCI bridge support for interfacing with 32-bit miniPCI or cardbus devices
Independent AHB and PCI clock speed
Supports 125MHz AHB speed
Supports PCI revision 2.1 protocols
Supports AHB bus 2.0 interfaces
Supports both regular and memory-mapped I/O on the PCI interface
Integrated PCI arbiter with power-on option to enable or disable
Support Round Robin arbitration with three external PCI devices and one internal device
Supports AHB burst transfers up to 16 data words
Configurable PCI registers by host CPU ARM9
Supports bus mastership from PCI to AHB or AHB to PCI bus
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Switch Engine
• 5-Port 10/100 integrated switch with one WAN and four LAN physical layer transceivers
• 16Kx32 on-chip SRAM for frame buffering
• 1.4Gbps on-chip memory bandwidth for wire-speed frame switching
• 10Mbps and 100Mbps modes of operation for both full and half duplex
• Supports 802.1Q tag-based VLAN and port-based VLAN
• Supports 8.2,1p-based priority, DiffServ priority, and post-based priority
• Integrated address look-up engine, supports 1K absolute MAC addresses
• Automatic address learning, address aging, and address migration
• Broadcast storm protection
• Full-duplex IEEE 802.3x flow control
• Half-duplex back pressure flow control
• Supports IGMP snooping
• Spanning Tree Protocol support
Advanced Memory Controller Features
• Supports glueless connection to two banks of ROM/SRAM/FLASH memory with programmable 8/16/32 bit data bus and
programmable access timing
• Supports glueless connection to two SDRAM banks with programmable 8/16/32-bit data bus and programmable
RAS/CAS latency
• Supports three external I/O banks with programmable 8/16/32-bit data bus and programmable access timing
• Programmable system clock speed for power management
• Automatic address line mapping for 8/16/32-bit accesses on Flash, ROM, SRAM, and SDRAM interfaces
Direct Memory Access (DMA) Engines
• Independent MAC DMA engine with programmable burst mode for WAN port
• Independent MAC DMA engine with programmable burst mode for LAN ports
• Supports little-endian byte ordering for memory buffers and descriptors
• Contains large independent receive and transmit FIFOs (3KB receive/3KB transmit) for back-to-back packet receive,
and guaranteed no under-run packet transmit
• Data alignment logic and scatter gather capability
Protocol Engine and XceleRouter™ Technology
• Supports IPv4 IP header/TCP/UDP packet checksum generation for host CPU offloading
• Supports IPv4 packet filtering based on checksum errors
Network Interface
• Features five MAC units and five PHY units
• Supports 10BASE-T and 100BASE-TX on all LAN ports and one WAN port. Also supports 100BASE-FX on the WAN
port and on one LAN port
• Supports automatic CRC generation and checking
• Supports automatic error packet discard
• Supports IEEE 802.3 auto-negotiation algorithm of full-duplex and half-duplex operation for 10Mbps and 100Mbps
• Supports full-/half-duplex operation on PHY interfaces
• Fully compliant with IEEE 802.3 Ethernet standards
• IEEE 802.3 full-duplex flow control and half-duplex backpressure collision flow control
• Supports MDI/MDI-X auto-crossover
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Peripherals
• Twenty-eight interrupt sources, including four external interrupt sources
• Normal or fast interrupt mode (IRQ, FIQ) supported
• Prioritized interrupt handling
• Sixteen programmable general purpose I/O. Pins individually configurable to input, output, or I/O mode for dedicated
signals
• Two programmable 32-bit timers with watchdog timer capability
• High-speed UART interface up to 115kbps
Other Features
• Integrated PLL to generate CPU and system clocks
• JTAG development interface for ICE connection
• 19mm x 19mm 289-pin PBGA
• 1.8V CMOS for core and 3.3V for I/O
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Signal Description
System Level Hardware Interfaces
Figure 3. System Level Interfaces
At the system level the KS8695P features the following interfaces:
•
•
•
•
•
•
•
•
•
Clock interface for crystal or external oscillator
JTAG development interface
One WAN Ethernet physical interface
Four LAN Ethernet physical interfaces
PHY LED drivers
One high-speed UART interface
Sixteen GPIO pins
33MHz, 32-bit PCI interface supporting three external masters
Advanced memory interface
– Programmable synchronous bus rate
– Programmable asynchronous interface timing
– Independently programmable data bus width for static and synchronous memory
– Glueless connection to SDRAM
– Glueless connection to flash memory or ROM
• Factory test
• Power and ground
Configuration Pins
The following pins are sampled as input during reset.
Configuration
Bank0 Flash Data Width
Pin Name
B0SIZE[1:0]
Pin #
E14, E15
WRSTO Polarity
EROEN/WRSTPLS
U17
CPU Clock Select
URTSN/CPUCLKSEL
M15
PCI Bridge Mode
PBMS
D3
CPUCLKSEL
URTSN/CPUCLKSEL
M15
Debug Enable
UDTRN/DBGENN
N15
Setting
‘00’= reserved
‘01’ = byte wide
‘10’ = half word wide (16 bits)
‘11’ = word wide (32 bits)
‘0’ = active high
‘1’ = active low
‘0’ = normal mode (PLL)
'1’ = bypass internal PLL
‘0’ = guest bridge mode
‘1’ = host bridge mode
‘0’ = normal operation
‘1’ = factory reserved
‘0’ = factory reserved
Table 1. Configuration Pins
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Following pins have second function as factory test of chip.
Configuration
Chip Test Enable
Pin Name
TESTEN
Pin #
F17
ERWEN0/TESTACK
ERWEN1/TESTREQB
ERWEN2/TESTREQA
ERWEN3/TICTESTTENN
UCTSN/BISTEN
UDCDN/SCANEN
URIN/TSTRST
TEST1
TEST2
M17
N17
P17
R17
M14
L15
L14
M4
F4
Setting
‘0’ = normal operation
‘1’ = factory reserved. Used for factory test of
chip and affects all signals listed in this table.
Table 2. Configuration Pins
Reset
The KS8695P has a single reset input that can be driven by a system reset circuit or a simple power on reset circuit. The
KS8695P also features a reset output (WRSTO) that can be used to reset other devices in the system. WRSTO can be
configured as either an active high reset or an active low reset through a strap-in option on pin U17, as shown in Table 1.
The KS8695P also has a built in watchdog timer. When the watchdog timer is programmed and the timer setting expires,
the KS8695P resets itself and also asserts WRSTO to reset the other devices in the system. Figure 4 shows a typical
system using the KS8695P WRSTO as the system reset.
Reset Circuit Diagram
Figure 4. Example of a Reset Circuit
VCC
R
10k
D1
KS8695P
CPU/FPGA
RST
RST_OUT_n
D2
C
10µF
Figure 5. Recommended Circuit for Interfacing with CPU/FPGA Reset
At power-on-reset, R, C,and D1 provide the necessary ramp rise time to reset the Micrel device. The reset out from
CPU/FPGA provides warm reset after power up.
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System Clock
The clock to the KS8695P is supplied by either a 25MHz ±50ppm crystal or by an oscillator. If an oscillator is used, it must
be connected to the XCLK1 input (pin E1) on the KS8695P. If a crystal is used, it must be connected with a circuit similar
to the one shown below. The 25MHz input clock is used by an internal PLL to generate the programmable SDOCLK.
SDOCLK is the system clock and can be programmed from 25MHz to 125MHz using the system clock and bus control
register at offset 0x0004. The CPUCLKSEL strap-in option on pin M15 needs to be pulled low for normal operation.
SDICLK is used to register the data read from the SDRAM back into the KS8695P. The system designer must ensure that
SDRAM timing is met when routing SDOCLK back to SDICLK.
Figure 6. Typical Clock Circuit
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Memory Interface
The KS8695P has a glueless interface for SDRAM and static memory, i.e. ROM, SRAM, and Flash. It supports up to two
banks of static memory (Figure 7), up to two banks of SDRAM (Figure 8), and three banks of external I/O (Figure 9). The
total address space for the KS8695P is 64MB. This includes SDRAM, static memory, external I/O, and the KS8695P's
own 64KB of register space.
The memory interface for the SDRAM and static memory has a special automatic address mapping feature. This allows
the designer to connect address bit 0 on the memory to ADDR[0] on the KS8695P and address bit 1 on the memory to
ADDR[1] on the memory, regardless of whether the designer is trying to achieve word, half word, or byte addressing.
The KS8695P memory controller performs the address mapping internally. This permits the designer to use the maximum
amount of address bits, instead of losing one or two bits because of address mapping. For external I/O, however, the
designer still needs to take care of the address mapping (see Figure 9).
Figure 7. Static Memory Interface Examples
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Figure 8. SDRAM Interface Examples
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Figure 9. External I/O Interface Examples
KS8695P outputs ERWEN[3:0] as write strobes to byte wide, half-word wide, and word-wide memory port. The following
figures show the most commonly implemented examples.
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Figure 10. ERWEN[3:0] Interface Examples
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Signal Descriptions by Group
Clock and Reset Pins
Pin
E1
Name
XCLK1/
CPUCLK
I/O Type(1)
I
E2
XCLK2
I
M15
URTSN/
CPUCLKSEL
O/I
A17
RESETN
I
U17
WRSTO
O
T17
EROEN/
WRSTPLS
O/I
Description
External Clock In. This signal is used as the source clock for the transmit clock of
the internal MAC and PHY. The clock frequency is 25MHz ±50ppm. The XCLK1
signal is also used as the reference clock signal for the internal PLL to generate the
125MHz internal system clock.
External Clock In. Used with XCLK1 pin when another polarity of crystal is needed.
This is unused for a normal clock input.
Normal Mode: UART request to send. Active low output.
During reset: CPU clock select. Select CPU clock source. CPUCLKSEL=0 (normal
mode), the internal PLL clock output is used as the CPU clock source.
CPUCLKSEL=1 (factory reserved test signal).
KS8695P chip reset. Active low input asserted for at least 256 system clock (40ns)
cycles to reset the KS8695P. When in the reset state, all the output pins are tristated and all open drain signals are floating.
Watchdog timer reset output. This signal is asserted for at least 200ms if RESETN
is asserted or when the internal watchdog timer expires.
Normal Mode: ROM/SRAM/FLASH and External I/O output enable. Active low.
When asserted, this signal controls the output enable port of the specified device.
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active high;
WRSTPLS=1, Active low. No default.
JTAG Interface Pins
Pin
G14
G15
F14
F15
F16
Name
TCK
TMS
TDI
TDO
TRSTN
I/O Type(1)
I
I
I
O
I
Description
JTAG test clock.
JTAG test mode select.
JTAG test data in.
JTAG test data out.
JTAG test reset. Active low.
WAN Ethernet Physical Interface Pins
Pin
G1
G2
G3
G4
G5
Name
WANTXP
WANTXM
WANRXP
WANRXM
WANFXSD
I/O Type(1)
O
O
I
I
I
Description
WAN PHY transmit signal + (differential).
WAN PHY transmit signal – (differential).
WAN PHY receive signal + (differential).
WAN PHY receive signal – (differential).
WAN fiber signal detect. Signal detect input when the WAN port is operated in
100BASE-FX 100Mb fiber mode. See Application Note 10.
Note:
1. I = Input.
O = Output.
O/I = Output in normal mode; input pin during reset.
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LAN Ethernet Physical Interface Pins
Pin
H1
J1
K1
L1
H2
J2
K2
L2
H3
J3
K3
L3
H4
J4
K4
L4
F1
F3
Name
LANTXP1
LANTXP2
LANTXP3
LANTXP4
LANTXM1
LANTXM2
LANTXM3
LANTXM4
LANRXP1
LANRXP2
LANRXP3
LANRXP4
LANRXM1
LANRXM2
LANRXM3
LANRXM4
ISET
LANFXSD1
I/O Type(1)
I
Description
LAN Port[4:1] PHY transmit signal + (differential).
I
LAN Port[4:1] PHY transmit signal – (differential).
O
LAN Port[4:1] PHY receive signal + (differential).
O
LAN Port[4:1] PHY receive signal – (differential).
I
I
Set PHY transmit output current. Connect to ground through a 3.01kΩ 1% resistor.
LAN fiber signal detect. Signal detect input when the LAN1 port is operated in
100BASE-FX 100Mb fiber mode. See Application Note 107.
Description
Normal Mode: WAN LED indicator 0. Programmable via WAN misc. Control register
bits [2:0].
‘000’ = Speed; ‘001’ = Link; ‘010’ = Full/half duplex; ‘011’ = Collision;
‘100’ = TX/RX activity; ‘101’ = Full-duplex collision; ‘110’ = Link/Activity.
During reset: Bank 0 Data Access Size. Bank 0 is used for the boot program.
B0SIZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
Normal Mode: WAN LED indicator 1. Programmable via WAN Misc. Control register
bits [6:4].
‘000’ = Speed; ‘001’= Link; ‘010’ = Full/half duplex; ‘011’ = Collision;
‘100’ = TX/RX activity; ‘101’ = Full-duplex collision; ‘110’ = Link/Activity.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
B0SIZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
LAN Port[4:1] LED indicator 0. Programmable via switch control 0 register bits
[27:25].
‘000’ = Speed; ‘001’ = Link; ‘010’ = Full/half duplex; ‘011’ = Collision;
'100’ = TX/RX activity; ‘101’ = Full-duplex collision; ‘110’ = Link/Activity.
LAN Port[4:1] LED indicator 1. Programmable via switch control 0 register bits
[24:22].
‘000’ = Speed; ‘001’ = Link; ‘010’ = Full/half duplex; ‘011’ = Collision;
‘100’ = TX/RX activity; ‘101’ = Full-duplex collision; ‘110’ = Link/Activity.
PHY LED Drivers
Pin
E15
Name
WLED0/
B0SIZE0
I/O Type(1)
O/I
E14
WLED1/
B0SIZE1
O/I
B17
C17
D17
E17
B16
C16
D16
E16
L1LED0
L2LED0
L3LED0
L4LED0
L1LED1
L2LED1
L3LED1
L4LED1
O
O
Note:
1. I = Input.
O = Output.
O/I = Output in normal mode; input pin during reset.
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UART Pins
Pin
N16
N14
N15
M16
M15
Name
URXD
UTXD
UDTRN/
DBGENN
UDSRN
URTSN/
CPUCLKSEL
I/O Type(1)
I
O
O/I
UCTSN/
BISTEN
UDCDN/
SCANEN
URIN/
TSTRST
I
Description
UART receive data.
UART transmit data.
UART data terminal ready. Active low.
DBGENN = 0 (factory reserved test signal)
UART data set ready. Active low.
Normal mode: UART request to send. Active low output.
During reset: CPU clock select. Select CPU clock source. CPUCLKSEL=0 (normal
mode), the internal PLL clock output is used as the CPU clock source.
CPUCLKSEL=1 (factory reserved test signal).
UART clear to send. BIST enable (factory reserved test signal).
I
UART data carrier detect. Scan enable (factory reserved test signal).
I
UART ring indicator. Chip test reset (factory reserved test signal).
M14
L15
L14
I
O/I
General Purpose I/O Pins
Pin
G17
G16
H17
H16
H15
H14
J17
J16
J15
J14
K17
K16
K15
K14
L17
L16
A3
Name
GPIO0/
EINT0
GPIO1/
EINT1
GPIO2/
EINT2
GPIO3/
EINT3
GPIO4/
TOUT0
GPIO5/
TOUT1
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
PRSTN
I/O Type(1)
I/O
Description
General purpose I/O pin. External interrupt request pin.
I/O
General purpose I/O pin. External interrupt request pin.
I/O
General purpose I/O pin. External interrupt request pin.
I/O
General purpose I/O pin. External interrupt request pin.
I/O
General purpose I/O pin. Timer 0 output pin.
I/O
General purpose I/O pin. Timer 1 output pin.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
General purpose I/O pin.
General purpose I/O pin.
General purpose I/O pin.
General purpose I/O pin.
General purpose I/O pin.
General purpose I/O pin.
General purpose I/O pin.
General purpose I/O pin.
General purpose I/O pin.
General purpose I/O pin.
PCI Reset. Active low. This signal is an input used to reset the KS8695P PCI logic.
If the KS8695P is the host, use the RESETN signal to drive this input. If the
KS8695P is a guest, use the system reset to drive this signal.
Note:
1. I = Input.
O = Output.
I/O = Bidirectional.
O/I = Output in normal mode; input pin during reset.
May 2006
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M9999-051806
Micrel, Inc.
KS8695P
General Purpose I/O Pins (continued)
Pin
D4
Name
PCLK
I/O Type(1)
I
C2
GNT3N
O
C3
GNT2N
O
C4
GNT1N
O
B2
REQ3N
I
B3
REQ2N
I
B4
REQ1N
I
A4
D5
B5
C5
A5
D6
B6
C6
B7
C7
A7
D8
B8
D9
A8
C9
D12
B12
C12
A12
D13
B13
C13
A13
B14
C14
A14
D15
B15
PAD31
PAD30
PAD29
PAD28
PAD27
PAD26
PAD25
PAD24
PAD23
PAD22
PAD21
PAD20
PAD19
PAD18
PAD17
PAD16
PAD15
PAD14
PAD13
PAD12
PAD11
PAD10
PAD9
PAD8
PAD7
PAD6
PAD5
PAD4
PAD3
I/O
May 2006
Description
PCI bus clock.This signal provides the timing for the PCI bus transactions. This
signal is used to drive the PCI bus interface and the internal PCI logic. All PCI bus
signals are sampled on the rising edges of the PCLK. PCLK can operate from
20MHz to 33MHz. For host mode, use PCLKOUT0 signal to drive this input. In
guest mode, use the system PCI clock to drive this input.
PCI bus grant 3. Active low. In host bridge mode, this is an output signal from the
internal PCI arbiter to grant PCI bus access to the device connected to REQ3N. In
guest bridge mode, this signal is reserved.
PCI bus grant 2. Active low. In host bridge mode, this is an output signal from the
internal PCI arbiter to grant PCI bus access to the device connected to REQ2N. In
guest bridge mode, this signal is reserved.
PCI bus grant 1. Active low. In host bridge mode, this is an output signal from the
internal PCI arbiter to grant PCI bus access to the device connected to REQ1N. In
guest bridge mode, this signal is an output to indicate that the KS8695P is
requesting to access the PCI bus as a PCI master. In guest bridge mode, this is
basically the KS8695P’s request output.
PCI bus request 3. Active low. In host bridge mode, this is an input signal from the
external PCI device to request PCI bus access. In guest bridge mode, this signal is
reserved.
PCI bus request 2. Active low. In host bridge mode, this is an input signal from the
external PCI device to request PCI bus access.In guest bridge mode, this signal is
reserved.
PCI bus request 1. Active low. In host bridge mode, this is an input signal from the
external PCI device to request PCI bus access. In guest bridge mode, this is an
input signal from an external PCI bus arbiter granting access to the bus. In guest
bridge, this is basically the KS8695P's grant input.
32-Bit PCI address and data. PCI bus transactions consist of an address phase
followed by one or more data phases. Address and data signals are multiplexed on
the same pins. For a PCI write transaction, the source of the data is the KS8695P.
For a PCI read transaction, the data source is the target. The KS8695P supports
both read and write burst transactions. In the case of a read transaction, a special
data turn around cycle is needed between the address phase and the data
phase(s).
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KS8695P
General Purpose I/O Pins (continued)
Pin
C15
A15
A16
A6
B9
A11
D14
Name
PAD2
PAD1
PAD0
CBEN3
CBEN2
CBEN1
CBEN0
I/O Type(1)
I/O
C8
PAR
I/O
D10
FRAMEN
I/O
A9
IRDYN
I/O
C10
TRDYN
I/O
C11
DEVSELN
I/O
D7
IDSEL
I
D11
STOPN
I/O
B11
PERRN
I/O
A10
SERRN
O
E4
M66EN
I
May 2006
I/O
Description
32-Bit PCI address and data (continued from previous page).
PCI commands and byte enable. Active low.
The PCI command and byte enable signals are multiplexed on the same pins.
During the first clock cycle of a PCI transaction, the CBEN bus contains the
command for the transaction. The PCI transaction consists of the address phases
and one or more data phases. During the data phases of the transaction, the bus
carries the byte enable for the current data phases.
Parity. PCI bus parity is even across PAD[31:0] and CBEN[3:0]. The KS8695P
generates PAR during the address phase and write data phases as a bus master
and during read data phases as a target. It checks for correct PAR during the read
data phase as a bus master, during every address phase as a bus slave, and during
write data phases as a target.
PCI bus frame signal. Active low. FRAMEN is an indication of an active PCI bus
cycle. It is asserted at the beginning of a PCI transaction, i.e. the address phase,
and deasserted before the final transfer of the data phase of the transaction.
PCI initiator ready signal. Active low. This signal is asserted by a PCI master to
indicate a valid data phase on the PAD bus during data phases of a write
transaction. During a read transaction, it indicates that the master is ready to accept
data from the target. A target monitors the IRDYN signal when a data phase is
completed on any rising edge of the PCI clock when both IRDYN and TRDYN are
asserted. Wait cycles are inserted until both IRDYN and TRDYN are asserted
together.
PCI target ready signal. Active low. This signal is asserted by a PCI slave to
indicate a valid data phase on the PAD bus during a read transaction. During a write
transaction, it indicates that the slave is ready to accept data from the target. A PCI
initiator monitors the TRDYN signal when a data phase is completed on any rising
edge of the PCI clock when both IRDYN and TRDYN are asserted. Wait cycles are
inserted until both IRDYN and TRDYN are asserted together.
PCI device select signal. Active low. This signal is asserted when the KS8695P is
selected as a target during a bus transaction. When the KS8695P is the initiator of
the current bus access, it expects the target to assert DEVSELN within fi ve PCI bus
cycles, confirming the access. If the target does not assert DEVSELN within the
required bus cycles, the KS8695P aborts the bus cycle. To meet the timing
requirement, the KS8695P asserts this signal in a medium speed decode timing.
(two bus cycles).
Initialization device select. Active high. It is used as a chip select during
configuration read and write transactions.
PCI stop signal. Active low. This signal is asserted by the PCI target to indicate to
the bus master that it is terminating the current transaction. The KS8695P responds
to the assertion of STOPN when it is the bus master, either to disconnect, retry, or
abort the transaction.
PCI parity error signal. Active low. The KS8695P asserts PERRN when it checks
and detects a bus parity error. When it generates the PAR output, the KS8695P
monitors for any reported parity error on PERRN. When the KS8695P is the bus
master and a parity error is detected, the KS8695P sets error bits in the control
status registers. It completes the current data burst transaction, and then stops the
operation. After the host clears the system error, the KS8695P continues its
operation.
PCI system error signal. Active low. If an address parity error is detected, the
KS8695P asserts the SERRN signal two clocks after the failing address.
PCI 66MHz enable. When asserted, this signal indicates the PCI bus segment is
operating at 66MHz. This pin is mainly used in guest bridge mode when the PCLK
is driven by an external host bridge.
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M9999-051806
Micrel, Inc.
KS8695P
General Purpose I/O Pins (continued)
Pin
D1
Name
PCLKOUT3
I/O Type(1)
O
C1
PCLKOUT2
O
B1
PCLKOUT1
O
A2
PCLKOUT0
O
B10
CLKRUNN
I/O
D2
MPCIACTN
O
D3
PBMS
I
Description
PCI clock output 3. In host bridge mode driven as 33MHz
In guest bridge mode, this signal is reserved
PCI clock output 2. In host bridge mode driven as 33MHz
In guest bridge mode, this signal is reserved
PCI clock output 1. In host bridge mode driven as 33MHz
In guest bridge mode, this signal is reserved
PCI clock output 0. In host bridge mode driven as 33MHz
In guest bridge mode, this signal is reserved
This is a cardbus only signal. The CLKRUNN signal is used by portable cardbus
devices to request that the system turn on the bus clock. Output is always active in
cardbus and miniPCI modes.
MiniPCI active. This signal is asserted by the PCI device to indicate that its current
function requires full system performance. MPCIACTN is an open drain output
signal. In miniPCI mode, this signal is always low.
PCI bridge mode select. This selects the operating mode for the PCI bridge. When
PBMS is high, the host bridge mode is selected and the on-chip PCI bus arbiter is
enabled. When PBMS is low, the guest bridge mode is selected and the on-chip
arbiter is disabled.
Advanced Memory Interface (SDRAM/ROM/FLASH/SRAM/EXTERNAL I/O)
Pin
T7
U7
Name
SDICLK
SDOCLK
I/O Type(1)
I
O
P4
ADDR21/BA1
O
P3
ADDR20/BA0
O
M3
M2
M1
N4
N3
N2
N1
P2
P1
R3
R2
R1
T2
T1
U1
U2
T3
U3
T4
U4
ADDR[19]
ADDR[18]
ADDR[17]
ADDR[16]
ADDR[15]
ADDR[14]
ADDR[13]
ADDR[12]
ADDR[11]
ADDR[10]
ADDR[9]
ADDR[8]
ADDR[7]
ADDR[6]
ADDR[5]
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[1]
ADDR[0]
O
Description
SDRAM Clock In: SDRAM clock input for the SDRAM memory controller interface.
System/SDRAM Clock Out: Output of the internal system clock, it is also used as
the clock signal for SDRAM interface.
Address Bit 21/Bank Address Input 1: Address bit 21 for asynchronous accesses.
Bank Address Input bit 1 for SDRAM accesses.
Address Bit 20/Bank Address Input 0: Address bit 20 for asynchronous accesses.
Bank Address Input bit 0 for SDRAM accesses.
Address Bus: The 22-bit address bus (including ADDR[21:20] above) covers 4M
word memory space shared by ROM/SRAM/FLASH, SDRAM, and external I/O
banks. During the SDRAM cycles, the internal address bus is used to generate RAS
and CAS addresses for the SDRAM. The number of column address bits in the
SDRAM banks can be programmed from 8 to 11 bits via the SDRAM control
registers. ADDR[12:0] are the SDRAM address and ADDR[21:20] are the SDRAM
bank address. During other cycles, the ADDR[21:0] is the byte address of the data
transfer. For SDRAM and FLASH/ROM/SRAM, connect all address lines, i.e. A0 to
A0, A1 to A1, etc. The memory controller automatically handles address line
adjustments for the 8/16/32 bit accesses. For external I/O devices, the user needs
to connect address lines for 8/16/32 bit accesses.
Note:
1. I = Input.
O = Output.
I/O = Bidirectional.
May 2006
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M9999-051806
Micrel, Inc.
KS8695P
Advanced Memory Interface (SDRAM/ROM/FLASH/SRAM/EXTERNAL I/O) (continued)
Pin
P7
R7
P8
R8
T8
U8
P9
R9
T9
U9
P10
R10
T10
U10
P11
R11
T11
U11
P12
R12
T12
U12
P13
R13
T13
U13
P14
R14
T14
U14
T15
U15
R4
P5
R5
T5
Name
DATA[31]
DATA[30]
DATA[29]
DATA[28]
DATA[27]
DATA[26]
DATA[25]
DATA[24]
DATA[23]
DATA[22]
DATA[21]
DATA[20]
DATA[19]
DATA[18]
DATA[17]
DATA[16]
DATA[15]
DATA[14]
DATA[13]
DATA[12]
DATA[11]
DATA[10]
DATA[9]
DATA[8]
DATA[7]
DATA[6]
DATA[5]
DATA[4]
DATA[3]
DATA[2]
DATA[1]
DATA[0]
SDCSN[1]
SDCSN[0]
SDRASN
SDCASN
I/O Type(1)
I/O
U5
P6
R6
T6
U6
SDWEN
SDQM[3]
SDQM[2]
SDQM[1]
SDQM[0]
O
O
U16
T16
R16
P16
ECSN[2]
ECSN[1]
ECSN[0]
EWAITN
O
R15
P15
RCSN[1]
RCSN[0]
O
O
O
O
I
Description
External Data Bus. 32-Bit bi-directional data bus for data transfer. The KS8695P
also supports 8-bit and 16-bit data bus widths.
SDRAM Chip Select: Active low chip select pins for SDRAM. The KS8695P
supports up to two SDRAM banks. One SDCSN output is provided for each bank.
SDRAM Row Address Strobe: Active low. The row address strobe pin for SDRAM.
SDRAM Column Address Strobe: Active low. The column address strobe pin for
SDRAM.
SDRAM Write Enable: Active low. The write enable signal for SDRAM.
SDRAM Data Input/Output Mask: Data input/output mask signals for SDRAM. The
SDQM is sampled high and is an output mask signal for write accesses and an
output enable signal for read accesses. Input data are masked during a write cycle.
The SDQM0/1/2/3 correspond to DATA[7:0], DATA[15:8], DATA[23:16] and
DATA[31:24], respectively.
External I/O Device Chip Select: Active low. Three external I/O banks are provided
for external memory mapped I/O operations. Each I/O bank stores up to 16KB.
The ECSNx signals indicate which of the three I/O banks is selected.
External Wait: Active low. This signal is asserted when an external I/O device or a
ROM/SRAM/FLASH bank needs more access cycles than those defined in the
corresponding control register.
ROM/SRAM/FLASH Chip Select: Active low. The KS8695P can access up to two
external ROM/SRAM/FLASH memory banks. The RCSN pins can be controlled to
map the CPU addresses into physical memory banks.
Note:
1. I = Input.
O = Output.
I/O = Bidirectional.
May 2006
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M9999-051806
Micrel, Inc.
KS8695P
Advanced Memory Interface (SDRAM/ROM/FLASH/SRAM/EXTERNAL I/O) (continued)
Pin
T17
Name
EROEN/
WRSTPLS
I/O Type(1)
O/I
M17
ERWEN0/
TESTACK
O
N17
ERWEN1/
TESTREQB
O
P17
ERWEN2/
TESTREQA
O
R17
ERWEN3/
TICTESTENN
O
E15
WLED0/
B0SIZE0
O/I
E14
WLED1/
B0SIZE1
O/I
Description
Normal mode: External I/O and ROM/SRAM/FLASH output enable: Active low.
When asserted, this signal controls the output enable port of the specified memory
device.
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, active low;
WRSTPLS = 1, active high. No default.
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
the ERWENx controls the byte write enable of the memory device (except SDRAM).
ARM CPU test signal (factory reserved test signal).
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
the ERWENx controls the byte write enable of the memory device (except SDRAM).
ARM CPU test signal (factory reserved test signal).
External I/O and ROM/SRAM/FLASH write byte enable: Active low. When asserted,
the ERWENx controls the byte write enable of the memory device except SDRAM).
ARM CPU test signal (factory reserved test signal).
External I/O and ROM/SRAM/FLASH write byte enable. Active low. When asserted,
the ERWENx controls the byte write enable of the memory device (except SDRAM).
ARM CPU test signal (factory reserved test signal).
Normal mode: WAN LED indicator 0: Programmable via WAN misc. Control register
bits [2:0].
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
B0SiZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
Normal mode: WAN LED indicator 1: Programmable via WAN Misc. Control register
bits [6:4].
000 = Speed; 001 = Link; 010 = Full/half duplex; 011 = Collision;
100 = TX/RX activity; 101 = Full-duplex collision; 110 = Link/Activity.
During reset: Bank 0 data access size. Bank 0 is used for the boot program.
B0SIZE[1:0] are used to specify the size of the bank 0 data bus width as follows:
‘01’ = one byte, ‘10’ = half-word, ‘11’ = one word, and ‘00’ = reserved.
Factory Test Pins
Pin
F7
M4
F4
Name
TESTEN
TEST1
TEST2
I/O Type(1)
I
I
I
Description
Factory test signal. Pull-down or direct connect to GND required.
Factory test signal. No connect for normal operation.
Factory test signal. No connect for normal operation.
Note:
1. I = Input.
O = Output.
O/I = Output in normal mode; input pin during reset.
May 2006
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M9999-051806
Micrel, Inc.
KS8695P
Power and Ground Pins
Pin
E5
E6
F5
F6
G5
G6
H5
H6
J5
J6
E7
E8
E9
E10
F7
F8
F9
F10
M7
M8
M9
H12
H13
J12
J13
K12
K13
N7
N8
N9
K5
K6
L5
L6
M5
M6
N5
N6
E11
E12
E13
F11
F12
F13
G12
G13
L12
L13
M10
M11
M12
M13
N10
N11
N12
N13
Name
VDDA1.8
I/O Type(1)
P
VDD1.8
P
1.8V digital core VDD.
VDDA3.3
P
3.3V analog VDD.
VDD3.3
P
3.3V digital I/O VDD.
Description
1.8V analog VDD.
Note:
1. P = Power supply.
May 2006
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M9999-051806
Micrel, Inc.
KS8695P
Power and Ground Pins (continued)
Pin
E3
H7
J7
K7
L7
A1
G7
G8
G9
G10
G11
H8
H9
H10
H11
J8
J9
J10
J11
K8
K9
K10
K11
L8
L9
L10
L11
Name
AGND
I/O Type(1)
Gnd
GND
Gnd
Description
Analog Ground.
Ground.
Note:
1. Gnd = Ground.
May 2006
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M9999-051806
Micrel, Inc.
KS8695P
Address Map and Register Description
Memory Map
Upon power up, the KS8695P memory map is confi gured as shown below.
Address Range
0x03FF0000-0x03FFFFFF
0x02000000-0x03FEFFFF
0x00000000-0x01FFFFFF
Region
64KB
32MB
32MB
Description
KS8695P System Configuration Register Space
Not Configured
Flash Bank 0
Memory Map Example
The default base address for the KS8695P system configuration registers is 0x03ff0000. After power up, the user is free
to remap the memory for their specific application. The following is an example of the memory space remapped for
operation.
Address Range
0x03FF0000-0x03FFFFFF
0x03E00000-0x03FEFFFF
0x03200000-0x036FFFFF
0x02C00000-0x031FFFFF
0x02800000-0x02BFFFFF
0x02000000-0x027FFFFF
0x00000000-0x01FFFFFF
Region
64KB
2MB
5MB
6MB
4MB
8MB
32MB
Description
KS8695P System Configuration Register Space
Disabled, Not Used
Space (External I/O)
Reserved FLASH Space, Not Used
FLASH
Disabled, Not Used
SDRAM
Register Description
The KS8695P system configuration registers (SCRs) are located in a block of 64KB in the host memory address space.
After power up and initialization, the user can remap the SCRs to a desired offset. The SCRs are 32 bits wide. They are
32 bit word-aligned and must be accessed using word instructions.
The AHB-PCI bridge configuration registers are also included in the SCRs. A subset of the AHB-PCI bridge configuration
registers is also accessible to an external PCI host when the KS8695P is configured in PCI guest mode. Refer to the
detailed Register Description document for additional information, including bit definitions. If you don’t have this document,
contact your local Micrel Field Application Engineer or salesperson.
Address Range
0x0000 – 0x0004
0x2000 – 0x2224
0x4000 – 0x4040
0x6000 – 0x60FC
0x8000 – 0x80FC
0xA000 – 0xA0FC
0xE000 – 0xA0FC
0xE200 – 0xE234
0xE400 – 0xE410
0xE600 – 0xE608
0xE800 – 0xE850
0xEA00 – 0xEA18
May 2006
Register Type
System Registers
PCI-AHB Bridge Configuration
Memory Controller Interface
WAN DMA
LAN DMA
Reserved
UART Registers
Interrupt Controller
Timer Registers
General Purpose I/O
Switch Engine Configuration
Miscellaneous Registers
Register Type
System Configuration
External I/O Bank 2
External I/O Bank 1
External I/O Bank 0
Not Used
Flash Bank 0 – 4MB
Not Used
SDRAM 16MB
35
Address Range
0x03FFFFFF – 0x03FEFFFF
0x03FEFFFF – 0x039FFFFF
0x039FFFFF – 0x035FFFFF
0x035FFFFF – 0x031FFFFF
0x031FFFFF – 0x02FFFFFF
0x02FFFFFF – 0x027FFFFF
0x027FFFFF – 0x00FFFFFF
0x00FFFFFF – 0x00000000
M9999-051806
Micrel, Inc.
KS8695P
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage
(VDDA1.8,VDD1.8)........................................ –0.5V to +2.4V
(VDDA3.3,VDD3.3)........................................ –0.5V to +4.0V
Input Voltage (all inputs) .............................. –0.5V to +4.0V
Output Voltage (all outputs) ......................... –0.5V to +4.0V
Lead Temperature (soldering, 10sec.)....................... 270°C
Pb (Lead) Free Temperature (soldering, 10sec.)....... 260°C
Storage Temperature (Ts) .........................–55°C to +150°C
Supply voltage
(VDDA1.8,VDD1.8)........................................ +1.7V to +1.9V
(VDDA3.3,VDD3.3)(3)..................................... +3.0V to +3.6V
Ambient Temperature (TA) ............................ –0°C to +70°C
Junction Temperature (TJ) ......................................... 150°C
Package Thermal Resistance(4)
PBGA (θJA) No Air Flow................................29.86°C/W
1m/s ..........................................21.86°C/W
2m/s ..........................................21.54°C/W
(θJC) No Air Flow..................................8.34°C/W
Electrical Characteristics(5)
Symbol
Parameter
Condition
Min
Typ
Max
Units
Total Supply Current (including TX output driver current)
100BASE-TX Operation: All ports 100% Utilization, SDOCLK = 125MHz
ITX
100BASE-TX (Analog TX)
VDDA3.3 = +3.3V
0.032
A
IRX
100BASE-TX (Analog RX)
VDDA1.8 = +1.8V
0.072
A
IDDIO
100BASE-T (Digital I/O)
VDD3.3 = +3.3V
0.033
A
IDDC
100BASE-T (Digital Core)
VDD1.8 = +1.8V
0.235
A
10BASE-TX Operation: All ports 100% Utilization, SDOCLK = 125MHz
ITX
10BASE-TX (Analog TX)
VDDA3.3 = +3.3V
0.030
A
IRX
10BASE-TX (Analog RX)
VDDA1.8 = +1.8V
0.072
A
IDDIO
10BASE-T (Digital I/O)
VDD3.3 = +3.3V
0.025
A
IDDC
10BASE-T (Digital Core)
VDD1.8 = +1.8V
0.234
A
Auto-Negotiation Mode: SDOCLK = 125MHz
ITX
10BASE-TX (Analog TX)
VDDA3.3 = +3.3V
0.032
A
IRX
10BASE-TX (Analog RX)
VDDA1.8 = +1.8V
0.07
A
IDDIO
10BASE-T (Digital I/O)
VDD3.3 = +3.3V
0.021
A
IDDC
10BASE-T (Digital Core)
VDD1.8 = +1.8V
0.233
A
TTL Inputs (PCI, LED, Memory Interface, UART)
VIH
Input High Voltage
VIL
Input Low Voltage
IIN
Input Current
(Excluding pull-up/pull-down)
2.0
VIN = GND ~ VDD3.3
–10
V
0.8
V
10
µA
TTL Outputs (PCI, LED, Memory Interface, UART)
VOH
Output High Voltage
IOH = –8mA; VDD3.3
VOL
Output Low Voltage
IOL = 8mA
IOZ
Output Tri-state Leakage
May 2006
2.4
36
V
0.7
V
10
µA
M9999-051806
Micrel, Inc.
Symbol
KS8695P
Parameter
Condition
Min
Typ
Max
Units
1.05
V
2
%
5
0.5
ns
ns
±0.5
ns
5
%
100BASE-TX Transmit (measured differentially after 1:1 transformer)
VO
Peak Differential Output Voltage
100Ω termination on the differential output
VIMB
Output Voltage Imbalance
100Ω termination on the differential output
tr, tt
Rise/Fall Time
Rise/Fall Time Imbalance
0.95
3
0
Duty Cycle Distortion
Overshoot
VSET
Reference Voltage of ISET
Output Jitters
0.5
V
Peak-to-peak
0.7
1.4
ns
5MHz square wave
400
mV
2.3
V
10BASE-T Receive
VSQ
Squelch Threshold
10BASE-T Transmit (measured differentially after 1:1 transformer)
VP
Peak Differential Output Voltage
100Ω termination on the differential output
Jitters Added
100Ω termination on the differential output
Rise/Fall Time
28
±3.5
ns
30
ns
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating. Unused inputs must always be tied to an appropriate logic voltage level (Ground
to VDD).
3. VDDA or VDD can operate from either a 2.5V or 3.3V supply.
4. No heat spreader in package.
5. Specification for packaged product only.
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Micrel, Inc.
KS8695P
Timing Diagrams
For PCI timing, please refer to the PCI specification, version 2.1.
Supply Voltages
tsr
RESETN
tch
tcs
Strap-In
trc
Strap-In Pin Output
Figure 11. Reset Timing
Symbol
Parameter
Min
Typ
Max
Units
tSR
Stable supply voltages to reset high
10
ms
tCS
Configuration set-up time
50
ns
tCH
Configuration hold time
50
ns
tRC
Reset to strap-in pin output
50
ns
Table 2. Reset Timing Parameters
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Micrel, Inc.
KS8695P
Figure 12. Static Memory Read Cycle
Figure 13. Static Memory Write Cycle
Symbol
Parameter(1)
Registers
RBiTACC
Programmable bank i access time
0x4010
RBiTPA
Programmable bank i page access time
0x4014
Table 3. Programmable Static Memory Timing Parameters
Note:
1. "i" Refers to chip select parameters 0 and 1.
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M9999-051806
Micrel, Inc.
KS8695P
Figure 14. External I/O Read and Write Cycles
Min(1)
Typ(1)
Max(1)
Units
Valid address to CS setup time
EBiTACS
+0.8
EBiTACS
+1.1
EBiTACS
+1.3
ns
OE valid to CS setup time
EBiTCOS
+0.6
EBiTCOS
+0.6
EBiTCOS
+1.0
ns
EBiTCOS
+0.6
EBiTCOS
+1.0
ns
EBiTCOH
+1.0
EBiTCOH
+1.4
ns
EBiTACT
ns
Symbol
Parameter
Tcta
Tcos
Tdsu
Valid read data to OE setup time
Tcws
WE valid to CS setup time
2.0
EBiTCOS
+0.6
Tdh
Write data to CS hold time
Tcah
Address to CS hold time
EBiTCOH
+1.0
Toew
OE/WE pulsewidth
EBiTACT
Tocs, Tcsw
Rising edge CS to OE/WE hold time
ns
0
ns
0
ns
Table 4. External I/O Memory Timing Parameters
Note:
1. Measurements for minimum were taken at 0°C, typical at 25°C, and maximum at 100°C.
Symbol
Parameter(1)
Registers
EBiTACS
Programmable bank i address setup time before chip select
0x4000, 0x4004, 0x4008
EBiTACT
Programmable bank i write enable/output enable access time
0x4000, 0x4004, 0x4008
EBiTCOS
Programmable bank i chip select setup time before OEN
0x4000, 0x4004, 0x4008
EBiTCOH
Programmable bank i chip select hold time
0x4000, 0x4004, 0x4008
Table 5. Programmable External I/O Timing Parameters
Note:
1. "i" Refers to chip select parameters 0, 1, or 2.
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Micrel, Inc.
KS8695P
Figure 15. DRAM Read Timing
Figure 16. SDRAM Write Timing
Symbol
Parameter(1)
Registers
SDTRC
Programmable SDRAM RAS to CAS latency
0x4038
SDCAS
Programmable SDRAM CAS latency
0x4038
Table 6. SDRAM Timing Parameters
Note:
1. "i" Refers to chip select parameters 0 and 1.
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M9999-051806
Micrel, Inc.
KS8695P
Package Information
289-Pin PBGA
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its
use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2003 Micrel, Incorporated.
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