MICREL MIC5163_09

MIC5163
Dual Regulator Controller for DDR3
GDDR3/4/5 Memory Termination
General Description
Features
The MIC5163 is a dual regulator controller designed
• 0.75V to 6V input supply voltage
specifically for low voltage memory termination
• Memory termination for: DDR3, GDDR3/4/5
applications such as DDR3 and GDDR3/4/5. The MIC5163
• Tracking programmable output
offers a simple, low cost JEDEC compliant solution for
• Logic controlled enable input
terminating high-speed, low-voltage digital buses.
• Wide bandwidth
The MIC5163 controls two external N-Channel MOSFETs
• Minimal external components required
to form two separate regulators. It operates by switching
between either the high-side MOSFET or the low-side
• Tiny MSOP-10 package
MOSFET, depending on whether the current is being
• –40°C < TJ < +125°C
sourced to the load or being sinked by the regulator.
Designed to provide a universal solution for memory
Applications
termination regardless of input voltage, output voltage, or
load current; the desired MIC5163 output voltage can be
• Desktop Computers
externally programmed by forcing the reference voltage.
• Servers
The MIC5163 operates from an input voltage as low as
• Notebook computers
0.75V up to 6V, with a second bias supply input required
• Workstations
for operation. The MIC5163 is available in a tiny MSOP-10
package with an operating junction temperature range of
–40°C to +125°C.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
____________________________________________________________________________________________________________
Typical Application
U1
MIC5163
VDDQ = 1.2V
VDDQ
VCC = 5V
VCC
100µF
6.3V
100µF
6.3V
EN
HSD
EN
VREF
1µF
10V
120pF
LSD
COMP
SUD50N02-06P
VTT = 0.6V
SUD50N02-06P
220pF
100µF
6.3V
GND FB
100µF
6.3V
GND
GND
MIC5163 as a DDR3 Memory Termination Device for 3.5A application
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
April 2009
M9999-042209-A
Micrel, Inc.
MIC5163
Ordering Information
Part Number
Temperature Range
Package
Lead Finish
MIC5163YMM
–40° to +125°C
10-Pin MSOP
Pb-Free
Note: MSOP is a Green RoHs compliant package. Lead finish is NiPdAu. Mold compound is halogen free.
Pin Configuration
VCC
1
10 NC
EN
2
9 HD
VDDQ
3
8 LD
VREF
4
7 COMP
GND
5
6 FB
10-Pin MSOP (MM)
Pin Description
Pin Number
Pin Name
1
VCC
2
EN
3
VDDQ
Input Supply Voltage
4
VREF
Reference output equal to half of VDDQ
5
GND
Ground
6
FB
7
COMP
8
LD
Low-side drive: Connects to the Gate of the external low-side MOSFET
9
HD
High-side drive: Connects to the Gate of the external high-side MOSFET
10
NC
Not internally connected
April 2009
Pin Function
Bias Supply (Input): Apply a voltage between +3V and +6V to this input for
internal bias to the controller
Enable (Input): CMOS compatible input. Logic high = enable, logic low =
shutdown
Feedback input to the internal error amplifier
Compensation (Output): Connect a capacitor to feedback pin for compensation
of the internal control loop
2
M9999-042209-A
Micrel, Inc.
MIC5163
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VCC)....................................... –0.3V to +7V
Supply Voltage (VDDQ) ..................................... –0.3V to +7V
Enable Input Voltage (VEN).............................. –0.3V to +7V
Lead Temperature (soldering, 10 sec.)...................... 265°C
Storage Temperature (TS).........................–65°C to +150°C
EDS Rating(3) ................................................................+2kV
Supply Voltage (VCC).......................................... +3V to +6V
Supply Voltage (VDDQ) ................................... +0.75V to +6V
Enable Input Voltage (VEN)..................................... 0V to VIN
Junction Temperature (TJ) ........................ –40°C to +125°C
Junction Thermal Resistance
MSOP (θJA) ...................................................130.5°C/W
MSOP (θJC) .....................................................42.6°C/W
Electrical Characteristics(4)
VDDQ = 1.35V; TA = 25°C, bold values indicate –40°C ≤ TJ ≤ +125°C, unless noted.
Parameter
Min
Typ
Max
Units
-1%
0.5VDDQ
+1%
V
Sourcing; 100mA to 3A
-5
-10
0.4
+5
+10
mV
mV
Sinking; -100mA to -3A
-5
-10
0.4
+5
+10
mV
mV
35
70
100
µA
µA
10.5
20
25
mA
mA
Condition
VREF Voltage Accuracy
VTT Voltage Accuracy (Note 5)
Supply Current (IDDQ)
VEN = 1.2V (controller ON)
No Load
Supply Current (ICC)
No Load
ICC Shutdown Current (Note 6)
VEN = 0.2V (controller OFF)
45
90
nA
Start-up Time (Note 7)
VCC = 5V external bias; VEN = VCC
8
15
30
µs
µs
Enable Input
Enable Input Threshold
Regulator Enable
Regulator Shutdown
0.3
V
35
mV
VIL < 0.2V (controller shutdown)
0.011
µA
VIH > 1.2V (controller enable)
5.75
µA
4.97
V
Enable Hysteresis
Enable Pin Input Current
V
1.2
Driver
High Side Gate Drive Voltage
Low Side Gate Drive Voltage
High Side MOSFET Fully ON
4.8
0.03
High Side MOSFET Fully OFF
Low Side MOSFET Fully ON
4.8
Low Side MOSFET Fully OFF
0.2
4.97
0.03
V
V
0.2
Notes:
1. Exceeding the absolute maximum rating may damage the device.
2. The device is not guaranteed to function outside its operating rating.
3. Devices are ESD sensitive. Handling precautions recommended. Human body model, 1.5kΩ in series with 100pF.
4. Specification for packaged product only.
5. The VTT voltage accuracy is measured as a delta voltage from the reference output (VTT - VREF).
6. Shutdown current is measured only on the VCC pin. The VDDQ pin will always draw a minimum amount of current when voltage is applied.
April 2009
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Micrel, Inc.
MIC5163
7. Start-up time is defined as the amount of time from EN = VCC to HSD = 90% of VCC
Test Circuit
MIC5163
VDDQ = 0.75-2.5V
VDDQ
SUD50N02-06P
VTT = 0.5*VDDQ
HD
VCC
VCC = 5V
EN
220µF
EN
LD
COMP VREF
10µF
470pF
FB
120pF
COUT = 3*560µF
GND
10k
Figure 1. Test Circuit
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MIC5163
200
180
160
140
VIN=0.75V
EN TH ON
vs. Input Voltage
10
9.5
9
8.5
VTT-VREF (V)
0.6
April 2009
120
80
Room Temp
0
0
120
80
100
60
40
2
3
4
5
INPUT VOLTAGE (V)
6
EN TH ON
vs. Temperature
VIN=2.5V
VIN=1.35V
0.7
0.6
-3A
-0.1A
0.1A
0.001
5
120
80
100
60
40
TEMPERATURE (°C)
120
80
100
60
40
TEMPERATURE (°C)
VTT-VREF
vs. Temperature
3A
20
0.5
6
0
2
3
4
5
INPUT VOLTAGE (V)
-20
1
VIN=0.75V
0.0015
0
0
Room Temp
1
125°C
20
6
20
0.05
-40
6.5
6
5.5
5
0
-40°C
-20
2
3
4
5
INPUT VOLTAGE (V)
-40°C
0.9
0.0005
125°C
1
0.1
EN TH ON (V)
8
7.5
7
-40
EN TH ON (V)
Room Temp
0.4
0
0.15
0.8
0.002
0.7
0.5
125°C
0.2
VIN=6V
0.0025
-40°C
0.8
0.25
HD Prop Delay
vs. Input Voltage
TEMPERATURE (°C)
0.9
100
0
VTT-VREF (V)
HD PROP DELAY (µs)
120
80
100
VIN=2.5V
60
VIN=6V
0.3
ICC Shutdown Current
vs. Input Voltage
TEMPERATURE (°C)
VIN=1.35V
40
VIN=2.5V
0.05
6
VIN=0.75V
20
VIN=1.35V
0.1
HD Prop Delay
vs. Temperature
VIN=6V
ICC CURRENT (µA)
0.15
60
2
3
4
5
INPUT VOLTAGE (V)
0.2
0
1
0
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
-40
HD PROP DELAY (µs)
9.5
0
TEMPERATURE (°C)
0.25
-40
125°C
0.3
9.5
6
ICC Shutdown Current
vs. Temperature
40
10
2
3
4
5
INPUT VOLTAGE (V)
-20
1
0
Room Temp
VIN=1.35V
10
VIN=0.75V
-20
ICC SHUTDOWN CURRENT (µA)
10.5
VIN=2.5V
10.5
-40
120
80
100
60
40
0
20
-40°C
-20
ICC CURRENT (µA)
11
VIN=6V
125°C
60
40
20
0
0
TEMPERATURE (°C)
ICC Current
vs. Input Voltage
11
Room Temp
120
100
80
VIN=0.75V
ICC Current
vs. Temperature
-40°C
20
VIN=2.5V
VIN=1.35V
IDDQ Current
vs. Input Voltage
ICC SHUTDOWN CURRENT (µA)
IDDQ CURRENT (µA)
VIN=6V
-20
200
180
160
140
120
100
80
60
40
20
0
IDDQ Current
vs. Temperature
-40
IDDQ CURRENT (µA)
Typical Characteristics
0.005
0.004
0.003
0.002
VTT-VREF
vs. Load @25Deg
VIN=6V
0.001
0
-0.001
VIN=0.75V
-0.002
-0.003
-0.004
-0.005
-3
-2
VIN=1.35V
VIN=2.5V
-1
0
1
LOAD (A)
2
3
M9999-042209-A
Micrel, Inc.
MIC5163
Functional Characteristics
April 2009
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Micrel, Inc.
MIC5163
Functional Characteristics (continued)
April 2009
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MIC5163
Functional Diagram
VDDQ
VCC
R1
A
HD
-A
LD
VREF
R2
Shutdown
EN
GND
FB
COMP
Figure 2. MIC5163 Block Diagram
April 2009
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Micrel, Inc.
MIC5163
VREF
Two resistors dividing down the VDDQ voltage provide
VREF. The resistors are valued at around 17kΩ. A
minimum capacitor value of 120pF from VREF to ground
is mandatory.
Functional Description
The MIC5163 is a high performance linear controller,
utilizing scalable N-Channel MOSFETs to provide
JEDEC compliant bus termination. Termination is
achieved by dividing down the VDDQ voltage by a half,
providing the reference (VREF) voltage. The MIC5163
controls two external N-Channel MOSFETs to form two
separate regulators. It operates by switching between
either the high-side MOSFET or the low-side MOSFET,
depending on whether the current is being sourced to
the load or being sinked by the regulator.
VCC
VCC supplies the internal circuitry of the MIC5163 and
provides the drive voltage to enhance the external NChannel MOSFETs. A small 1μF capacitor is
recommended for bypassing the VCC pin.
Feedback and Compensation
The feedback provides the path for the error amplifier to
regulate the VTT. An external resistor must be placed
between the feedback and VTT. Feedback resistor values
should not exceed 10kΩ and compensation capacitors
should not be less than 40pF.
VDDQ
The VDDQ pin on the MIC5163 provides the source
current through the high side N-Channel and the
reference voltage to the device. The MIC5163 can
operate at VDDQ input voltages as low as 0.75V. A
bypass capacitance will increase performance by
improving the source impedance at higher frequencies.
Enable
The MIC5163 features an active high enable input. In the
off mode state, leakage currents are reduced to
microamperes. The enable input has thresholds
compatible with TTL/CMOS for simple logic interfacing.
The enable pin can be tied directly to VDDQ or VCC for
functionality.
VTT
VTT is the actual termination point. VTT is regulated to
VREF. Due to high speed signaling, the load current seen
by VTT is constantly changing. To maintain adequate
large signal transient response, Oscons and ceramics
are recommended on VTT. The Oscon capacitors provide
bulk charge storage while the smaller ceramic capacitors
provide current during the fast edges of the bus
transition.
April 2009
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M9999-042209-A
Micrel, Inc.
MIC5163
on DDR3, the MIC5163 is also capable of providing bus
terminations for DDR, DDR2 and GDDR3/4/5.
Application Information
Synchronous Dynamic Random Access Memory
(SDRAM) has continually evolved over the years to keep
up with ever-increasing computing needs. The latest
addition to SDRAM technology is DDR3 SDRAM. DDR3
SDRAM is the third generation of the DDR SDRAM
family and offers improved power savings, higher data
bandwidth and enhanced signal quality with multiple ondie termination (ODT) selection. In DDR3 SDRAM the
values of the ODT are based on the value of an external
resistor. In addition to using this external resistor for
setting the ODT value, it is also used for calibrating the
ODT value so that it maintains its resistance value to
within a 10% tolerance.
To improve signal integrity and support higher frequency
operations, the JEDEC committee defined a fly-by
termination scheme used with the clocks, the command
bus and address bus signals. The fly-by topology
reduces simultaneous switching noise (SSN) by
deliberately causing flight-time skew between the data
and strobes at every DRAM as the clock, address and
command signals traverse the DIMM.
The DDR3 SDRAM uses a programmable impedance
output buffer. Currently, there are two drive strength
settings, 34Ω and 40Ω. The 40Ω drive strength setting is
currently a reserved specification defined by JEDEC, but
available on the DDR3 SDRAM.
FPGA
VDDQ
The VDDQ pin on the MIC5163 provides the source
current through the high side N-Channel and the
reference voltage to the device. The MIC5163 can
operate at VDDQ voltages as low as 0.75V. Due to the
possibility of large transient currents being sourced from
this line, significant bypass capacitance will increase
performance by improving the source impedance at
higher frequencies. Since the reference is simply VDDQ/2,
perturbations on the VDDQ will also appear at half the
amplitude on the reference. For this reason, low ESR
capacitors such as ceramics or Oscons are
recommended on VDDQ.
VTT
VTT is the actual termination point. VTT is regulated to
VREF. Due to high speed signaling, the load current seen
by VTT is constantly changing. To maintain adequate
large signal transient response, Oscons and ceramics
are recommended on VTT. The proper combination and
placement of the Oscon and ceramic capacitors is
important to reduce both ESR and ESL such that highcurrent high-speed transients do not exceed the dynamic
voltage tolerance requirement of VTT. The Oscon
capacitors provide bulk charge storage while the smaller
ceramic capacitors provide current during the fast edges
of the bus transition. Using several smaller ceramic
capacitors distributed near the termination resistors is
typically important to reduce the effects of PCB trace
inductance.
DDR3 DIMM
DDR3 Component
Driver
Driver
RS
VREF = 0.75V
3” Trace Length
VREF = 0.75V
Receiver
Receiver
VREF
Two resistors dividing down the VDDQ voltage provide
VREF (Figure 5). The resistors are valued at around
17kΩ. A minimum capacitor value of 120pF from VREF to
ground is required to remove high frequency signals
reflected from the source. Large capacitance values
(>1500pF) should be avoided. Values greater than
1500pF slow down VREF and detract from the reference
voltage’s ability to track VDDQ during high speed load
transients.
DDR3 DIMM
DDR3 Component
FPGA
Driver
Driver
RS
VREF = 0.75V
Receiver
3” Trace Length
VREF = 0.75V
Receiver
Figure 3. Dynamic OCT between Stratix III/IV
FPGA Devices
The MIC5163 is a high performance linear controller that
utilizes scalable N-Channel MOSFETs to provide
JEDEC compliant bus termination. Termination is
achieved by dividing down the VDDQ voltage by half to
provide the reference (VREF) voltage. An internal error
amplifier compares the termination voltage (VTT) and
VREF, controlling two external N-Channel MOSFETs to
sink and/or source current to maintain a termination
voltage (VTT) equal to VREF. The N-Channels receive
their enhancement voltage from a separate VCC pin on
the device. Although the general discussion is focused
April 2009
U1
MIC5163
VDDQ = 1.2V
VCC
100µF
6.3V
100µF
6.3V
EN
EN
VREF
1µF
10V
120pF
GND
SUD50N02-06P
VDDQ
VCC = 5V
VTT = 0.6V
HSD
LSD
COMP
220pF
GND FB
100µF
6.3V
100µF
6.3V
GND
Figure 4. MIC5163 as a DDR3 Memory Termination Device
for 7A Application
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MIC5163
compatible with TTL/CMOS for simple logic interfacing.
The enable pin can be tied directly to VDDQ or VCC for
functionality. Do not float the enable pin. Floating this pin
causes the enable to be in an indeterminate state.
VDDQ
VREF
120pF
Input Capacitance
Although the MIC5163 does not require an input
capacitor for stability, using one greatly improves device
performance. Due to the high-speed nature of the
MIC5163, low ESR capacitors such as Oscon and
ceramics are recommended for bypassing the input. The
recommended value of capacitance will depend greatly
on the proximity to the bulk capacitance. Although a
10μF ceramic capacitor will suffice for most applications,
input capacitance may need to be increased in cases
where the termination circuit is greater than 1-inch away
from the bulk capacitance.
GND
Figure 5. VDDQ Divided Down to Provide VREF
VREF can also be manipulated for different applications.
A separate voltage source can be used to externally set
the reference point, bypassing the divider network. Also,
external resistors can be added from VREF-to-ground or
VREF-to-VDDQ to shift the reference point up or down.
Output Capacitance
Large, low ESR capacitors are recommended for the
output (VTT) of the MIC5163. Although low ESR
capacitors are not required for stability, they are
recommended to reduce the effects of high-speed
current transients on VTT. The change in voltage during
the transient condition will be the effect of the peak
current multiplied by the output capacitor’s ESR. For that
reason, Oscon type capacitors and ceramic are excellent
choices for this application. Oscon capacitors have
extremely low ESR and a large capacitance-to-size ratio.
Ceramic capacitors are also well suited to termination
due to their low ESR. These capacitors should have a
dielectric rating of X5R or X7R. Y5V and Z5U type
capacitors are not recommended, due to their poor
performance at high frequencies and over temperature.
The minimum recommended capacitance for a 3.5A
peak circuit is 100μF. Output capacitance can be
increased to achieve greater transient performance.
VCC
VCC supplies the internal circuitry of the MIC5163 and
provides the drive voltage to enhance the external NChannel MOSFETs. A small 1μF capacitor is
recommended for bypassing the VCC pin. The minimum
VCC voltage should be a gate-source voltage above VTT
without exceeding 6V. For example, on an DDR3
compliant terminator, VDDQ equals 1.5V and VTT equals
0.75V. If the N-Channel MOSFET selected requires a
gate source voltage of 2.5V, VCC should be a minimum
of 3.25V
Feedback and Compensation
The feedback provides the path for the error amplifier to
regulate VTT. An external resistor must be placed
between the feedback and VTT. This allows the error
amplifier to be correctly externally compensated. For
most applications, a 510Ω resistor is recommended. The
COMP pin on the MIC5163 is the output of the internal
error amplifier. By placing a capacitor and resistor
between the COMP pin and the feedback pin, this
coupled with the feedback resistor, places an external
pole and zero on the error amplifier. With a 510Ω
feedback resistor, a minimum 220pF capacitor is
recommended for a 3.5A peak termination circuit. An
increase in the load will require additional N-Channel
MOSFETs and/or increase in output capacitance may
require feedback and/or compensation capacitor values
to be changed to maintain stability. Feedback resistor
values should not exceed 10kΩ and compensation
capacitors should not be less than 40pF.
MOSFET Selection
The MIC5163 utilizes external N-Channel MOSFETs to
sink and source current. MOSFET selection will settle to
two main categories: size and gate threshold (VGS).
MOSFET Power Requirements
One of the most important factors is to determine the
amount of power the MOSFET is going to be required to
dissipate. Power dissipation in a DDR3 circuit will be
identical for both the high side and low side MOSFETs.
Since the supply voltage is divided by half to supply VTT,
both MOSFETs have the same voltage dropped across
them. They are also required to be able to sink and
source the same amount of current (for either all 0s or all
1s). This equates to each side being able to dissipate
the same amount of power. Power dissipation
calculation for the high-side MOSFET is as follows:
Enable
The MIC5163 features an active high enable input. In the
off mode state, leakage currents are reduced to
microamperes. The enable input has thresholds
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MIC5163
PD = (VDDQ − VTT) × I_SOURCE
Where I_source is the average source current. Power
dissipation for the low-side MOSFET is as follows:
°C
W
This shows that our total thermal resistance must be
better than 68.57°C/W. Since the total thermal
resistance is a combination of all the individual thermal
resistances, the amount of heat sink required can be
calculated as follows:
θ JA = 68.57
PD = VTT × I_SINK
Where I_sink is the average sink current.
In a typical 3.5A peak DDR3 circuit, power considerations for MOSFET selection would occur as follows.
θSA = θJA − (θJC + θCS)
In our example:
PD = (VDDQ −VTT) × I_SOURCE
PD = (1.5V −0.75V) × 1.75A
θSA = θJA − (θJC + θCS)
PD = 1.3125 W
This typical DDR3 application would require both highside and low-side N-Channel MOSFETs to be able to
handle 1.3125 Watts each. In applications where there is
excessive power dissipation, multiple N-Channel
MOSFETs may be placed in parallel. These MOSFETs
will share current, distributing power dissipation across
each device.
The maximum MOSFET die (junction) temperature limits
maximum power dissipation. The ability of the device to
dissipate heat away from the junction is specified by the
junction-to-ambient (θJA) thermal resistance. This is the
sum of junction-to-case (θJC) thermal resistance, caseto-sink (θCS) thermal resistance and sink-to-ambient
(θSA) thermal resistance;
Where TJ is the maximum junction temperature, TA is the
maximum ambient temperature and PD is the power
dissipation.
In our example:
TJ − T A
PD
θ JA =
150°C − 60°C
1.3125W
April 2009
θ SA = 66.57
°C
W
MOSFET Gate Threshold
N-Channel MOSFETs require an enhancement voltage
greater than its source voltage. Typical N-Channel
MOSFETs have a gate-source threshold (VGS) of 1.8V
and higher. Since the source of the high side N-Channel
is connected to VTT, the MIC5163 VCC pin requires a
voltage equal to or greater than the VGS voltage. For
example, our DDR3 termination circuit has a VTT voltage
of 0.75V. For an N-Channel that has a VGS rating of
2.5V, the VCC voltage can be as low as 3.25V. With an
N-Channel that has a 4.5V VGS, the minimum VCC
required is 5.25V. Although these N-Channels are driven
below their full enhancement threshold, it is
recommended that the VCC voltage has enough margin
to be able to fully enhance the MOSFETs for large signal
transient response. In addition, low gate thresholds
MOSFETs are recommended to reduce the VCC
requirements.
TJ − T A
PD
θ JA =
°C ⎛
°C
°C ⎞
− ⎜ 1 .5
+ 0 .5
⎟
W ⎝
W
W⎠
In most cases, case-to-sink thermal resistance can be
assumed to be about 0.5°C/W.
The DDR3 termination circuit for our example, using 2 Dpack N-Channel MOSFETs (one high side and one on
the low side) will require at least a 43°C/W heat sink per
MOSFET. This may be accomplished with an external
heat sink or even just the copper area that the MOSFET
is soldered to. In some cases, airflow may also be
required to reduce thermal resistance.
θJA = θJC + θCS + θSA
In our example of a 3.5A peak DDR3 termination circuit,
we have selected a D-pack N-Channel MOSFET that
has a maximum junction temperature of 150°C. The
device has a junction-to-case thermal resistance of
1.5°C/W. Our application has a maximum ambient
temperature of 60°C. The required junction-to-ambient
thermal resistance can be calculated as follows:
θ JA =
θ SA = 68.57
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MIC5163
Design Example
J1
EN
J8
CIN
VDDQ
PVin
16
15
9
PGnd
PVin
PGnd
SGnd
PGnd
PVin
1
22
TP4
1
4
R2 - 698
C23
120pF
19
18
C7 - 100pF, 50V
1
1
2
2
J22
VTT
1
3
LSD
2
TP21
21
20
HSD
GND
9
Q22
SUD50N02-06
1
8
3
1
TP3
C10
47µF
6.3V
3
1
C9
47µF
6.3V
TP23 TP24
EN
+ C26
100µF
6.3V
R23
MIC5163-YMM
C27
C32
100µF
6.3V
4
2
R3 - 20K
C14
VCC
R24
J24
EN
2
1
C6 - 39pF, 25V
23
2
24
C22
1µF
10V
Q21
VREF
Comp
GND
2
U21
PGND
1
25
27
28
29
30
31
26
PGnd
SW
SW
SW
SW
PGnd
PGnd
FB
CF
SW
8
R4
47.5K
J5
POR
Comp
POR
14
7
RC
SW
6
SVin
U1
22950_32L_5x5YML
Dly
13
C12 - 10nF, 50V
C11
1nF, 50V
EN
SW
5
SW
4
PVin
12
3
J23
C5
10µF, 6.3V
TP1
VIN
PVin
PVin
PGnd
J4
RC
PVin
11
2
10
1
PGnd
1
TP1
32
2
1 TP5 2
3
4
J3
DLY
2
C2 - 22µF, 6.3V
C1 - 22µF, 6.3V
SUD50N02-06
2
3
C21
100µF
6.3V
C30
100µF
6.3V
C31
2700µF
2.5V
VDDQ
+
TP22
2
L1
1µH, 17Ainductor
1000uF, 6.3V
FB
7
6
C24 - 220pF
R22
1K
R21
5
SW
1
R5
100K
VIN
J10
C13
1nF, 50V
2
2N2007E
Q1
1
J2
ShDn
VIN
3
GND
J26
GND
17
GND
C8 - 390pF, 50V
C4
22µF, 6.3V
C3 - 22µF, 6.3V
PGND
MIC5163 As a DDR3 Memory Termination Device for 3.5A Application
Bill of Materials
Item
C1, C2,
C3, C4
Part Number
Manufacturer
GRM21BR60J226ME39L
Murata(1)
C2012X5R0J226K
08056D226MAT2A
GRM188R60J106ME47D
C5
C6
C7
C8
AVX
Murata
AVX(3)
Vishay Vitramon
1
10 µF, 6.3V, X5R, 0603
39pF, 25V, X7R, 0603
TDK(2)
VJ0603Y101KXAAT
Vishay Vitramon(4)
100pF, 50V, 0603 ceramic cap
1
VJ0603Y391KXAAT
(4)
390pF, 50V, 0603 ceramic cap
1
47 µF,6.3V, 1206
or
Vishay Vitramon
(1)
Murata
C3216X5R0J476M
TDK(2)
12066D476MAT2A
AVX(3)
or
(4)
VJ0603Y102KXXMB
Vishay Vitramon
Vishay Vitramon(4)
C26
0603ZD105KAT2A
GRM188R61A105K
VJ0603A121KXXAT
AVX
Vishay
VJ0603A221KXXAT
Vishay(4)
120pF, 25V, 0603 ceramic cap
220pF, 25V, 0603 ceramic cap
(3)
AVX
AVX(3)
100µF, 6.3V, 7374 Tent
C27
April 2009
1
(4)
AVX(3)
06033C221JAT2A
2
1µF, 10V 0603 ceramic cap
(1)
06033A121JAT2A
NOSD107M006R0080
1nf, 50V, 0603 ceramic cap
10nf, 50V, 0603 ceramic cap
(3)
Murata
or
2
VJ0603Y103KXXMB
C24
1
C1608C0G1H390J
C12
C23
or
or
(4)
C11, C13
C22
or
or
(1)
06036D106MAT2A
VJ0603Y390KXXMB
22µF, 6.3V, X5R, 0805
(3)
TDK(2)
Qty.
4
(2)
C1608X5R0J106K
GRM31CR60J476ME19L
C9, C10
TDK
Description
1
or
1
or
1
or
1
N.U. 0603 ceramic cap
13
M9999-042209-A
Micrel, Inc.
MIC5163
Item
Part Number
Manufacturer
Description
C30, C32,
C21
18126D107MAT
AVX(3)
100µF, 6.3V, 1812 ceramic cap
3
C31
2SEPC2700M
Sanyo(5)
2700µF, 2.5V Oscon Cap
1
CIN
597D108X06R3R2T
Vishay(4)
1000µF, 6.3V, R-case
1
L1
CEP125HNP-1R0-MC
1µH, 17A inductor
1
Q1
2N7002E(SOT-23)
Vishay(4)
Signal MOSFET-SOT-236
1
Q21, Q22
SUD50N02-06P
Vishay(4)
Low VGS(th) N-Channel 20-V (D-S)
2
R1
CRCW06031101FRT1
Vishay Dale(4)
510Ω (0603 size), 1%
1
CRCW06036980FRT1
(4)
698Ω (0603 size), 1%
1
R2
Sumida
(6)
Qty.
Vishay Dale
(4)
R3
CRCW06032002FRT1
Vishay Dale
R4
CRCW06034752FRT1
Vishay Dale(4)
CRCW06031003FRT1
R5
20K, (0603 size), 1%
1
47.5K, (0603 size), 1%
1
(4)
100K (0603 size), 1%
1
(4)
510Ω (0805 size), 1%
1
1K (0603 size), 1%
1
Vishay Dale
R21
CRCW0805510RFKTA
Vishay Dale
R22, R24
CRCW06031K00FKTA
Vishay Dale(4)
R23
U1
U21
NU 0603
MIC22950YML
MIC5163YMM
Micrel
(7)
Buck Regulator
1
Micrel
(7)
Dual Regulator Controller for DDR3
1
Notes:
1. Murata: www.murata.com.
2. TDK: www.tdk.com.
3. AVX: www.avx.com.
4. Vishay: www.vishay.com.
5. Sanyo: www.sanyo.com
6. Sumida: www.sumida.com
7. Micrel, Inc.: www.micrel.com.
April 2009
14
M9999-042209-A
Micrel, Inc.
MIC5163
Package Information
10-Pin MSOP (MM)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its
use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2009 Micrel, Incorporated.
April 2009
15
M9999-042209-A