Micrel, Inc. 3.3V, PRECISION, 33MHz to 500MHz PROGRAMMABLE LVPECL AND LVDS BUS CLOCK SYNTHESIZER Precision Edge® Precision Edge® SY89532/33L SY89532L SY89533L FEATURES Integrated synthesizer plus fanout buffers, clock Precision Edge® drivers , and translator in a single 64-pin package 3.3V ±10% power supply Low jitter: <50ps cycle-to-cycle Low pin-to-pin skew: <50ps 33MHz to 500MHz output frequency range Direct interface to crystal: 14MHz to 18MHz LVPECL output (SY89532L), LVPECL/LVDS outputs (SY89533L) TTL/CMOS compatible control logic 3 independently programmable output frequency banks: • 9 differential output pairs @BankB (LVPECL/LVDS) • 2 differential output pairs @BankA (LVPECL) • 2 differential output pairs @BankC (LVPECL) ExtVCO input allows synthesizer and crystal interface to be bypassed Available in 64-pin EPAD-TQFP DESCRIPTION The SY89532 and SY89533L programmable clock synthesizer/drivers are a 3.3V, high-frequency, precision PLLbased clock driver family optimized for multi-frequency, multiprocessor server and synchronous computing applications that require the highest precision. These devices integrate the following blocks into a single monolithic IC: • • • • PLL (Phase-Lock-Loop)-based synthesizer Fanout buffers Clock generator (dividers) Logic translation (LVPECL, LVDS) This level of integration minimizes the additive jitter and part-to-part skew associated with the discrete alternative, resulting in superior system-level timing as well as reduced board space and power. For applications that must interface to a reference clock, see the SY89534/5. PRODUCT SELECTION GUIDE APPLICATIONS Servers Input Output Workstations Device Parallel processor-based systems SY89532L X LVPECL LVPECL LVPECL Other high-performance computing SY89533L X LVPECL Communications Crystal Reference BankA BankB LVDS BankC LVPECL SY89534L(1) X LVPECL LVPECL LVPECL SY89535L(1) X LVPECL LVDS LVPECL Note: 1.Refer to SY89534/35L data sheet for details. Precision Edge is a registered trademark of Micrel, Inc. M9999-010808 [email protected] or (408) 955-1690 Rev.: F 1 Amendment: /0 Issue Date: January 2008 Precision Edge® SY89532/33L Micrel, Inc. PACKAGE/ORDERING INFORMATION NC GND VCCA VCC_LOGIC VCC_LOGIC OUT_SYNC FSEL_A0 FSEL_A1 FSEL_A2 VCCOA QA0 /QA0 QA1 /QA1 VCCOB QB0 Ordering Information(1) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC NC NC VCO_SEL /EXTVCO EXTVCO LOOP_REF LOOP_FILTER GND XTAL2 XTAL1 VBB_REF M(3) M(2) M(1) M(0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 /QB0 QB1 /QB1 QB2 /QB2 QB3 /QB3 QB4 /QB4 QB5 /QB5 QB6 /QB6 QB7 /QB7 QB8 /QC1 QC1 /QC0 QC0 VCCOC FSEL_C2 FSEL_C1 FSEL_C0 GND FSEL_B2 FSEL_B1 FSEL_B0 GND VCCOB VCCOB /QB8 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Part Number Package Type Operating Range Package Marking Lead Finish SY89532LHC H64-1 Commercial SY89532LHC Sn-Pb SY89532LHCTR(2) H64-1 Commercial SY89532LHC Sn-Pb SY89533LHC SY89533LHC Sn-Pb SY89533LHC Sn-Pb H64-1 Commercial SY89533LHCTR(2) H64-1 Commercial SY89532LHZ H64-1 Commercial SY89532LHZ with Pb-Free Pb-Free bar-line indicator Matte-Sn SY89532LHZTR(2, 3) H64-1 Commercial SY89532LHZ with Pb-Free Pb-Free bar-line indicator Matte-Sn SY89533LHZ H64-1 Commercial SY89533LHZ with Pb-Free Pb-Free bar-line indicator Matte-Sn SY89533LHZTR(2, 3) H64-1 Commercial SY89533LHZ with Pb-Free Pb-Free bar-line indicator Matte-Sn 64-Pin EPAD-TQFP (H64-1) Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs. FUNCTIONAL BLOCK DIAGRAM NC NC NC NC GND VCCA VCC_Logic VCC_Logic OUT_Sync FSEL_A0 (LSB) FSEL_A1 FSEL_A2 VCCOA QA0 /QA0 QA1 /QA1 VCCOB 1 2 3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 QB0 48 /QB0 3 VCO_SEL 4 /ExtVCO 5 ExtVCO 6 Loop Ref 7 Loop Filter 8 47 QB1 46 /QB1 GND XTAL2 0 = Internal VCO enabled 1 = Internal VCO disabled (default) VCO Select 44 /QB2 2x 3-Bit Divider A 2, 4, 6, 8, 10, 12,18 43 QB3 A EN 42 /QB3 Mux 1 9 Clock 10 Oscillator XTAL1 45 QB2 Buf Phase Detector 11 VBB_Ref 12 VCC–1.3V Reference Charge Pump Buf 41 QB4 5 40 /QB4 VCO 3-Bit Divider B 2, 4, 6, 8, 10, 12,18 (600MHz to 1000MHz) M-Divide 34, 36, 38, 40, 42 44, 48, 50, 52, 54 56, 60, 70, 72 600MHz to 1000MHz 9x 39 QB5 B EN 38 /QB5 37 QB6 3 36 /QB6 3-Bit Divider C 2, 4, 6, 8, 10, 12,18 (MSB) M3 13 M2 14 35 QB7 C EN 34 /QB7 M1 15 33 QB8 (LSB) M0 16 3 2x 32 /QB8 31 VCCOB 18 19 20 21 22 23 24 25 26 27 28 29 /QC1 QC1 /QC0 QC0 VCCOC FSEL_C2 FSEL_C1 FSEL_C0 (LSB) GND FSEL_B2 FSEL_B1 FSEL_B0 (LSB) GND M9999-010808 [email protected] or (408) 955-1690 17 2 30 VCCOB Precision Edge® SY89532/33L Micrel, Inc. PIN DESCRIPTION Power Pin Number Pin Name Functional Description 60, 61 VCC_Logic Power for Core Logic: Connect to 3.3V supply. 3.3V power pins are not internally connected on the die, and must be connected together on the PCB. 62 VCCA Power for PLL: Connect to “quiet” 3.3V supply. 3.3V power pins are not internally connected on the die, and must be connected together on the PCB. 55 30, 31, 50 VCCOA VCCOB 21 VCCOC 9, 25, 63, 29 (exposed pad) GND Power for Output Drivers: Connect all VCCO pins to 3.3V supply. VCCO pins are not connected internally on the die. Ground: Exposed pad must be soldered to a ground plane. Configuration Pin Number Pin Name Functional Description 4 VCO_SEL LVTTL/CMOS-Compatible Input: Selects between internal or external VCO. For external VCO, leave floating. Default condition is logic HIGH. Internal 25kΩ pull-up. When tied LOW, internal VCO is selected. 7 LOOP REF Analog Input/Output: Provides the reference voltage for PLL loop filter. 8 LOOP FILTER Analog Input/Output: Provides the loop filter for PLL. See “External Loop Filter Considerations” for loop filter values. 13,14,15,16 M (3:0) LVTTL/CMOS-Compatible Input: Used to change the PLL (Phase-Lock Loop) feedback divider. Internal 25kΩ pull-up. (M0 = LSB). Default is logic HIGH. See “Feedback Divide Select” table. 22, 23, 24 FSEL_C (2:0) LVTTL/CMOS-Compatible Input: Bank C post divide select. Internal 25kΩ pull-up. Default is logic HIGH. See “Post-Divide Frequency Select” table. 26, 27, 28 FSEL_B (2:0) LVTTL/CMOS-Compatible Input: Bank B post divide select. Internal 25kΩ pull-up. Default is logic HIGH. See “Post-Divide Frequency Select” table. 56, 57, 58 FSEL_A (2:0) LVTTL/CMOS-Compatible Input: Bank A post divide select. Internal 25kΩ pull-up. Default is logic HIGH. See “Post-Divide Frequency Select.” FSEL_A0 = LSB. 59 OUT_SYNC Banks A,B,C output synchronous control: (LVTTL/CMOS compatible). Internal 25kΩ pull-up. After any bank has been programmed, toggle with a HIGH-LOWHIGH pulse to resynchronize all output banks. Pin Number Pin Name Functional Description 1, 2, 3 NC 10, 11 XTAL2, XTAL1 12 VBB_REF 5, 6 /EXT_VCO, EXT_VCO 51, 52, 53, 54 QA1 to QA0 Bank A 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_A (0:2). Terminate outputs with 50Ω to VCC –2V. See “Output Termination Recommendations” section for termination detail. 32–49 QB8 to QB0 Bank B Output Drivers: SY89532: 100k LVPECL output drivers. SY89533: Differential LVDS outputs. See “Output Termination Recommendations” section for termination detail. Output frequency is controlled by FSEL_B (0:2). 17, 18, 19, 20 QC1 to QC0 Bank C 100k LVPECL Output Drivers: Output frequency is controlled by FSEL_C (0:2). Terminate outputs with 50Ω to VCC–2V. See “Output Termination Recommendations” section. 64 NC Input/Output M9999-010808 [email protected] or (408) 955-1690 No Connect: Leave floating. Crystal Input. Directly connect a series resonant crystal across inputs. Reference Output Voltage. Used for single-ended input. Maximum sink/source current = 0.5mA. Differential “Any In” Compatible Input Pair. Allows for external VCO connection. The “Any In” input structure accepts many popular logic types. See “Input Interface for ExtVCO Pins” section for intercace diagrams. Can leave unconnected if using internal VCO. No Connect: Leave floating. 3 Precision Edge® SY89532/33L Micrel, Inc. ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Value Unit All VCC VCC Pin Potential to Ground Pin –0.5 to +4.0 V VIN Input Voltage (except XTAL 1,2 pins) –0.5 to VCCI V VXTAL 1,2 XTAL 1, 2 Input Voltage (VCC–1.9V) to VCC V IOUT DC Output Current –50 ±10 mA mA TLEAD Lead Temperature (soldering, 20sec.) 260 °C Tstore Storage Temperature –65 to +150 °C θJA Package Thermal Resistance (Junction-to-Ambient) With Die attach soldered to GND: –Still-Air (TQFP) –200lfpm (TQFP) –500lfpm (TQFP) 23 18 15 °C/W °C/W °C/W 44 36 30 °C/W °C/W °C/W 4.3 °C/W –LVPECL outputs –LVDS outputs With Die attach NOT soldered to GND:(2) θJC –Still-Air (TQFP) –200lfpm (TQFP) –500lfpm (TQFP) Package Thermal Resistance (Junction-to-Case) Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. It is recommended that the user always solder the exposed die pad to a ground plane for enhanced heat dissipation. DC ELECTRICAL CHARACTERISTICS Power Supply TA = 0°C TA = +25°C TA = +85°C Symbol Parameter Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit VCCA(1) PLL and Logic Supply Voltage 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 V VCCOA/C Bank A and C VCC Output 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 V VCCOB Bank B VCC Output LVPECL/LVDS 3.0 3.3 3.6 3.0 3.3 3.6 3.0 3.3 3.6 V — — — 275 260 330 — — 225 285 260 330 — — — 300 260 330 mA mA VCC_LOGIC ICC Total Supply Current(2) SY89533L LVDS Notes: 1. VCCA, VCC_LOGIC, VCCOA/C. VCCOB are not internally connected together inside the device. They must be connected together on the PCB. 2. No load. Outputs floating, Banks A, B, and C enabled. M9999-010808 [email protected] or (408) 955-1690 4 Precision Edge® SY89532/33L Micrel, Inc. DC ELECTRICAL CHARACTERISTICS LVCMOS/LVTTL Input Control Logic TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit — 2.0 — — V VIH Input HIGH Voltage 2.0 — — 2.0 — VIL Input LOW Voltage — — 0.8 — — 0.8 — — 0.8 V IIH Input HIGH Current — — — — — 150 — — — µA IIL Input LOW Current — — — –300 — — — — — µA ExtVCO (pins 5, 6) INPUT (All VCC pins = +3.3V ±10%) TA = 0°C Symbol Parameter TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit 100(1) 200(2) — — — — 100(1) 200(2) — — — — 100(1) 200(2) — — — — mV mV Input HIGH Voltage — — VCC +0.3 — — VCC +0.3 — — VCC +0.3 V Input LOW Voltage –0.3 — — –0.3 — — –0.3 — — V Max. Unit VID Differential Input Voltage VIH VIL Notes: 1. VIN < 2.4V 2. VIN < VCC +0.3V 100K LVPECL Outputs TA = 0°C Symbol Parameter TA = +25°C Max. Min. Typ. TA = +85°C Min. Typ. VOH Output HIGH Voltage(1) Max. Min. Typ. VCC–1.075 — VCC–0.830 VCC–1.075 — VCC–0.830 VCC–1.075 — VCC–0.830 V VOL Output LOW Voltage(1) VCC–1.860 — VCC–1.570 VCC–1.860 — VCC–1.570 VCC–1.860 — VCC –1.570 V VBB Output Reference Voltage VCC–1.26 VCC–1.32 VCC–1.38 VCC–1.26 VCC–1.32 VCC–1.38 VCC–1.26 VCC–1.32 VCC–1.38 V Note: 1. 50Ω to VCC –2V. Banks A, B, and C enabled. LVDS Outputs (SY89533L) Bank B QB0:8(2) TA = 0°C Symbol Parameter Swing(2, 3) TA = +25°C TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit 250 — 450 250 — 450 250 — 450 mV VOD Output Voltage VOH Output HIGH Voltage — — 1.475 — — 1.475 — — 1.475 V VOL Output LOW Voltage 0.925 — — 0.925 — — 0.925 — — V VOCM Output Common Mode Voltage(2) 1.125 — 1.375 1.125 — 1.375 1.125 — 1.375 V ∆VOCM Change in Common Mode Voltage(2) –50 — 50 –50 — 50 –50 — 50 mV Notes: 2. 100Ω termination across differential pair. 3. VOD M9999-010808 [email protected] or (408) 955-1690 5 Precision Edge® SY89532/33L Micrel, Inc. AC ELECTRICAL CHARACTERISTICS VCC_LOGIC = VCCA = VCCOA/B/C = +3.3V ±10% TA = 0°C Symbol TA = +85°C Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit fIN Xtal Input Frequency Range(1) — — — 14 — 18 — — — MHz fOUT Output Frequency Range Internal VCO External VCO — — — — — — 33.33 — — — 500 622.08 — — — — — — MHz MHz 600 — 1000 600 — 1000 600 — 1000 MHz — — 1250 — — 1250 — — 1250 MHz — — — — — 50 — — 50 ps — — 0 60 50 150 — — 0 60 50 150 — — 0 60 50 150 ps ps tVCO Parameter TA = +25°C VCO Frequency Range External VCO Frequency tskew Device(2) Within Pin-to-Pin Skew, Bank-to-Bank (Within Same Logic Type) (Between Logic Types) Part-to-Part Skew(3) — — — — — 200 — — 200 ps tLOCK Maximum PLL Lock Time — — — — — 10 — — 10 ms tJITTER Cycle-to-Cyle Jitter(4) (pk-to-pk) — — — — 25 50 — — — ps (rms) — — — — 20 50 — — 50 ps Minimum Pulse Width — — — 50 — — 50 — — ns Target PLL Loop Bandwidth Feedback Divider Ratio: 72(6) Feedback Divider Ratio: 34(6) — — 1.0 2.0 — — — — 1.0 2.0 — — — — 1.0 2.0 — — MHz MHz Total Jitter(5) tpw (min) External VCO Clock Input — — 1.25 — — 1.25 — — 1.25 GHz tDC fOUT Duty Cycle — — — 45 50 55 45 50 55 % t r, t f Output Rise/Fall Time (20% to 80%) LVPECL_Out (SY89533L) LVDS_Out — — — — 400 450 — — 250 300 400 450 — — — — 400 450 tOUTPUT_RESET (See Timing Diagrams) — — — — — 10 — — — ns tHOLD_FSEL — — — 5 — — — — — ns tSETUP_FSEL — — — 5 — — — — — ns tOUTPUT_SYNC — — — 1 — — — — — VCO clock cycle FSEL-to-Valid Output Transition Time — — — — — 1 — — — µs tSETUP_OUT_SYNC — — — 500 — — — — — ps ps Notes: 1. Fundamental mode crystal. 2. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. 3. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. 4. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC =Tn–Tn+1 where T is the time between rising edges of the output signal. 5. Loop filter values shown in Figure 3. 6. Using recommended loop filter components. See “Functional Description, External Loop Filter Considerations.” M9999-010808 [email protected] or (408) 955-1690 6 Precision Edge® SY89532/33L Micrel, Inc. TIMING DIAGRAMS Conditions: Internal VCO, unless otherwise stated. VCO FSEL 001 010 FOUT OUT_SYNC tOUTPUT_SYNC tOUTPUT_RESET tHOLD_FSEL tSETUP_FSEL TIME Frequency Programming (Internal VCO Clock) VCO FSEL 001 010 FOUT OUT_SYNC tOUTPUT_SYNC tOUTPUT_RESET tHOLD_FSEL tSETUP_FSEL TIME Frequency Programming (External VCO Clock) VCO FSEL 001 010 FOUT OUT_SYNC fSEL to VALID OUTPUT TRANSITION TIME TIME Output Frequency Update to Valid Output M9999-010808 [email protected] or (408) 955-1690 7 Precision Edge® SY89532/33L Micrel, Inc. FUNCTIONAL DESCRIPTION External VCO Operation At the core of the SY89532/33L clock synthesizer is a precision PLL driven by 14MHz to 18MHz series resonant crystal. For users who wish to supply a TTL or LVPECL clock input, please use the SY89534L or SY89535L. The PLL output is sent to three banks of outputs. Each bank has its own programmable frequency divider, and the design is optimized to provide very low skew between banks, and very low jitter. If the designer wishes to use an external VCO, the VCO_SEL pin can be left floating or tied HIGH, and the external VCO signal is connected to the ExtVCO differential input pair. The ExtVCO input structure is designed to accept many popular logic types. See “Input Interface for ExtVCO Pins” section for interface diagrams. A SONET OC-48 compliant 622.08MHz clock is a good example of an application requiring an external VCO. For this application, use a VCXO to supply the 1244.16MHz. to the ExtVCO pins, and set VCO_SEL to HIGH. To save power and reduce noise, the internal VCO is shut down when VCO_SEL is HIGH. ExtVCO Input Interface The flexible ExtVCO inputs are designed to accept any differential or single-ended input signal within 300mV above VCC and 300mV below ground. Do not leave unused ExtVCO inputs floating. Tie either the true or complement inputs to ground, but not both. A logic zero is achieved by connecting the complement input to ground with the true input floating. For a TTL input, tie a 2.5kΩ resistor between the complement input and ground. See “Input Interface for ExtVCO Pins” section, Figures 5a through 5j. Input Levels LVDS, CML and HSTL differential signals may be connected directly to the ExtVCO inputs. Depending on the actual worst case voltage seen, the minimum input voltage swing varies as illustrated in the following table: PLL Programming and Operation IMPORTANT: If the internal VCO will be used, VCO_SEL must be tied LOW, and ExtVCO pins can be left unconnected. The internal VCO range is 600MHz to 1000MHz, and the feedback ratio is selectable via the MSEL divider control (M3:0 pins). If the designer wishes to use the internal VCO, the VCO_SEL pin must be tied low. The feedback ratio can be changed without powering the chip down. The PLL output is fed to three banks of outputs: Bank A, Bank B, and Bank C. Banks A and C each have two differential LVPECL output pairs. Bank B has nine differential output pairs. On the SY89532L, Bank B is LVPECL. On the SY89533L, Bank B is LVDS. Each bank has a separate frequency divider circuit that can be reprogrammed on the fly. The FSEL_x0:2 (where x is A,B, or C) pins control the divider value. The FSEL divider can be programmed in ratios from 2 to 18, and the outputs of Banks A,B, and C can be synchronized after programming by pulsing the OUT_SYNC pin HIGH-LOW-HIGH. To determine the correct settings for SY89532/33L follow these steps: 1. Refer to the "Suggested Selections for Specific Customer Applications" section for common applications, as well as the formula used to compute the output frequency. 2. Determine the desired output frequency, such as 66MHz. 3. Choose a crystal frequency between 14MHz and 18MHz. In this example, we choose 18MHz for the crystal frequency. This results in an input/output ratio of 66/18. 4. Refer to the "Feedback Divide Select Table" and the "Post-Divide Frequency Select Table" to find values for MSEL and FSEL such that MSEL/FSEL equals the same 66/18 ratio. In this example, values of MSEL=44 and FSEL=12 work. 5. Make sure that XTAL (the crystal frequency) multiplied by MSEL is between 600MHz and 1000MHz. The user may need to experiment with different crystal frequencies to satisfy these requirements. M9999-010808 [email protected] or (408) 955-1690 Input Voltage Range Minimum Voltage Swing 0 to 2.4V 100mV 0 to VCC +0.3 200mV VCC R2 1.5k EXTVCO R2 1.5k R1 1.05k /EXTVCO R1 1.05k GND Figure 1. Simplified Input Structure 8 Precision Edge® SY89532/33L Micrel, Inc. Crystal Input and Oscillator Interface External Loop Filter Considerations The SY89532/33L features a fully integrated on-board oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design, and thus, a series-resonant crystal is preferred, but not required. A parallel-resonant crystal can be used with the SY89532/ 33L with only a minor error in the desired frequency. A parallelresonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified, a few hundred ppm translates to kHz inaccuracies. In a general computer application this level of inaccuracy is immaterial. As the oscillator is somewhat sensitive to loading on its inputs, the user is advised to mount the crystal as close to the SY89532/33L as possible to avoid any board level parasitics. In addition, trace lengths should be matched. Figure 2 shows how to interface with a crystal. Table 1 illustrates the crystal specifications. Certain crystals may require a 10pf capacitor across XTAL1 and XTAL2 for proper operation. This is normally not required, but it is recommended that provisions be made for it. The SY89532/33L features an external PLL loop filter that allows the user to tailor the PLL’s behavior to their application and operating environment. We recommend using ceramic capacitors with NPO or X7R dielectric, as they have very low effective series resistance. For applications that require ultralow cycle-to-cycle jitter, use the components shown in Figure 3. The PLL loop bandwidth is a function of feedback divider ratio, and the external loop filter allows the user to compensate. For instance, the PLL’s loop bandwidth can be decreased by using a smaller resistor in the loop filter. This results in less noise from the PLL input, but potentially more noise from the VCO. Refer to “AC Electrical Characteristics” for target PLL loop bandwidth. The designer should take care to keep the loop filter components on the same side of the board and as close as possible to the SY89532/33L’s LOOP_REF and LOOP_FILTER pins. To insure minimal noise pick up on the loop filter, it is desirable to cut away the ground plane directly underneath the loop filter component pads and traces. However, the benefit may not be significant in all applications and one must be careful to not alter the characteristic impedance of nearby traces. R1 330 SY89532/33L C1 0.2µF XTAL2 (Pin 26, SOIC) XTAL 16.666MHz C2 470pF XTAL1 (Pin 25, SOIC) Loop Filter Optional Loop Reference Figure 3. External Loop Filter Connection Quartz Crystal Selection: (1) Raltron Series Resonant: AS-16.666-S-SMD-T-MI (2) Raltron Parallel Resonant: AS-16.666-18-SMD-T-MI Figure 2. Crystal Interface OUTPUT FREQUENCY: 14MHz-18MHz MODE OF OSCILLATION: FUNDAMENTAL Min. Typ. Max. Unit Frequency Tolerance @25°C — ±30 ±50 PPM Frequency Stability over 0°C to 70°C — ±50 ±100 ppm Operating Temperature Range –20 — +70 °C Storage Temperature Range –55 — +125 °C Aging (per yr/1st 3yrs) — — ±5 ppm Load Capacitance — 18 (or series) — pF Equivalent Series Resistance (ESR) — — 50 Ω Drive Level — 100 — µW Table 1. Quartz Crystal Oscillator Specifications M9999-010808 [email protected] or (408) 955-1690 9 Precision Edge® SY89532/33L Micrel, Inc. Power Supply Filtering Techniques output in the same manner as the normal output that is begin used. Unused LVPECL output pairs can be left floating. Unused LVDS output pairs (SY89533L) should be terminated w/100Ω across the pair. Unused output banks can be switched off by tying the appropriate FSEL pins to ground. Unused output pairs that are in a bank that is disabled can be left floating, regardless of output driver type. LVPECL operation: • Typical voltage swing is 700mVPP to 800mVPP into 50Ω. • Common mode voltage is VCC–1.3V, typical. • 100Ω termination across the output pair is NOT recommended for LVPECL. LVDS operation (Bank B, SY89533L): • Typical voltage swing is 250mVPP to 450mVPP into effective 50Ω. • Common mode voltage is 1.25V, typical. • 100Ω termination across differential output pair is fine. As with any high-speed integrated circuit, power supply filtering is very important. At a minimum, VCCA, VCC_Logic, and all VCCO pins should be individually connected using a via to the power supply plane, and separate bypass capacitors should be used for each pin. To achieve optimal jitter performance, each power supply pin should use separate instances of the circuit shown in Figure 4. “Power Supply” side Ferrite Bead* 22µF “Device” side VCC Pins 1µF *For VCC_Analog,VCC_TTL, VCC1, use ferrite bead = 200mA, 0.45 Murata P/N BLM21A1025 0.01µF DC, *For VCC_OUT use ferrite bead = 3A, 0.025 Murata, P/N BLM31P005 DC, Thermal Considerations *Component size: 0805 This part has an exposed die pad for enhanced heat dissipation. We strongly recommend soldering the exposed pad to a ground plane. Where this is not possible, we recommend maintaining at least 500lfpm air flow. For additional information on exposed-pad characteristics and implementation details, see Amkor Technology’s write-up at www.amkor.com. Figure 4. Power Supply Filtering Output Logic Characteristics See “Output Termination Recommendations” for illustrations. In cases where single-ended output is desired, the designer should terminate the unused complimentary POST-DIVIDE FREQUENCY SELECT TABLE (FSEL) FSEL_A2(1) (MSB) FSEL_A1(1) FSEL_A0(1) (LSB) 0 0 0 TBD 0 0 1 VCO ÷ 2 0 1 0 VCO ÷ 4 0 1 1 VCO ÷ 6 1 0 0 VCO ÷ 8 1 0 1 VCO ÷ 10 1 1 0 VCO ÷ 12 1 1 1 VCO ÷ 18 Note: 1. Same dividers apply to FSEL_B (0:2) and FSEL_C (0:2). M9999-010808 [email protected] or (408) 955-1690 10 Output Divider Precision Edge® SY89532/33L Micrel, Inc. FEEDBACK DIVIDE SELECT TABLE (MSEL) M3 M2 M1 M0 VCO Frequency(1) 0 0 0 0 Ref x 34 0 0 0 1 Ref x 36 0 0 1 0 Ref x 38 0 0 1 1 Ref x 40 0 1 0 0 Ref x 42 0 1 0 1 Ref x 44 0 1 1 0 Ref x 48 0 1 1 1 Ref x 50 1 0 0 0 Ref x 52 1 0 0 1 Ref x 54 1 0 1 0 Ref x 56 1 0 1 1 Ref x 60 1 1 1 0 Ref x 70 1 1 1 1 Ref x 72 Note: 1. Ref = Crystal Frequency. SUGGESTED SELECTIONS FOR SPECIFIC CUSTOMER APPLICATIONS Protocol Rate (MHz) FSEL (Post Divider) MSEL (Feedback Div.) XTAL (MHz) FOUT PCI 33 18 36 16.67 33 Fast Ethernet 100 6 40 15 100 1/8 FC 133 6 52 15.36 133 ESCON 200 4 50 16 200 FOUT = (XTAL x MSEL) FSEL Notes: 1. 600MHz < (XTAL x MSEL) < 1000MHz. 2. Where two settings provide the user with the identical desired frequency, the setting with the higher input reference frequency (and lower feedback divider) will usually have lower output jitter. However, the reference input frequency, as well as the VCO frequency, must be kept within their respective ranges. M9999-010808 [email protected] or (408) 955-1690 11 Precision Edge® SY89532/33L Micrel, Inc. INPUT INTERFACE FOR EXTVCO PINS VCC(DRIVER) VCC(532/3) ≥ VCC(DRIVER) VCC(532/3) ≥ VCC(DRIVER) VCC(DRIVER) TTL LVTTL EXTVCO /EXTVCO 2.5k 1% CML 102Ω 1% SY89532L SY89533L /EXTVCO SY89532L SY89533L Figure 5b. CML-DC Coupled Figure 5a. 5V, 3.3V “TTL” VCC(532/3) ≥ VCC(DRIVER) VCC(DRIVER) 2.3V to 2.7V EXTVCO EXTVCO VCC PECL /EXTVCO 2.5V LVTTL EXTVCO 50Ω 1% /EXTVCO 2.5k 1% 50Ω 1% SY89532L SY89533L SY89532L SY89533L VCC–2V Figure 5d. 3.3V LVPECL-DC Coupled Figure 5c. 2.5V “LVTTL” VCC VCC(DRIVER) VCC CML EXTVCO EXTVCO 102Ω 1% /EXTVCO HSTL 3.92kΩ 1% /EXTVCO 50Ω 50Ω SY89532L SY89533L SY89532L SY89533L Figure 5f. CML-AC Coupled–Short Trace Lengths Figure 5e. HSTL M9999-010808 [email protected] or (408) 955-1690 3.92kΩ 1% 12 Precision Edge® SY89532/33L Micrel, Inc. VCC VCC(DRIVER) 82Ω 1% 82Ω 1% VCC EXTVCO CML VCC /EXTVCO 130Ω 1% 130Ω 1% SY89532L SY89533L LVDS 100Ω 1% EXTVCO /EXTVCO SY89532L SY89533L Figure 5h. LVDS Figure 5g. CML-AC Coupled–Long Trace Lengths VDDQ VDDQ 105Ω 1% 105Ω 1% 105Ω 1% VCC EXTVCO SSTL_2 105Ω 1% EXTVCO SSTL_2 /EXTVCO /EXTVCO 100Ω 1% 100Ω 1% SY89532L SY89533L 100Ω 1% Figure 5i. SSTL_2 M9999-010808 [email protected] or (408) 955-1690 VCC 100Ω 1% Figure 5j. SSTL_3 13 SY89532L SY89533L Precision Edge® SY89532/33L Micrel, Inc. OUTPUT TERMINATION RECOMMENDATIONS +3.3V +3.3V ZO = 50Ω R1 130Ω R1 130Ω R2 82Ω R2 82Ω +3.3V ZO = 50Ω “Source” “Destination” VT = VCC –2V Figure 6. PECL Parallel Termination–Thevenin Equivalent +3.3V +3.3V ZO = 50Ω ZO = 50Ω 50Ω “Source” 50Ω 50Ω “Destination” VCC Rb C1 (optional) 0.01µF Figure 7. LVPECL Three-Resistor “Y–Termination” +3.3V +3.3V ZO = 50Ω 100Ω 1% ZO = 50Ω “Source” “Destination” Figure 8. SY89533L LVDS Differential Termination Notes: 1. PECL Y-termination is a power-saving alternative to Thevenin termination. 2. Place termination resistors as close to destination inputs as possible. 3. Rb resistor sets the DC bias voltage, equal to VT. For +3.3V systems Rb = 46Ω to 50Ω. M9999-010808 [email protected] or (408) 955-1690 14 Precision Edge® SY89532/33L Micrel, Inc. 64-PIN EPAD-TQFP (DIE UP) (H64-1) Package EP- Exposed Pad Die CompSide Island Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane PCB Thermal Consideration for 64-Pin EPAD-TQFP Package MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 TEL + 1 (408) 944-0800 FAX + 1 (408) 474-1000 WEB USA http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2005 Micrel, Incorporated. M9999-010808 [email protected] or (408) 955-1690 15