SY89531L Eval Board 5/20/#7AEA2

3.3V, PRECISION, 33MHz to 500MHz SY89531/2/3/4/5/6L
PROGRAMMABLE LVPECL, HSTL
EVALUATION
BOARD
AND LVDS BUS CLOCK SYNTHESIZER
FEATURES
DESCRIPTION
■ Integrated synthesizer plus fan out buffer, clock
generator (dividers), and translators in a 64-pin
package
■ 3.3V ±10% power supply
■ Low jitter: <50ps cycle-to-cycle jitter
■ Low within-device skew: <50ps
■ 33MHz to 500MHz output frequency range
■ Direct interface to crystal (SY89531/2/3L) from
14MHz to 18MHz (see SY89531/2/3L data sheet for
recommended crystal)
■ Reference (TTL/CML/LVPECL) input between 14MHz
to 160MHz for the SY89534/5/6L
■ TTL/CMOS control logic
■ Three independently programmable output
frequency banks:
• Two differential output pairs @ Bank A
• Nine differential output pairs @ Bank B
• Two differential output pairs @ Bank C
The SY89531/2/3/4/5/6L are precision, high-speed clock
synthesizers optimized for multi-frequency, multi-processor
server, and synchronous computing applications. This
document provides design and implementation information,
and a detailed description of the SY89531/2/3/4/5/6L
evaluation board. The evaluation board is intended to provide
a convenient test and evaluation platform for the SY89531/
2/3/4/5/6L Clock Synthesizer devices. One pair of outputs
is taken from Bank A, and Bank C, and two pairs from Bank
B for pin-to-pin skew measurements.
CH1
50Ω
Term.
Scope
CH2
TRIG
S9
VCCA
S13
GND
VCC_A
/A0 A0
Out Bank B /B3
Out Bank A
optional capacitor
50Ω
Term.
B3
X2
U1 SY89531L
Raltron
16.6MHz Series Crystal
/B4
X1
Out Bank C
B4
C0 /C0
VEE_GND
VLOGIC
S11
VCC_B
S15
VCC_C
Bank A — LVPECL
Bank B — HSTL
Bank C — LVPECL
RMS Jitter (1ps)
Cycle-to-Cycle Jitter
(4ps)RMS
CH1
50Ω
Term.
Wavecrest
DTS-2079
HP8596E
Spectrum Analyzer
Figure 1. SY89531L Evaluation Board and Test Set-Up
Rev.: A
1
Amendment: /0
Issue Date: May 2003
SY89531/2/3/4/5/6L Evaluation Board
Micrel
CH1
50
W
Term.
Scope
CH2
TRIG
S9
VCCA
S13
GND
VCC_A
/A0
S20
A0
Out Bank B /B3
Out Bank A
optional capacitor
S24
B3
X2
U1
SY89532L
X1
Raltron
/B4
50
W
Term.
S25
16.6MHz Series Crystal
Out Bank C
C0
B4
/C0
VEE_GND
S29
VLOGIC
VCC_B
Bank A Ð LVPECL
Bank B Ð LVPECL
Bank C Ð LVPECL
RMS Jitter (1ps)
S11
S15
VCC_C
Cycle-to-Cycle Jitter
(4ps)RMS
CH1
50
W
Wavecrest
DTS-2079
Term.
HP8596E
Spectrum Analyzer
Figure 2. SY89532L Evaluation Board and Test Set-Up
CH1
Scope
CH2
TRIG
S9
VCCA
S13
GND
VCC_A
/A0
S20
A0
Out Bank B /B3
Out Bank A
optional capacitor
S24
B3
X2
U1
SY89533L
X1
/B4
50
W
Term.
S25
50
W
Term.
Raltron
16.6MHz Series Crystal
Out Bank C
C0
B4
/C0
VEE_GND
S29
VLOGIC
Bank A Ð LVPECL
Bank B Ð LVDS
Bank C Ð LVPECL
S11
VCC_B
S15
VCC_C
RMS Jitter (1ps)
Cycle-to-Cycle Jitter
(4ps)RMS
CH1
50
W
Term.
Note:
Unused LVDS outputs need to
be terminated into 50W.
Wavecrest
DTS-2079
HP8596E
Spectrum Analyzer
Figure 3. SY89533L Evaluation Board and Test Set-Up
2
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SY89531/2/3/4/5/6L Evaluation Board
CH1
50
W
Term.
Scope
CH2
TRIG
S9
VCCA
S13
GND
VCC_A
S20
HP8133
/A0
Frequency Synthesizer
A0
Out Bank B /B3
Out Bank A
14MHz to 160MHz
S24
S5
B3
REF_CLK
OUT
U1
S7
SY89534L
/B4
/REF_CLK
/OUT
Out Bank C
C0
B4
/C0
VEE_GND
S25
S29
VLOGIC
VCC_B
Bank A Ð LVPECL
Bank B Ð LVPECL
Bank C Ð LVPECL
50
S11
S15
VCC_C
W
Term.
HP8596E
Spectrum Analyzer
Figure 4. SY89534L Evaluation Board and Test Set-Up
CH1
Scope
CH2
TRIG
S9
VCCA
S13
GND
VCC_A
S20
/A0
HP8133
A0
50
Out Bank B /B3
W
Term.
Out Bank A
Frequency Synthesizer
14MHz to 160MHz
S24
S5
U1
S7
SY89535L
/REF_CLK
/OUT
/B4
Out Bank C
C0
B4
/C0
VEE_GND
S25
50
S29
50
W
W
W
Term.
Term.
Term.
VLOGIC
Bank A Ð LVPECL
Bank B Ð LVDS
Bank C Ð LVPECL
50
S11
VCC_B
S15
VCC_C
W
Term.
Note:
Unused LVDS outputs need to
be terminated into 50W.
50
B3
REF_CLK
OUT
HP8596E
Spectrum Analyzer
Figure 5. SY89535L Evaluation Board and Test Set-Up
3
SY89531/2/3/4/5/6L Evaluation Board
Micrel
CH1
Scope
CH2
TRIG
S9
VCCA
S13
GND
VCC_A
HP8133
Frequency Synthesizer
14MHz to 160MHz
/A0 A0
Out Bank B /B3
Out Bank A
50Ω Term.
B3
50Ω Term.
/B4
50Ω Term.
S5
OUT
S7
/OUT
REF_CLK
U1 SY89536L
/REF_CLK
Out Bank C
B4
C0 /C0
VEE_GND
50Ω Term.
VLOGIC
VCC_B
S11
S15
VCC_C
Bank A — LVPECL
Bank B — HSTL
Bank C — LVPECL
50Ω
Term.
HP8596E
Spectrum Analyzer
Figure 6. SY89536L Evaluation Board and Test Set-Up
4
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SY89531/2/3/4/5/6L Evaluation Board
FUNCTIONAL DESCRIPTION
At the core of the SY89531/2/3L clock synthesizer is a
precision PLL driven by a 14MHz to 18MHz series resonant
crystal. For users who wish to supply a TTL/CML or LVPECL,
14MHz to 160MHz clock input, use the Micrel SY89534L,
SY89535L or SY89536L. The PLL output is sent to three
banks of outputs. Each bank has its own programmable
frequency divider, and the design is optimized to provide
very low skew between banks, and very low jitter generation.
The evaluation boards simplify test and measurement by
allowing easy setting of the M-Divider and post-dividers.
The evaluation board, however, does not allow external
VCOs to be evaluated. The VCO range is 600MHz to
1000MHz, and the feedback ratio is selectable via the
M-Divider control dip switches. In addition, the M-Divider
and post-dividers can be programmed on the fly and do not
need powering down during programming.
Power Supply
The SY89531/2/3/4/5/6L are 3.3V devices. Therefore,
VCCA, VCC_A, VCC_B, VCC_C, and Vlogic should be
connected to +3.3VDC and VEE_GND and GND should be
connected to 0VDC.
Board Layout
The evaluation board is constructed with FR-4 material
and is co-planar designed to minimize noise, achieve high
bandwidth, and minimize crosstalk.
LVPECL operation is typically 750mV PP into 50Ω.
Common mode is VCC–1.3V. Unused pairs of outputs do
not need to be terminated and do not add jitter. LVDS
operation, on the other hand, has a typical voltage swing of
350mV into 50Ω. Common mode voltage is 1.25VDC. LVDS
outputs are terminated with 100Ω across the pair. Unused
outputs must be terminated with 100Ω.
Test Description
This section contains step-by-step instructions for
evaluating the SY89531/2/3L in terms of spectral purity and
measurement of cycle-to-cycle jitter.
1. Connect VCCA, VCC_A, VCC_B, VCC _C, and Vlogic
to +3.3VDC.
2. Connect VEE_GND, and GND to 0VDC.
3. IMPORTANT (for SY89532L and SY89533L only)
Set B_logic to 0
Set XVCO to 0
Set XVCOB to 1
4. Configure test setup as shown in Figures 1 to 4.
5. Example Configuration:
Fcrystal = 16.6MHz (Raltron AS-SIM Series Resonance
Crystal)*
*NOTE: If a high frequency clock or pulse generator such
as a Agilent 8133 is used to drive the device, a 250ps
Transition Time Converter should be used before driving
the device.
M = 60
Post divider banks A to C = 18
If the above configuration is used, the expected frequency
will be 55.33MHz.
Layer Stack
L1
Signal/GND
L2
Impedance GND
L3
VCCA/Vlogic
L4
VCC_A/VCC_B/VCC_C
L5
VEE/GND
L6
Signal
SW2
Signal Inputs/Outputs
The SY89531L, SY89532L and SY89533L evaluation
boards have been designed with a 16.6MHz crystal input.
The SY89534L, SY89535L and SY89536L have been
designed to take a TTL/CML or LVPECL input between 14MHz
and 160MHz. In addition, Bank A, Bank B, and Bank C have
been pre-configured to illustrate the performance of the device.
See Table 1, Device Input and Output Signals.
Inputs
Device
Crystal
Reference
0
2. FSEL_B0
1
3. FSEL_B1
1
4. FSEL_B2
1
5. FSEL_C0
1
6. FSEL_C1
1
7. FSEL_C2
1
Outputs
BankA
BankB
BankC
SY89531L 16.6MHz
LVPECL HSTL
SY89532L 16.6MHz
LVPECL LVPECL LVPECL
SY89533L 16.6MHz
LVPECL LVDS
1. XVCOB
1
2. XVCO
0
3. FSEL_A0
1
LVPECL
4. FSEL_A1
1
LVPECL
5. FSEL_A2
1
LVPECL
14 to 160MHz LVPECL LVPECL LVPECL
SY89535L
14 to 160MHz LVPECL LVDS
14 to 160MHz LVPECL HSTL
SW3
LVPECL
SY89534L
SY89536L
1. B_logic
Table 1. Device Input and Output Signals
5
SY89531/2/3/4/5/6L Evaluation Board
Micrel
9. On the control panel, select the persist histogram
button.
10. Then select the horizontal histogram and set the
vertical and horizontal limits. Jitter information is
then shown at the bottom of the screen.
11. As a reminder, to minimize accumulated jitter,
always set the time delay to a minimum.
12. In addition, jitter is measured on the rising edge of a
waveform.
13. Further, the evaluation boards provide ports to
measure pin to pin skew using Bank B. Bank B has
B3P, B3N, B4P, and B4N pins connected to SMA20,
SMA24, SMA25, and SMA29.
14. To measure cycle-to-cycle jitter using a Wavecrest
DTS-2079 follow steps 15 to 22.
15. Double click on the Wavecrest icon and select clock
histogram.
16. Select CH1 input, refer to the test set-up figures.
17. To measure:
a. T2 – T1 select stop edges to skip = 0
SW4
1. M0
1
2. M1
1
3. M2
0
4. M3
1
Once dip switches SW2, SW3, and SW4 are set, check
current consumption it should be as follows:
Device
ICC (mA)
SY89531L
342
SY89532L
342
SY89533L
342
SY89534L
436
SY89535L
SY89536L
436
436
18.
19.
20.
21.
22.
b. T3 – T1 select stop edges to skip = 1
c. T4 – T1 select stop edges to skip = 2
d. T5 – T1 select stop edges to skip = 3
Set hits > 30,000.
Select “view accum hits.”
Set measure = period
Select pulse finds. Make sure min., and max.
voltages are correct.
Hit “run and plot information to screen.”
Figure 7. Spectral Plot Bank C
Output
Reference/Oscillator
Frequency
M-Divider
Min.
Max.
Frequency of VCO
(MHz)
Min.
Max.
Fmin = 14MHz
44
70
616
980
Ftyp = 16MHz
38
60
608
960
Fmax = 18MHz
34
54
612
972
Table 2. Valid M-Divider Settings
vs. VCO Frequency for the SY89531/32/33L
TIME (310ps/div.)
Frequency
Figure 8. Output Waveform Bank C
6. To measure non-correlated random jitter using a
Tektronix 11801B Digital Sampling Oscilloscope
follow step 7 to 12.
7. On the Tektronix scope, set acquisition mode to run.
8. Then press the autoset button located on the front
panel.
Predividers
M-Divider
Min. Max.
Freq. of VCO
(MHz)
Min. Max.
Fmin = 14MHz
1
44
70
616
980
Fmax = 160MHz
8
30
50
600
1000
Table 3. Valid M-Divider and Predivider Settings
vs. VCO Frequency for the SY89534/35/36L
6
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SY89531/2/3/4/5/6L Evaluation Board
FEEDBACK DIVIDE SELECT TABLE (M-DIVIDER)
M3
M2
M1
M0
VCO Frequency (1)
0
0
0
0
Ref × 34
0
0
0
1
Ref × 36
0
0
1
0
Ref × 38
0
0
1
1
Ref × 40
0
1
0
0
Ref × 42
0
1
0
1
Ref × 44
0
1
1
0
Ref × 48
0
1
1
1
Ref × 50
1
0
0
0
Ref × 52
1
0
0
1
Ref × 54
1
0
1
0
Ref × 56
1
0
1
1
Ref × 60
1
1
1
0
Ref × 70
1
1
1
1
Ref × 72
Table 4. M-Divider Settings
Note 1.
Ref = Crystal Frequency.
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SY89531/2/3/4/5/6L Evaluation Board
Micrel
FREQUENCY ASKED QUESTIONS
What Do I Do with the Exposed Pad on the Bottom of
the Package?
The purpose of the exposed pad at the bottom of the
package is to conduct heat more efficiently out of the
package. Solder or use thermal conductive epoxy. Although
the pad is connected to GND, there has not been any
degradation in either output generated jitter or input jitter
tolerance performance. In addition, the exposed pad is
directly connected to the chip ground internally. Make sure
the exposed pad ground and the device ground are the
same potential.
Also verify that the oscillator output has no “pedestals” in
the response due to improper impedance matching and/or
inadequate drive capability of the oscillator.
If the SY89531/2/3L experiences start-up problems, add
a 10pF capacitor across XTAL1, and XTAL2. Start-up
problems can be easily recognized. Start-up problems can
be seen as the VCO oscillating at either its maximum or
minimum frequency. Adding a capacitor across XTAL1 and
XTAL2 lowers the gain of the crystal oscillator driver if
electrical series resistance of the crystal is high, in addition
to snapping out an parasitic that maybe present.
As a general guideline, do not use CMOS-based PLLs to
drive the SY89534/5/6L. They almost always have too much
high frequency deterministic jitter for this application. Also
fanning out one oscillator to several locations on your board
is not a good idea. Crosstalk and inadequate drive can
adversely affect performance.
I Just Got my Evaluation Board and I Cannot Get
Anything to Work.
First check the power supplies. This evaluation board
uses one power supply. You should see a current draw of
about 342mA for the SY89532/3L and 436mA for
SY89534/5L when the part is running. After, check the
voltage swing levels of REFCLK.
Next, make sure that B_logic is set to 0, since it is really
used to ground the chip, and XVCO is set to 0 and XVCOb
is set to 1.
Aside from setting the M-Divider, and Post dividers
incorrectly, everything should operate as expected at this
point.
What Layout Tips Do You Have?
1.
Establish controlled impedance stripline, microstrip,
or co-planar construction techniques for high-speed
signal paths.
2.
All differential paths are critical timing paths, and
skew should be matched to within ±10ps.
3.
Signal trace impedance should not vary more than
±5%. If in doubt, perform TDR analysis of signal
traces.
4.
Maintain compact filter networks as close to filter
pins as possible.
5.
Provide ground plane relief under filter path to
reduce stray capacitance and be careful of crosstalk
coupling into the filter network.
6.
Maintain low jitter on the REFCLK input by isolating
the XTAL oscillator from power supply noise by
adequately decoupling.
7.
Keep XTAL oscillator close to SY89531/2/3/4/5/6L.
8.
Isolate the input, output, and REFCLK signal traces
from other clock and data signals on your board if
these other traces are within 3x the trace width.
Isolation can be achieved by putting ground traces
in between.
What is the Time Domain Reflectometry Test?
TDR (Time Domain Reflectometry) is used to verify
impedance continuity along a signal path. Many
interconnects, such as SMA, if not launched correctly onto
the PCB will exhibit inductive like resonance with an abrupt
capacitive discontinuity. This discontinuity will subtract signal
from the inputs and outputs and effectively close the resulting
data eye.
What Should I Use to Generate REFCLK in my
SY89534/5/6L Design?
This depends on data rate, jitter budget, and cost.
However, REFCLK input jitter will affect the overall jitter
performance of the system. A fundamental series tone
crystal-based oscillator is ideal. Measure the jitter of the
oscillator with a Wavecrest DTS2077 or a CSA803. A
measurement above the 3ps noise floor of the instrument
is too high. Remember that the REFCLK input is multiplied
by the M-Divider selected value, so the resulting jitter
increases by 20log (M-Divider). If you use a clock derived
from an ASIC, verify the single cycle and accumulated cycle
jitter.
Crystal based oscillators typically have poor AC power
supply rejection ratio, and if you are providing board power
via 400kHz switching supplies you may have to provide
some level of filtering, not just bypassing, for the supplies.
Should I Adjust the Loop Filter?
The values found in the data sheets are the result of
extensive modeling as well as lab testing. Therefore, we
recommend starting with those values.
8
Micrel
SY89531/2/3/4/5/6L Evaluation Board
DESCRIPTION OF CONNECTORS
SY89531L
Connector
S9
S11
S13
S15
S20
S24
S25
S29
Name
A0p
C0p
A0n
C0n
B3p
B3n
B4p
B4n
Type
LVPECL
LVPECL
LVPECL
LVPECL
HSTL
HSTL
HSTL
HSTL
Connects to
Pin 54
Pin 20
Pin 53
Pin 19
Pin 43
Pin 42
Pin 41
Pin 40
Description
AC-Coupled Output–Bank A
AC-Coupled Output–Bank C
AC-Coupled Output–Bank C
AC-Coupled Output–Bank A
DC-Coupled Output–Bank C
DC-Coupled Output–Bank B
DC-Coupled Output–Bank B
DC-Coupled Output–Bank B
Connector
S9
Name
A0p
Type
LVPECL
Connects to
Pin 54
Description
AC-Coupled Output–Bank A
S11
S13
S15
S20
S24
S25
S29
C0p
A0n
C0n
B3p
B3n
B4p
B4n
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
Pin 20
Pin 53
Pin 19
Pin 43
Pin 42
Pin 41
Pin 40
AC-Coupled Output–Bank C
AC-Coupled Output–Bank C
AC-Coupled Output–Bank A
AC-Coupled Output–Bank C
AC-Coupled Output–Bank B
AC-Coupled Output–Bank B
AC-Coupled Output–Bank B
Name
A0p
C0p
A0n
C0n
B3p
B3n
B4p
B4n
Type
LVPECL
LVPECL
LVPECL
LVPECL
LVDS
LVDS
LVDS
LVDS
Connects to
Pin 54
Pin 20
Pin 53
Pin 19
Pin 43
Pin 42
Pin 41
Pin 40
Description
AC-Coupled Output–Bank A
AC-Coupled Output–Bank C
AC-Coupled Output–Bank C
AC-Coupled Output–Bank A
AC-Coupled Output–Bank B
AC-Coupled Output–Bank B
AC-Coupled Output–Bank B
AC-Coupled Output–Bank B
Name
X2
X1
A0p
C0p
A0n
C0n
B3p
B3n
B4p
B4n
Type
TTL/LVPECL
TTL/LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
Connects to
Pin 10
Pin 11
Pin 54
Pin 20
Pin 53
Pin 19
Pin 43
Pin 42
Pin 41
Pin 40
Description
TTL or LVPECL Frequency Input
TTL or LVPECL Frequency Input
AC-Coupled Output–Bank A
AC-Coupled Output–Bank C
AC-Coupled Output–Bank C
AC-Coupled Output–Bank A
AC-Coupled Output–Bank C
AC-Coupled Output–Bank B
AC-Coupled Output–Bank B
AC-Coupled Output–Bank B
SY89532L
SY89533L
Connector
S9
S11
S13
S15
S20
S24
S25
S29
SY89534L
Connector
S5
S7
S9
S11
S13
S15
S20
S24
S25
S29
9
SY89531/2/3/4/5/6L Evaluation Board
Micrel
DESCRIPTION OF CONNECTORS
SY89535L
Connector
S5
S7
S11
S13
S15
S20
S24
S25
S29
Name
X2
X1
C0p
A0n
C0n
B3p
B3n
B4p
B4n
Type
TTL/LVPECL
TTL/LVPECL
LVPECL
LVPECL
LVPECL
LVDS
LVDS
LVDS
LVDS
Connects to
Pin 10
Pin 11
Pin 20
Pin 53
Pin 19
Pin 43
Pin 42
Pin 41
Pin 40
Description
TTL or LVPECL Frequency Input
TTL or LVPECL Frequency Input
AC-Coupled Output–Bank C
AC-Coupled Output–Bank C
AC-Coupled Output–Bank A
AC-Coupled Output–Bank B
AC-Coupled Output–Bank B
AC-Coupled Output–Bank B
AC-Coupled Output–Bank B
Name
X2
X1
C0p
A0n
C0n
B3p
B3n
B4p
B4n
Type
TTL/LVPECL
TTL/LVPECL
LVPECL
LVPECL
LVPECL
HSTL
HSTL
HSTL
HSTL
Connects to
Pin 10
Pin 11
Pin 20
Pin 53
Pin 19
Pin 43
Pin 42
Pin 41
Pin 40
Description
TTL or LVPECL Frequency Input
TTL or LVPECL Frequency Input
AC-Coupled Output–Bank C
AC-Coupled Output–Bank C
AC-Coupled Output–Bank A
DC-Coupled Output–Bank B
DC-Coupled Output–Bank B
DC-Coupled Output–Bank B
DC-Coupled Output–Bank B
SY89536L
Connector
S5
S7
S11
S13
S15
S20
S24
S25
S29
10
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SY89531/2/3/4/5/6L Evaluation Board
EVALUATION BOARD SCHEMATICS
VLOGIC
C36
0.01µF
C37
0.1µF
J5
J12
1
1
C38 VLOGIC
22µF
S9
SMA
VCCA
S13
SMA
J4
1
GND
C5
0.01µF
C9
0.01µF
R4
VEE 120Ω
R8
120Ω VEE
VEE
OUT_SYNC
SMA
J6
FSEL_A0
1
C41
22µF VCC_A
FSEL_A2
VLOGIC
J8
C35
22µF
C54
0.01µF
C42
0.01µF
C43
0.1µF
VCCA
C1
0.2µF
8
9
10
VEE
VEE
Y1
16MHz
11
12
M3
M2
M1
14
15
16
17
M0
13
49
50
51
52
53
54
55
56
58
59
60
61
62
63
U1 SY89531L
VCC_C
VEE
VCC_B1
FSEL_C2
FSEL_C1
FSEL_B2
B_LOGIC
FSEL_C0
FSEL_B0
VEE
R10
120Ω
R6
120Ω
C56
0.01µF
C7
0.01µF
S15
SMA
Chip Analog Ground
B0
/B1
B1
/B2
B2
/B3
B3
/B4
B4
/B5
B5
/B6
B6
/B7
B7
/B8
48
47
46
S20
SMA
45
44
43
42
S24
SMA
41
40
39
38
S25
SMA
37
36
35
S29
SMA
34
33
32
7
31
1
C53 VCC_C
22µF
30
C52
0.1µF
6
XVCO
29
C51
0.01µF
5
XVCOB
28
C2
R3 47pF
330Ω
J11
27
VCC_C
26
4
23
3
VEE
TESTC
TESTB
TESTA
VCO_SEL
XVCCB
XVCO
LFLT
/LFLT
GND1
XTAL2
XTAL1
VBB_REF
M3
M2
M1
M0
22
2
21
1
20
1
C48
22µF VCC_B
19
C47
0.1µF
J7
1
C44 V
EE_GND
22µF
VEE
C1
C1
C0
C0
VCCO_C
FSEL_C2
FSEL_C1
FSEL_C0
GND2
FSEL_B2
FSEL_B1
FSEL_B0
B_LOGIC
VCCO_B1
VCCO_B2
B8
C46
0.01µF
VEE
VCC_B2
VCCA
TESTQ
GND3
VCCA
VCC_L2
VCC_L1
OUT_SYNC
FSEL_A0
FSEL_A1
FSEL_A2
VCC_A
/A0
A0
/A1
A1
VCCO_B3
/B0
VEE
VCC_B1
18
VEE
64
VCCA
57
FSEL_A1
25
C40
0.1µF
24
C39
0.01µF
C45
0.01µF
C34
0.1µF
VEE
VCC_A
VCC_B2
C33
0.01µF
Notes:
1. Banks A to C configured as LVPECL
2. Set B_LOGIC = 0
3. Set XVCO = 0
4. Set XVCOB = 1
5. VCCA, VCC_A, VCC_B, VCC_C, VLOGIC = 3.3V
6. VEE_GND, GND = 0V
FSEL_B1
VEE
VLOGIC
S11
SMA
R34
10k
Layer Definitions:
Layer 1: Single Zo = 50Ω
Layer 2: Impedance GND
Layer 3: VCCA/VLOGIC
Layer 4: VCC_A/VCC_B/VCC_C
Layer 5: VEE
Layer 6: Single Zo = 50Ω/GND
R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R46 R43
10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k
SW3
FSEL_A2
FSEL_A1
FSEL_A0
XVCO
XVCOB
SW DIP-8
SW2
FSEL_C2
FSEL_C1
FSEL_C0
FSEL_B2
FSEL_B1
FSEL_B0
B_LOGIC
SW DIP-8
SW2
SW DIP-8
Figure 9. SY89531L Schematic
11
M3
M2
M1
M0
SY89531/2/3/4/5/6L Evaluation Board
Micrel
VLOGIC
C36
0.01µF
C37
0.1µF
J5
J12
1
1
C38 VLOGIC
22µF
S9
SMA
VCCA
S13
SMA
J4
1
C33
0.01µF
GND
C5
0.01µF
C9
0.01µF
R4
VEE 120Ω
R8
120Ω VEE
VEE
OUT_SYNC
SMA
J6
VCCA
FSEL_A2
VLOGIC
16
VCC_C
VEE
VCC_B1
FSEL_C2
FSEL_C1
FSEL_B2
B_LOGIC
FSEL_C0
FSEL_B0
R10
120Ω
VEE
C56
0.01µF
S15
SMA
R6
120Ω
C7
0.01µF
1
C44 V
EE_GND
22µF
Chip Analog Ground
R15
120Ω
45
C16
0.01µF
VEE
42
41
R19
120Ω
C20
0.01µF
R20
120Ω
C21
0.01µF
S20
SMA
S24
SMA
VEE
40
39
38
S25
SMA
37
VEE
36
35
R24
120Ω
34
33
C25
0.01µF
S29
SMA
VEE
32
15
31
14
17
M0
13
30
12
29
11
U1 SY89532L
28
9
M3
M2
M1
50
43
8
Y1
16MHz
51
44
/B3
B3
/B4
B4
/B5
B5
/B6
B6
/B7
B7
/B8
27
VEE
52
B2
XVCO
LFLT
/LFLT
GND1
XTAL2
XTAL1
VBB_REF
M3
M2
M1
M0
10
VEE
53
XVCCB
6
7
C1
0.2µF
54
5
26
C53 VCC_C
22µF
55
46
23
C52
0.1µF
56
B1
/B2
22
C51
0.01µF
XVCO
58
TESTA
VCO_SEL
21
1
XVCOB
59
47
3
20
C2
47pF
R3
330Ω
J11
60
48
/B1
4
VCC_C
61
B0
TESTB
19
VEE
63
64
TESTC
2
TESTQ
GND3
VCCA
VCC_L2
VCC_L1
OUT_SYNC
FSEL_A0
FSEL_A1
FSEL_A2
VCC_A
/A0
A0
/A1
A1
VCCO_B3
/B0
1
C48
22µF VCC_B
VCC_B2
C1
C1
C0
C0
VCCO_C
FSEL_C2
FSEL_C1
FSEL_C0
GND2
FSEL_B2
FSEL_B1
FSEL_B0
B_LOGIC
VCCO_B1
VCCO_B2
B8
C47
0.1µF
VCCA
C43
0.1µF
VEE
1
J8
C46
0.01µF
VEE
VEE
18
VCC_B1
62
VCCA
VEE
57
FSEL_A1
C42
0.01µF
49
C41
22µF VCC_A
25
C40
0.1µF
24
C39
0.01µF
J7
C54
0.01µF
FSEL_A0
1
C45
0.01µF
C35
22µF
VEE
VCC_A
VCC_B2
C34
0.1µF
Notes:
1. Banks A to C configured as LVPECL
2. Set B_LOGIC = 0
3. Set XVCO = 0
4. Set XVCOB = 1
5. VCCA, VCC_A, VCC_B, VCC_C, VLOGIC = 3.3V
6. VEE_GND, GND = 0V
FSEL_B1
VEE
VLOGIC
S11
SMA
R34
10k
Layer Definitions:
Layer 1: Single Zo = 50Ω
Layer 2: Impedance GND
Layer 3: VCCA/VLOGIC
Layer 4: VCC_A/VCC_B/VCC_C
Layer 5: VEE
Layer 6: Single Zo = 50Ω/GND
R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R46 R43
10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k
SW3
FSEL_A2
FSEL_A1
FSEL_A0
XVCO
XVCOB
SW DIP-8
SW2
FSEL_C2
FSEL_C1
FSEL_C0
FSEL_B2
FSEL_B1
FSEL_B0
B_LOGIC
SW DIP-8
SW2
SW DIP-8
Figure 10. SY89532L Schematic
12
M3
M2
M1
M0
Micrel
SY89531/2/3/4/5/6L Evaluation Board
VLOGIC
J5
1
C38 VLOGIC
22µF
1
J6
C41 V
22µF CC_A
1
C42
0.01µF
C43
0.1µF
1
C44
22µF VEE_GND
Chip Analog Ground
Y1
16MHz
11
12
M3
M2
M1
14
15
16
17
M0
13
49
50
51
52
53
54
55
56
58
59
60
61
63
VCC_C
VEE
VCC_B1
FSEL_C2
FSEL_C1
FSEL_B2
FSEL_C0
R10
120Ω
B_LOGIC
FSEL_B0
R6
120Ω
32
VEE
31
10
VEE
U1 SY89533L
30
9
43
29
8
/B3
B3
/B4
B4
/B5
B5
/B6
B6
/B7
B7
/B8
28
C1
0.2µF
XVCO
LFLT
/LFLT
GND1
XTAL2
XTAL1
VBB_REF
M3
M2
M1
M0
27
C53 VCC_C
22µF
7
46
24
1
6
XVCO
B1
/B2
B2
23
R15
330Ω
5
XVCOB
R57
100Ω
TESTA
VCO_SEL
XVCCB
22
C2
47pF
J11
VEE
VCC_B2
48
21
4
VCC_C
VCCA
B0
/B1
20
3
VEE
C52
0.1µF
VCCA
J7
C54
0.01µF
TESTC
TESTB
19
2
57
FSEL_A1
C1
/C1
C0
/C0
VCCO_C
FSEL_C2
FSEL_C1
FSEL_C0
GND2
FSEL_B2
FSEL_B1
FSEL_B0
B_LOGIC
VCCO_B1
VCCO_B2
B8
1
18
C48 V
22µF CC_B
62
64
J8
C51
0.01µF
R8
120Ω VEE
TESTQ
GND3
VCCA
VCC_L2
VCC_L1
OUT_SYNC
FSEL_A0
FSEL_A1
FSEL_A2
VCC_A
/A0
A0
/A1
A1
VCCO_B3
/B0
VEE
VCC_B1
C47
0.1µF
R4
VEE 120Ω
C35
22µF
VLOGIC
VCCA
C46
0.01µF
C9
0.01µF
FSEL_A2
VEE
C45
0.01µF
C5
0.01µF
FSEL_A0
1
VCC_B2
1
C34
0.1µF
VEE
OUT_SYNC
SMA
VCC_A
C40
0.1µF
J4
GND
VEE
C39
0.01µF
VCCA
S13
SMA
C33
0.01µF
26
C37
0.1µF
25
C36
0.01µF
S9
SMA
J12
47
45
44
R56
100Ω
C16
0.01µF
R55
100Ω
C20
0.01µF
42
S20
SMA
S24
SMA
41
40
39
38
37
36
35
34
R54
100Ω
C21
0.01µF
R53
100Ω
R52
100Ω
C25
0.01µF
S25
SMA
S29
SMA
33
R51
100Ω
Notes:
1. Banks A and C are LVPECL, Bank B is LVDS
2. Set B_LOGIC = 0
3. Set XVCO = 0
4. Set XVCOB = 1
5. VCCA, VCC_A, VCC_B, VCC_C, VLOGIC = 3.3V
6. VEE_GND, GND = 0V
FSEL_B1
VEE
C56
0.01µF
S15
SMA
C7
VEE
0.01µF
VLOGIC
S11
SMA
R34
10k
Layer Definitions:
Layer 1: Single Zo = 50Ω
Layer 2: Impedance GND
Layer 3: VCCA/VLOGIC
Layer 4: VCC_A/VCC_B/VCC_C
Layer 5: VEE
Layer 6: Single Zo = 50Ω/GND
R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R46 R43
10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k
SW3
FSEL_A2
FSEL_A1
FSEL_A0
XVCO
XVCOB
SW DIP-8
SW2
FSEL_C2
FSEL_C1
FSEL_C0
FSEL_B2
FSEL_B1
FSEL_B0
B_LOGIC
SW DIP-8
SW2
SW DIP-8
Figure 11. SY89533L Schematic
13
M3
M2
M1
M0
SY89531/2/3/4/5/6L Evaluation Board
Micrel
VLOGIC
J5
1
C38 VLOGIC
22µF
1
VEE
J6
C41 V
22µF CC_A
C53
22µF VCC_C
17
C52
0.1µF
C42
0.01µF
C43
0.1µF
1
C44 V
EE_GND
22µF
Chip Analog Ground
49
50
51
52
53
54
55
VCC_C
VEE
VEE
VCC_B1
FSEL_C2
FSEL_C1
FSEL_B2
B_LOGIC
FSEL_C0
R10
120Ω
FSEL_B0
R6
120Ω
R15
120Ω
45
44
C16
0.01µF
S20
SMA
VEE
43
42
41
R19
120Ω
C20
0.01µF
R20
120Ω
C21
0.01µF
S24
SMA
VEE
40
39
38
S25
SMA
37
VEE
36
35
R24
120Ω
34
33
C25
0.01µF
S29
SMA
VEE
32
1
31
16
30
15
29
14
28
M0
13
27
12
U1 SY89534L
24
9
23
6
22
J11
56
46
21
VCC_C
58
B1
/B2
B2
/B3
B3
/B4
B4
/B5
B5
/B6
B6
/B7
B7
/B8
7
M3
M2
M1
59
TESTA
VCO_SEL
XVCCB
XVCO
LFLT
/LFLT
GND1
XTAL2
XTAL1
VBB_REF
M3
M2
M1
M0
8
VEE
60
47
3
11
R24
50Ω
61
48
/B1
10
R15
50Ω
62
B0
TESTB
5
63
TESTC
20
XVCO
C1
0.2µF
C51
0.01µF
VCCA
VEE
VCC_B2
2
19
XVCOB
VCCA
1
4
C2
R19 47pF
330Ω
S7
SMA
C35
22µF
J7
C54
0.01µF
64
VEE
57
FSEL_A1
TESTQ
GND3
VCCA
VCC_L2
VCC_L1
OUT_SYNC
FSEL_A0
FSEL_A1
FSEL_A2
VCC_A
/A0
A0
/A1
A1
VCCO_B3
/B0
1
C48 V
22µF CC_B
S5
SMA
R8
120Ω VEE
C1
/C1
C0
/C0
VCCO_C
FSEL_C2
FSEL_C1
FSEL_C0
GND2
FSEL_B2
FSEL_B1
FSEL_B0
B_LOGIC
VCCO_B1
VCCO_B2
B8
C47
0.1µF
R4
VEE 120Ω
VEE
J8
18
VEE
C46
0.01µF
C9
0.01µF
C34
0.1µF
VLOGIC
VCC_B1
C45
0.01µF
C5
0.01µF
FSEL_A2
VCCA
VCC_B2
1
FSEL_A0
1
C40
0.1µF
J4
C33
0.01µF
VEE
OUT_SYNC
SMA
VCC_A
C39
0.01µF
VCCA
S13
SMA
GND
26
C37
0.1µF
25
C36
0.01µF
S9
SMA
J12
Notes:
1. Banks A and C are LVPECL, Bank B is LVDS
2. Set B_LOGIC = 0
3. Set XVCO = 0
4. Set XVCOB = 1
5. VCCA, VCC_A, VCC_B, VCC_C, VLOGIC = 3.3V
6. VEE_GND, GND = 0V
FSEL_B1
VEE
C56
0.01µF
S15
SMA
C7
VEE
0.01µF
VLOGIC
S11
SMA
R34
10k
Layer Definitions:
Layer 1: Single Zo = 50Ω
Layer 2: Impedance GND
Layer 3: VCCA/VLOGIC
Layer 4: VCC_A/VCC_B/VCC_C
Layer 5: VEE
Layer 6: Single Zo = 50Ω/GND
R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R46 R43
10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k
SW3
FSEL_A2
FSEL_A1
FSEL_A0
XVCO
XVCOB
SW DIP-8
SW2
FSEL_C2
FSEL_C1
FSEL_C0
FSEL_B2
FSEL_B1
FSEL_B0
B_LOGIC
SW DIP-8
SW2
SW DIP-8
Figure 12. SY89534L Schematic
14
M3
M2
M1
M0
Micrel
SY89531/2/3/4/5/6L Evaluation Board
VLOGIC
J5
C36
0.01µF
1
C38 VLOGIC
22µF
C37
0.1µF
S9
SMA
J12
1
VEE
VCCA
S13
SMA
J4
1
GND
C5
0.01µF
C9
0.01µF
R4
VEE 120Ω
R8
120Ω VEE
VCC_A
J6
C39
0.01µF
FSEL_A0
FSEL_A2
VEE
C54
0.01µF
C42
0.01µF
C43
0.1µF
VCCA
J7
1
C44
22µF VEE_GND
Chip Analog Ground
VEE
49
50
51
52
53
VCC_B2
54
55
56
58
59
60
61
VCCA
TESTQ
GND3
VCCA
VCC_L2
VCC_L1
OUT_SYNC
FSEL_A0
FSEL_A1
FSEL_A2
VCC_A
/A0
A0
/A1
A1
VCCO_B3
/B0
VEE
63
64
1
C48
22µF VCC_B
C47
0.1µF
62
VCCA
J8
C46
0.01µF
FSEL_A1
57
VCC_B1
C45
0.01µF
C35
22µF
VLOGIC
R57
100Ω
VEE
1
TESTC
B0
48
VCC_C
2
TESTB
TESTA
/B1
B1
47
4
VCO_SEL
/B2
45
5
XVCCB
XVCO
B2
/B3
44
B3
42
/B4
B4
/B5
41
B5
/B6
B6
38
/B7
B7
35
/B8
33
/LFLT
GND1
XTAL2
13
M1
15
16
M2
M1
M0
17
M0
14
VCC_C
VEE
VCC_B1
FSEL_C2
FSEL_C1
FSEL_B2
FSEL_C0
R10
120Ω
VEE
C56
0.01µF
S15
SMA
R6
120Ω
B_LOGIC
FSEL_B0
32
R15
50Ω
12
M3
M2
31
R24
50Ω VEE
XTAL1
VBB_REF
M3
30
11
29
S7
SMA
28
10
U1 SY89535L
27
9
26
S5
SMA
LFLT
8
25
C1
0.2µF
7
24
XVCO
23
VEE
6
22
R15
330Ω
XVCOB
21
C2
47pF
20
1
C53 VCC_C
22µF
C52
0.1µF
C1
/C1
C0
/C0
VCCO_C
FSEL_C2
FSEL_C1
FSEL_C0
GND2
FSEL_B2
FSEL_B1
FSEL_B0
B_LOGIC
VCCO_B1
VCCO_B2
B8
C51
0.01µF
3
18
J11
19
VCC_B2
C34
0.1µF
VEE
OUT_SYNC
SMA
1
C41 V
22µF CC_A
C40
0.1µF
C33
0.01µF
46
R56
100Ω
C16
0.01µF
R55
100Ω
43
C20
0.01µF
S20
SMA
S24
SMA
40
39
37
36
34
R54
100Ω
C21
0.01µF
R53
100Ω
R52
100Ω
C25
0.01µF
S25
SMA
S29
SMA
R51
100Ω
Notes:
1. Banks A and C are LVPECL, Bank B is LVDS
2. Set B_LOGIC = 0
3. Set XVCO = 0
4. Set XVCOB = 1
5. VCCA, VCC_A, VCC_B, VCC_C, VLOGIC = 3.3V
6. VEE_GND, GND = 0V
FSEL_B1
VEE
C7
0.01µF
VLOGIC
S11
SMA
R34
10k
Layer Definitions:
Layer 1: Single Zo = 50Ω
Layer 2: Impedance GND
Layer 3: VCCA/VLOGIC
Layer 4: VCC_A/VCC_B/VCC_C
Layer 5: VEE
Layer 6: Single Zo = 50Ω/GND
R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R46 R43
10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k
SW3
FSEL_A2
FSEL_A1
FSEL_A0
XVCO
XVCOB
SW DIP-8
SW2
FSEL_C2
FSEL_C1
FSEL_C0
FSEL_B2
FSEL_B1
FSEL_B0
B_LOGIC
SW DIP-8
SW2
SW DIP-8
Figure 13. SY89535L Schematic
15
M3
M2
M1
M0
SY89531/2/3/4/5/6L Evaluation Board
Micrel
VLOGIC
J5
1
C38 VLOGIC
22µF
1
VEE
J6
C41
22µF VCC_A
C42
0.01µF
C43
0.1µF
1
C44
22µF VEE_GND
Chip Analog Ground
49
50
51
52
VCC_C
VEE
VEE
VCC_B1
FSEL_C2
FSEL_C1
FSEL_B2
B_LOGIC
FSEL_C0
R10
120Ω
FSEL_B0
R6
120Ω
48
S20
SMA
45
43
42
S24
SMA
41
40
39
38
S25
SMA
37
36
35
S29
SMA
34
33
32
31
30
1
C53 V
22µF CC_C
29
16
28
15
27
14
24
13
U1 SY89536L
23
C52
0.1µF
12
17
C51
0.01µF
53
44
6
9
M0
54
B2
/B3
B3
/B4
B4
/B5
B5
/B6
B6
/B7
B7
/B8
22
J11
55
XVCCB
XVCO
LFLT
/LFLT
GND1
XTAL2
XTAL1
VBB_REF
M3
M2
M1
M0
21
VCC_C
56
46
7
M3
M2
M1
58
B1
/B2
8
VEE
59
TESTA
VCO_SEL
11
R24
50Ω
60
47
3
10
R15
50Ω
61
/B1
20
XVCO
62
B0
TESTB
5
63
TESTC
2
19
XVCOB
C1
0.2µF
S7
SMA
VCCA
VEE
VCC_B2
1
4
C2
R19 47pF
330Ω
S5
SMA
C35
22µF
J7
C54
0.01µF
64
VEE
VCCA
TESTQ
GND3
VCCA
VCC_L2
VCC_L1
OUT_SYNC
FSEL_A0
FSEL_A1
FSEL_A2
VCC_A
/A0
A0
/A1
A1
VCCO_B3
/B0
1
C48
22µF VCC_B
57
FSEL_A1
C1
/C1
C0
/C0
VCCO_C
FSEL_C2
FSEL_C1
FSEL_C0
GND2
FSEL_B2
FSEL_B1
FSEL_B0
B_LOGIC
VCCO_B1
VCCO_B2
B8
C47
0.1µF
R8
120Ω VEE
VEE
J8
18
VCC_B1
C46
0.01µF
R4
VEE 120Ω
C34
0.1µF
VLOGIC
VCCA
C45
0.01µF
C9
0.01µF
FSEL_A2
VEE
VCC_B2
1
C5
0.01µF
FSEL_A0
1
C40
0.1µF
J4
C33
0.01µF
VEE
OUT_SYNC
SMA
VCC_A
C39
0.01µF
VCCA
S13
SMA
GND
26
C37
0.1µF
25
C36
0.01µF
S9
SMA
J12
Notes:
1. Banks A and C are LVPECL, Bank B is LVDS
2. Set B_LOGIC = 0
3. Set XVCO = 0
4. Set XVCOB = 1
5. VCCA, VCC_A, VCC_B, VCC_C, VLOGIC = 3.3V
6. VEE_GND, GND = 0V
FSEL_B1
VEE
C56
0.01µF
S15
SMA
C7
VEE
0.01µF
VLOGIC
S11
SMA
R34
10k
Layer Definitions:
Layer 1: Single Zo = 50Ω
Layer 2: Impedance GND
Layer 3: VCCA/VLOGIC
Layer 4: VCC_A/VCC_B/VCC_C
Layer 5: VEE
Layer 6: Single Zo = 50Ω/GND
R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R46 R43
10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k
SW3
FSEL_A2
FSEL_A1
FSEL_A0
XVCO
XVCOB
SW DIP-8
SW2
FSEL_C2
FSEL_C1
FSEL_C0
FSEL_B2
FSEL_B1
FSEL_B0
B_LOGIC
SW DIP-8
SW2
SW DIP-8
Figure 14. SY89536L Schematic
16
M3
M2
M1
M0
Micrel
SY89531/2/3/4/5/6L Evaluation Board
BILL OF MATERIALS
SY89531L
Item
Part Number
Manufacturer
Description
C1
PCC1749CT-ND
Panasonic/Digi-Key(1)
0.2µF, 50V, Capacitor, Size 0603
1
C2
PCC470ACVCT-ND
Panasonic/Digi-Key(1)
47pF, 50V, Capacitor, Size 0603
1
C5, C7, C9, C33,
C36, C39, C42, C45,
C46, C51, C54, C56
PCCIC3CQCT-ND
Panasonic/Digi-Key(1)
0.01µF, 50V Capacitor, Size 0402
12
C34, C37, C40,
C43, C47, C52
PCC104BCT-ND
Panasonic/Digi-Key(1)
0.1µF, 50V Capacitor, Size 1206
6
C35, C38, C41,
C44, C48, C53
PCT3226CT-ND
Panasonic/Digi-Key(1)
22µF, 35V, Tantalum, D-Size
6
J4, J5, J6, J7
J8, J11, J12
111-0703-001-ND
Johnson/Digi-Key(2)
Banana Jack
7
R3
P332HCT-ND
Panasonic/Digi-Key(1)
330Ω Resistor, Size 0603
1
R4, R6, R8, R10
P121HCT-ND
Panasonic/Digi-Key(1)
120Ω Resistor, Size 0402
4
R33, R34, R35, R36
R37, R38, R39, R40,
R41, R42, R43, R44,
R45, R46
P100KHCT-ND
Panasonic/Digi-Key(1)
10k Resistor, Size 0602
14
S9, S11, S13, S15,
S20, S24, S25, S29,
OUT_SYNC
142-0701-851-ND
Johnson/Digi-Key(2)
SMA
9
SW2, SW3, SW4
CT2188LPST-ND
CTS/Digi-Key(3)
DIP-8
3
U1
SY89531L
Micrel Semiconductor(4)
3.3V Programmable LVPECL and HSTL
Bus Clock Synthesizer
1
Y1
16.6 AS-SMD
Raltron(5)
16MHz
1
Note 1.
Panasonic tel: 847-468-5624
Note 2.
Johnson Components tel: 800-247-8256
Note 3.
CTS tel: 574-293-7511
Note 4.
Micrel Semiconductor tel: 408-944-0800
Note 5.
Raltron tel: 305-593-6033
17
Qty.
SY89531/2/3/4/5/6L Evaluation Board
Micrel
SY89532L
Item
Part Number
Manufacturer
Description
C1
PCC1749CT-ND
Panasonic/Digi-Key(1)
0.2µF, 50V, Capacitor, Size 0603
C2
PCC470ACVCT-ND
Panasonic/Digi-Key(1)
47pF, 50V, Capacitor, Size 0603
1
C5, C7, C9, C16,
C20, C21, C25, C33
C36, C39, C42, C45,
C46, C51, C54, C56
PCCIC3CQCT-ND
Panasonic/Digi-Key(1)
0.01µF, 50V Capacitor, Size 0402
16
C34, C37, C40,
C43, C47, C52
PCC104BCT-ND
Panasonic/Digi-Key(1)
0.1µF, 50V Capacitor, Size 1206
6
C35, C38, C41,
C44, C48, C53
PCT3226CT-ND
Panasonic/Digi-Key(1)
22µF, 35V, Tantalum, D-Size
6
J4, J5, J6, J7
J8, J11, J12
111-0703-001-ND
Johnson/Digi-Key(2)
Banana Jack
7
R3
P332HCT-ND
Panasonic/Digi-Key(1)
330Ω Resistor, Size 0603
1
R4, R6, R8, R10
R15, R19, R20, R24
P121HCT-ND
Panasonic/Digi-Key(1)
120Ω Resistor, Size 0402
8
R33, R34, R35, R36
R37, R38, R39, R40,
R41, R42, R43, R44,
R45, R46
P100KHCT-ND
Panasonic/Digi-Key(1)
10k Resistor, Size 0602
14
S9, S11, S13, S15,
S20, S24, S25, S29,
OUT_SYNC
142-0701-851-ND
Johnson/Digi-Key(2)
SMA
9
SW2, SW3, SW4
CT2188LPST-ND
CTS/Digi-Key(3)
DIP-8
3
U1
SY89532L
Micrel Semiconductor(4)
3.3V Programmable LVPECL and LVDS
Bus Clock Synthesizer
1
Y1
16.6 AS-SMD
Raltron(5)
16MHz
1
Note 1.
Panasonic tel: 847-468-5624
Note 2.
Johnson Components tel: 800-247-8256
Note 3.
CTS tel: 574-293-7511
Note 4.
Micrel Semiconductor tel: 408-944-0800
Note 5.
Raltron tel: 305-593-6033
18
Qty.
1
Micrel
SY89531/2/3/4/5/6L Evaluation Board
SY89533L
Item
Part Number
Manufacturer
Description
C1
PCC1749CT-ND
Panasonic/Digi-Key(1)
0.2µF, 50V, Capacitor, Size 0603
C2
PCC470ACVCT-ND
Panasonic/Digi-Key(1)
47pF, 50V, Capacitor, Size 0603
1
C5, C7, C9, C16,
C20, C21, C25, C33
C36, C39, C42, C45,
C46, C51, C54, C56
PCCIC3CQCT-ND
Panasonic/Digi-Key(1)
0.01µF, 50V Capacitor, Size 0402
16
C34, C37, C40,
C43, C47, C52
PCC104BCT-ND
Panasonic/Digi-Key(1)
0.1µF, 50V Capacitor, Size 1206
6
C35, C38, C41,
C44, C48, C53
PCT3226CT-ND
Panasonic/Digi-Key(1)
22µF, 35V, Tantalum, D-Size
6
J4, J5, J6, J7
J8, J11, J12
111-0703-001-ND
Johnson/Digi-Key(2)
Banana Jack
7
R3
P332HCT-ND
Panasonic/Digi-Key(1)
330Ω Resistor, Size 0603
1
R4, R6, R8, R10,
R15, R19, R20, R24
P121HCT-ND
Panasonic/Digi-Key(1)
120Ω Resistor, Size 0402
8
R33, R34, R35, R36
R37, R38, R39, R40,
R41, R42, R43, R44,
R45, R46
P10.0KHCT-ND
Panasonic/Digi-Key(1)
10k Resistor, Size 0602
14
R51, R52, R53, R54
R55, R56, R57
P100HCT-ND
Panasonic/Digi-Key(1)
100Ω Resistor, Size 0402
S9, S11, S13, S15,
S20, S24, S25, S29,
OUT_SYNC
142-0701-851-ND
Johnson/Digi-Key(2)
SMA
9
SW2, SW3, SW4
CT2188LPST-ND
CTS/Digi-Key(3)
DIP-8
3
3.3V Programmable LVPECL and LVDS
Bus Clock Synthesizer
1
16MHz
1
Semiconductor(4)
U1
SY89533L
Micrel
Y1
16.6 AS-SMD
Raltron(5)
Note 1.
Panasonic tel: 847-468-5624
Note 2.
Johnson Components tel: 800-247-8256
Note 3.
CTS tel: 574-293-7511
Note 4.
Micrel Semiconductor tel: 408-944-0800
Note 5.
Raltron tel: 305-593-6033
19
Qty.
1
SY89531/2/3/4/5/6L Evaluation Board
Micrel
SY89534L
Item
Part Number
Manufacturer
Description
C1
PCC1749CT-ND
Panasonic/Digi-Key(1)
0.2µF, 50V, Capacitor, Size 0603
C2
PCC470ACVCT-ND
Panasonic/Digi-Key(1)
47pF, 50V, Capacitor, Size 0603
1
C5, C7, C9, C16,
C20, C21, C25, C33
C36, C39, C42, C45,
C46, C51, C54, C56
PCCIC3CQCT-ND
Panasonic/Digi-Key(1)
0.01µF, 50V Capacitor, Size 0402
16
C34, C37, C40,
C43, C47, C52
PCC104BCT-ND
Panasonic/Digi-Key(1)
0.1µF, 50V Capacitor, Size 1206
6
C35, C38, C41,
C44, C48, C53
PCT3226CT-ND
Panasonic/Digi-Key(1)
22µF, 35V, Tantalum, D-Size
6
J4, J5, J6, J7
J8, J11, J12
111-0703-001-ND
Johnson/Digi-Key(2)
Banana Jack
7
R3
P332HCT-ND
Panasonic/Digi-Key(1)
330Ω Resistor, Size 0603
1
R4, R6, R8, R10,
R15, R19, R20, R24
P121HCT-ND
Panasonic/Digi-Key(1)
120Ω Resistor, Size 0402
8
R15, R24
P51.1LCT-ND
Panasonic/Digi-Key(1)
50Ω Resistor, Size 0402
2
R33, R34, R35, R36
R37, R38, R39, R40,
R41, R42, R43, R44,
R45, R46
P10.0KHCT-ND
Panasonic/Digi-Key(1)
10k Resistor, Size 0602
14
R51, R52, R53, R54
R55, R56, R57
P100HCT-ND
Panasonic/Digi-Key(1)
100Ω Resistor, Size 0402
S5, S9, S9, S11, S13,
S15, S20, S24, S25,
S29, OUT_SYNC
142-0701-851-ND
Johnson/Digi-Key(2)
SMA
11
SW2, SW3, SW4
CT2188LPST-ND
CTS/Digi-Key(3)
DIP-8
3
U1
SY89534L
Micrel Semiconductor(4)
3.3V Programmable LVPECL and LVDS
Bus Clock Synthesizer
1
Y1
16.6 AS-SMD
Raltron(5)
16MHz
1
Note 1.
Panasonic tel: 847-468-5624
Note 2.
Johnson Components tel: 800-247-8256
Note 3.
CTS tel: 574-293-7511
Note 4.
Micrel Semiconductor tel: 408-944-0800
Note 5.
Raltron tel: 305-593-6033
20
Qty.
1
Micrel
SY89531/2/3/4/5/6L Evaluation Board
SY89535L
Item
Part Number
Manufacturer
Description
C1
PCC1749CT-ND
Panasonic/Digi-Key(1)
0.2µF, 50V, Capacitor, Size 0603
C2
PCC470ACVCT-ND
Panasonic/Digi-Key(1)
47pF, 50V, Capacitor, Size 0603
1
C5, C7, C9, C16,
C20, C21, C25, C33
C36, C39, C42, C45,
C46, C51, C54, C56
PCCIC3CQCT-ND
Panasonic/Digi-Key(1)
0.01µF, 50V Capacitor, Size 0402
16
C34, C37, C40,
C43, C47, C52
PCC104BCT-ND
Panasonic/Digi-Key(1)
0.1µF, 50V Capacitor, Size 1206
6
C35, C38, C41,
C44, C48, C53
PCT3226CT-ND
Panasonic/Digi-Key(1)
22µF, 35V, Tantalum, D-Size
6
J4, J5, J6, J7
J8, J11, J12
111-0703-001-ND
Johnson/Digi-Key(2)
Banana Jack
7
R3
P332HCT-ND
Panasonic/Digi-Key(1)
330Ω Resistor, Size 0603
1
R4, R6, R8, R10,
P121HCT-ND
Panasonic/Digi-Key(1)
120Ω Resistor, Size 0402
4
R15, R24
P51.1LCT-ND
Panasonic/Digi-Key(1)
50Ω Resistor, Size 0402
2
R33, R34, R35, R36
R37, R38, R39, R40,
R41, R42, R43, R44,
R45, R46
P10.0HCT-ND
Panasonic/Digi-Key(1)
10k Resistor, Size 0602
14
R51, R52, R53, R54
R55, R56, R57
P100HCT-ND
Panasonic/Digi-Key(1)
100Ω Resistor, Size 0402
7
S5, S7, S9, S11, S13,
S15, S20, S24, S25,
S29, OUT_SYNC
142-0701-851-ND
Johnson/Digi-Key(2)
SMA
11
SW2, SW3, SW4
CT2188LPST-ND
CTS/Digi-Key(3)
DIP-8
3
3.3V Programmable LVPECL and LVDS
Bus Clock Synthesizer
1
16MHz
1
Semiconductor(4)
U1
SY89535L
Micrel
Y1
16.6 AS-SMD
Raltron(5)
Note 1.
Panasonic tel: 847-468-5624
Note 2.
Johnson Components tel: 800-247-8256
Note 3.
CTS tel: 574-293-7511
Note 4.
Micrel Semiconductor tel: 408-944-0800
Note 5.
Raltron tel: 305-593-6033
21
Qty.
1
SY89531/2/3/4/5/6L Evaluation Board
Micrel
SY89536L
Item
Part Number
Manufacturer
Description
C1
PCC1749CT-ND
Panasonic/Digi-Key(1)
0.2µF, 50V, Capacitor, Size 0603
1
C2
PCC470ACVCT-ND
Panasonic/Digi-Key(1)
47pF, 50V, Capacitor, Size 0603
1
C5, C7, C9, C33,
C36, C39, C42, C45,
C46, C51, C54, C56
PCCIC3CQCT-ND
Panasonic/Digi-Key(1)
0.01µF, 50V Capacitor, Size 0402
12
C34, C37, C40,
C43, C47, C52
PCC104BCT-ND
Panasonic/Digi-Key(1)
0.1µF, 50V Capacitor, Size 1206
6
C35, C38, C41,
C44, C48, C53
PCT3226CT-ND
Panasonic/Digi-Key(1)
22µF, 35V, Tantalum, D-Size
6
J4, J5, J6, J7
J8, J11, J12
111-0703-001-ND
Johnson/Digi-Key(2)
Banana Jack
7
R3
P332HCT-ND
Panasonic/Digi-Key(1)
330Ω Resistor, Size 0603
1
R4, R6, R8, R10,
P121HCT-ND
Panasonic/Digi-Key(1)
120Ω Resistor, Size 0402
4
R33, R34, R35, R36
R37, R38, R39, R40,
R41, R42, R43, R44,
R45, R46
P10.0KHCT-ND
Panasonic/Digi-Key(1)
10k Resistor, Size 0602
14
R51, R52, R53, R54
R55, R56, R57
P100HCT-ND
Panasonic/Digi-Key(1)
100Ω Resistor, Size 0402
S5, S9, S9, S11, S13,
S15, S20, S24, S25,
S29, OUT_SYNC
142-0701-851-ND
Johnson/Digi-Key(2)
SMA
11
SW2, SW3, SW4
CT2188LPST-ND
CTS/Digi-Key(3)
DIP-8
3
U1
SY89536L
Micrel Semiconductor(4)
3.3V Programmable LVPECL and HSTL
Bus Clock Synthesizer
1
Y1
16.6 AS-SMD
Raltron(5)
16MHz
1
Note 1.
Panasonic tel: 847-468-5624
Note 2.
Johnson Components tel: 800-247-8256
Note 3.
CTS tel: 574-293-7511
Note 4.
Micrel Semiconductor tel: 408-944-0800
Note 5.
Raltron tel: 305-593-6033
MICREL, INC.
TEL
1849 FORTUNE DRIVE SAN JOSE, CA 95131
+ 1 (408) 944-0800
FAX
+ 1 (408) 944-0970
WEB
Qty.
USA
http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use.
Micrel reserves the right to change circuitry and specifications at any time without notification to the customer.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can
reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into
the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s
use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser’s own risk and Purchaser agrees to fully indemnify
Micrel for any damages resulting from such use or sale.
© 2003 Micrel, Incorporated.
22