NC7SV57 / NC7SV58 TinyLogic® ULP-A Universal Configurable Two-Input Logic Gates Features Description 0.9V to 3.6V VCC Supply Operation Extremely High Speed tPD - 2.5ns: Typical for 2.7V to 3.6V VCC - 3.1ns: Typical for 2.3V to 2.7V VCC - 4.0ns: Typical for 1.65V to 1.95V VCC - 6.0ns: Typical for 1.4V to 1.6V VCC - 8.0ns: Typical for 1.1V to 1.3V VCC - 23.0ns: Typical for 0.9V VCC The NC7SV57 and NC7SV58 are universal configurable two-input logic gates from Fairchild’s Ultra-Low Power ® (ULP-A) series of TinyLogic . ULP-A is ideal for applications that require extreme high-speed, high drive, and low power. This product is designed for a wide low-voltage operating range (0.9V to 3.6V VCC) and applications that require more drive and speed than ® the TinyLogic ULP series, but still offer best-in-class, low-power operation. 3.6V Over-Voltage Tolerant I/Os at VCC from 0.9V to 3.6V Power-Off High-Impedance Inputs and Outputs High Static Drive (IOH/IOL) - ±24mA at 3.00V VCC - ±18mA at 2.30V VCC - ±6mA at 1.65V VCC - ±4mA at 1.4V VCC - ±2mA at 1.1V VCC - ±0.1mA at 0.9V VCC Proprietary Quiet Series™ Noise/EMI Reduction Each device is capable of being configured for 1 of 5 unique two-input logic functions. Any possible two-input combinatorial logic function can be implemented, as shown in the Function Selection Table. Device functionality is selected by how the device is wired at the board level. Figures 1 through 10 illustrate how to connect the NC7SV57 and NC7SV58, respectively, for the desired logic function. All inputs have been implemented with hysteresis. The NC7SV57 and NC7SV58 are uniquely designed for optimized power and speed and are fabricated with an advanced CMOS technology to achieve high-speed operation while maintaining low CMOS power dissipation. Ultra-Small MicroPak™ Package Ultra-Low Dynamic Power Ordering Information Part Number NC7SV57P6X Top Mark V57 Package 6-Lead SC70, EIAJ SC-88a, 1.25mm Wide NC7SV57L6X H3 6-Lead Micropak™, 1.0mm Wide NC7SV57FHX H3 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch NC7SV58P6X V58 6-Lead SC70, EIAJ SC-88a, 1.25mm Wide NC7SV58L6X H4 6-Lead Micropak™, 1.0mm Wide NC7SV58FHX H4 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 Packing Method 3000 Units on Tape & Reel 5000 Units on Tape & Reel 3000 Units on Tape & Reel 5000 Units on Tape & Reel www.fairchildsemi.com NC7SV57 / NC7SV58 — TinyLogic® ULP-A Universal Configuration Two-Input Logic Gates December 2010 Figure 1. Battery Life vs. VCC Supply Voltage Notes: ® 1. TinyLogic ULP and ULP-A with up to 50% less power consumption can extend your battery life significantly. Battery Life = (Vbattery•Ibattery•.9)/(Pdevice)/24hrs/day 2 where Pdevice = (ICC • VCC) + (CPD + CL) • VCC • f. 2. Assumes ideal 3.6V Lithium Ion battery with current rating of 900mAH and derated 90% and device frequency at 10MHz, with CL = 15pF load. © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 NC7SV57 / NC7V58 — TinyLogic® ULP A Universal Configuration Two-Input Logic Gates Battery Life www.fairchildsemi.com 2 Figure 2. SC70 (Top View) Figure 3. MicroPak™ (Top Through View) Figure 4. Pin 1 Orientation Notes: 3. AAA represents product code top mark (see Ordering Information). 4. Orientation of top mark determines pin one location. 5. Reading the top mark left to right, pin one is the lower left pin. Pin Definitions Pin # SC70 Pin # MicroPak™ Name 1 1 I1 2 2 GND 3 3 I0 Data Input 4 4 Y Output 5 5 VCC 6 6 I2 © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 Description Data Input Ground NC7SV57 / NC7V58 — TinyLogic® ULP A Universal Configuration Two-Input Logic Gates Pin Configurations Supply Voltage Data Input www.fairchildsemi.com 3 Inputs NC7SV57 NC7SV58 I2 I1 I0 Y = (I0) • (I2) + (I1) • (I2) Y = (I0) • (I2) + (I1) • (I2) L L L H L L L H L H L H L H L L H H L H H L L L H H L H L H H H L H L H H H H L H = HIGH Logic Level L = LOW Logic Level Function Selection Table 2-Input Logic Function Device Selection Connection Configuration 2-Input AND NC7SV57 Figure 5 2-Input AND with Inverted Input NC7SV58 Figure 11, Figure 12 2-Input AND with Both Inputs Inverted NC7SV57 Figure 8 2-Input NAND NC7SV58 Figure 10 2-Input NAND with Inverted Input NC7SV57 Figure 6, Figure 7 2-Input NAND with Both Inputs Inverted NC7SV58 Figure 13 2-Input OR NC7SV58 Figure 13 2-Input OR with Inverted Input NC7SV57 Figure 6, Figure 7 2-Input OR with Both Inputs Inverted NC7SV58 Figure 10 2-Input NOR NC7SV57 Figure 8 2-Input NOR with Inverted Input NC7SV58 Figure 10, Figure 11 2-Input NOR with Both Inputs Inverted NC7SV57 Figure 5 2-Input XOR NC7SV58 Figure 14 2-Input XNOR NC7SV57 Figure 9 © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 NC7SV57 / NC7V58 — TinyLogic® ULP A Universal Configuration Two-Input Logic Gates Function Table www.fairchildsemi.com 4 Figure 5 that can diagrams for a implementation is next to the board-level physical implementation of how the pins of the function should be connected. through Figure 9 show the logical functions be implemented using the NC7SV57. The show the DeMorgan’s equivalent logic duals given two-input function. The logical Figure 5. Figure 7. 2-Input AND Gate Figure 6. 2-Input NAND with Inverted B Input Figure 9. © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 2-Input NAND Gate with Inverted A Input Figure 8. 2-Input XNOR Gate 2-Input NOR Gate NC7SV57 / NC7V58 — TinyLogic® ULP A Universal Configuration Two-Input Logic Gates NC7SV57 Logic Configurations www.fairchildsemi.com 5 implementation is next to the board-level physical implementation of how the pins of the function should be connected. Figure 10 through Figure 14 show the logical functions that can be implemented using the NC7SV58. The diagrams show the DeMorgan’s equivalent logic duals for a given two-input function. The logical Figure 10. Figure 12. 2-Input NAND Gate Figure 11. 2-Input AND Gate with Inverted A Input 2-Input AND with Inverted B Input Figure 14. © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 Figure 13. 2-Input XOR Gate 2-Input OR Gate NC7SV57 / NC7V58 — TinyLogic® ULP A Universal Configuration Two-Input Logic Gates NC7SV58 Logic Configurations www.fairchildsemi.com 6 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter VCC Supply Voltage VIN DC Input Voltage VOUT IIK IOK IOH / IOL ICC or IGND TSTG PD ESD DC Output Voltage DC Input Diode Current DC Output Diode Current HIGH or LOW State (6) VCC=0V Min. Max. Unit -0.5 4.6 V -0.5 4.6 V -0.5 VCC + 0.5 -0.5 4.6 VIN < 0V ±50 VOUT < 0V -50 VOUT > VCC +50 DC Output Source / Sink Current DC VCC or Ground Current per Supply Pin Storage Temperature Range Power Dissipation at +85°C -65 V mA mA ±50 mA ±50 mA +150 °C MicroPak™-6 130 SC70-6 150 MicroPak2™-6 120 Human Body Model, JEDEC:JESD22-A114 4000 Charged Device Model, JEDEC:JESD22-C101 2000 mW V Note: 6. IO absolute maximum rating must be observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VCC Supply Voltage Operating VIN Input Voltage VOUT IOH/IOL TA Δt/ΔV θJA Output Voltage Output Current Conditions Thermal Resistance Max. Unit 0.9 3.6 V V 0 3.6 VCC=0V 0 3.6 HIGH or LOW State 0 VCC VCC=3.0V to 3.6V ±24.0 VCC=2.3V to 2.7V ±18.0 VCC=1.65V to 1.95V ±6.0 VCC=1.4V to 1.6V ±4.0 V mA VCC=1.1V to 1.3V ±2.0 VCC=0.9V ±0.1 µA +85 °C ns/V Operating Temperature, Free Air Minimum Input Edge Rate Min. -40 VIN=0.8V to 2.0, VCC=3.0V 10 SC70-6 425 MicroPak™-6 500 MicroPak2™-6 560 NC7SV57 / NC7V58 — TinyLogic® ULP A Universal Configuration Two-Input Logic Gates Absolute Maximum Ratings °C/W Note: 7. Unused inputs must be held HIGH or LOW. They may not float. © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 www.fairchildsemi.com 7 Symbol Parameter VCC Conditions 0.90 VP VN VH Positive Threshold Voltage Negative Threshold Voltage TA=-40 to 85°C Min. Max. Min. Max. 0.30 0.70 0.30 0.70 1.10 0.40 1.00 0.40 1.00 1.40 0.50 1.40 0.50 1.40 1.65 0.70 1.50 0.70 1.50 2.30 1.00 1.80 1.00 1.80 2.70 1.30 2.20 1.30 2.20 0.90 0.10 0.60 0.10 0.60 1.10 0.15 0.70 0.15 0.70 1.40 0.20 0.80 0.20 0.80 1.65 0.25 0.90 0.25 0.90 2.30 0.40 1.15 0.40 1.15 2.70 0.60 1.50 0.60 1.50 0.90 0.07 0.50 0.07 0.50 1.10 0.08 0.60 0.08 0.60 1.40 0.10 0.80 0.10 0.80 1.65 0.15 1.00 0.15 1.00 2.30 0.25 1.10 0.25 1.10 2.70 0.40 1.20 0.40 1.20 0.90 VCC-0.1 VCC-0.1 1.10 ≤ VCC ≤ 1.30 VCC-0.1 VCC-0.1 1.40 ≤ VCC ≤ 1.60 VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 2.30 ≤ VCC ≤ 2.70 VCC-0.2 VCC-0.2 2.70 ≤ VCC ≤ 3.60 VCC-0.2 VCC-0.2 Hysteresis Voltage 1.65 ≤ VCC ≤ 1.95 VOH TA=25°C HIGH Level Output Voltage IOH=-100µA 1.10 ≤ VCC ≤ 1.30 IOH=-2mA .75 x VCC .75 x VCC 1.40 ≤ VCC ≤ 1.60 IOH=-4mA .75 x VCC .75 x VCC 1.25 1.25 1.65 ≤ VCC ≤ 1.95 2.30 ≤ VCC ≤ 2.70 2.30 ≤ VCC ≤ 2.70 2.70 ≤ VCC ≤ 3.60 2.30 ≤ VCC ≤ 2.70 2.70 ≤ VCC ≤ 3.60 2.70 ≤ VCC ≤ 3.60 IOH=-6mA IOH=-12mA IOH=-18mA IOH=-24mA 2.0 2.0 1.8 1.8 2.2 2.2 1.7 1.7 2.4 2.4 2.2 Units V V V V NC7SV57 / NC7V58 — TinyLogic® ULP A Universal Configuration Two-Input Logic Gates DC Electrical Characteristics 2.2 Continued on following page…. © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 www.fairchildsemi.com 8 Symbol Parameter VCC TA=25°C Conditions Min. Max. 0.90 LOW Level Output Voltage 0.1 0.1 0.2 0.2 0.2 0.2 2.30 ≤ VCC ≤ 2.70 0.2 0.2 2.70 ≤ VCC ≤ 3.60 0.2 0.2 1.10 ≤ VCC ≤ 1.30 IOL=2mA .25 x VCC .25 x VCC 1.40 ≤ VCC ≤ 1.60 IOL=4mA .25 x VCC .25 x VCC 1.65 ≤ VCC ≤ 1.95 IOL=6mA 0.3 0.3 0.4 0.4 0.4 0.4 2.70 ≤ VCC ≤ 3.60 2.30 ≤ VCC ≤ 2.70 2.70 ≤ VCC ≤ 3.60 2.70 ≤ VCC ≤ 3.60 IIN 0.90 to 3.60 IOFF Power Off Leakage Current ICC Quiescent Supply Current 0.1 1.10 ≤ VCC ≤ 1.30 IOL=100µA Units Max. 1.40 ≤ VCC ≤ 1.60 2.30 ≤ VCC ≤ 2.70 Input Leakage Current Min. 0.1 1.65 ≤ VCC ≤ 1.95 VOL TA=-40 to 85°C 0 0.90 to 3.60 IOL=12mA V 0.6 0.6 0.4 0.4 IOL=24mA 0.55 0.55 0 ≤ VIN ≤ 3.6V ±0.1 ±0.5 µA 0 ≤ (VIN, VO) ≤ 3.60 0.5 0.5 µA VIN=VCC or GND 0.9 0.9 IOL=18mA VCC ≤ VIN ≤ 3.6V ±0.9 µA AC Electrical Characteristics Symbol Parameter VCC 0.90 1.10 ≤ VCC ≤ 1.30 tPHL, tPLH Propagation Delay 1.40 ≤ VCC ≤ 1.60 1.65 ≤ VCC ≤ 1.95 2.30 ≤ VCC ≤ 2.70 2.70 ≤ VCC ≤ 3.60 TA=25°C Conditions Min. CL=15pF, RL=1MΩ Typ. TA=-40 to 85°C Min. Typ. Min. Units 15.0 CL=15pF, RL=2KΩ CL=30pF, RL=500Ω 4.0 8.0 16.5 3.3 31.0 2.0 6.0 10.0 2.0 12.0 2.0 4.0 9.1 1.9 10.0 1.5 3.1 6.2 1.4 6.7 1.2 2.5 5.4 1.2 6.1 ns CIN Input Capacitance 0 8 pF COUT Output Capacitance 0 12 pF CPD Power Dissipation Capacitance 0.90 to 3.60 10 pF © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 Figure VI=0V or VCC, f=10MHz Figure 15 Figure 16 NC7SV57 / NC7V58 — TinyLogic® ULP A Universal Configuration Two-Input Logic Gates DC Electrical Characteristics (Continued) www.fairchildsemi.com 9 Figure 15. AC Test Circuit Figure 16. AC Waveforms VCC Symbol 3.3V ± 0.3V 2.5V ± 0.2V 1.8V ± 0.15V 1.5V ± 0.10V 1.2V ± 0.10V 0.9V Vmi 1.5V VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 Vmo 1.5V VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 NC7SV57 / NC7V58 — TinyLogic® ULP A Universal Configuration Two-Input Logic Gates AC Loadings and Waveforms www.fairchildsemi.com 10 SYMM C L 2.00±0.20 0.65 A 0.50 MIN 6 4 B PIN ONE 1.25±0.10 1 1.90 3 0.30 0.15 (0.25) 0.40 MIN 0.10 0.65 A B 1.30 LAND PATTERN RECOMMENDATION 1.30 1.00 0.80 SEE DETAIL A 1.10 0.80 0.10 C 0.10 0.00 C 2.10±0.30 SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED GAGE PLANE (R0.10) 0.25 0.10 0.20 A) THIS PACKAGE CONFORMS TO EIAJ SC-88, 1996. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. D) DRAWING FILENAME: MKT-MAA06AREV6 30° 0° 0.46 0.26 DETAIL A SCALE: 60X Figure 17. 6-Lead, SC70, EIAJ SC-88a, 1.25mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. NC7SV57 / NC7V58 — TinyLogic® ULP A Universal Configuration Two-Input Logic Gates Physical Dimensions Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/analog/pdf/sc70-6_tr.pdf Package Designator P6X © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 3000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 11 2X 0.05 C 1.45 B 2X (1) 0.05 C (0.254) (0.49) 5X 1.00 (0.75) PIN 1 IDENTIFIER 5 (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C 0.25 6X 0.15 1.0 DETAIL A 0.10 0.05 0.45 0.35 0.10 0.00 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 0.5 (0.05) 6X Notes: BOTTOM VIEW (0.13) 4X DETAIL A PIN 1 TERMINAL 0.075 X 45 CHAMFER 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.5M-1994 4. FILENAME AND REVISION: MAC06AREV4 5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY OTHER LINE IN THE MARK CODE LAYOUT. Figure 18. 6-Lead, MicroPak™, 1.0mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. NC7SV57 / NC7V58 — TinyLogic® ULP A Universal Configuration Two-Input Logic Gates Physical Dimensions Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. Package Designator L6X © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 12 0.89 0.35 0.05 C 1.00 2X B A 5X 0.40 PIN 1 MIN 250uM 0.66 1.00 1X 0.45 6X 0.19 0.05 C TOP VIEW RECOMMENDED LAND PATTERN FOR SPACE CONSTRAINED PCB 2X 0.90 0.05 C 0.35 0.55MAX C 5X 0.52 SIDE VIEW 0.73 (0.08) 4X 1 DETAIL A 2 1X 0.57 0.09 0.19 6X 3 0.20 6X ALTERNATIVE LAND PATTERN FOR UNIVERSAL APPLICATION (0.05) 6X 5X 0.35 0.25 0.35 6 5 0.60 4 (0.08) 4X BOTTOM VIEW 0.10 .05 C C B A 0.40 0.30 NOTES: A. COMPLIES TO JEDEC MO-252 STANDARD B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LANDPATTERN RECOMMENDATION IS BASED ON FSC DESIGN. E. DRAWING FILENAME AND REVISION: MGF06AREV3 Figure 19. 0.075X45° CHAMFER DETAIL A PIN 1 LEAD SCALE: 2X 6-Lead, MicroPak2, 1x1mm Body, .35mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. NC7SV57 / NC7V58 — TinyLogic® ULP A Universal Configuration Two-Input Logic Gates Physical Dimensions Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf . Package Designator FHX © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 13 NC7SV57 / NC7V58 — TinyLogic® ULP A Universal Configuration Two-Input Logic Gates © 2002 Fairchild Semiconductor Corporation NC7SV57 • NC7SV58 • Rev. 1.0.4 www.fairchildsemi.com 14