74AUP1T97 TinyLogic® Low Power Configurable Gate with Voltage-Level Translator Features Description Single Supply Voltage Translator - 1.8V to 3.3V Input at VCC=3.3V - 1.8V to 2.5V Input at VCC=2.5V 2.3V to 3.6V VCC Supply Voltage Operation The 74AUP1T97 is a universal configurable 2-input logic gate that provides single supply voltage level translation. This device is designed for applications with inputs switching levels that accept 1.8V low voltage CMOS signals while operating from either a single 2.5V or 3.3V supply voltage. The 74AUP1T97 is an ideal low power solution for mixed voltage signal applications especially for battery-powered portable applications. This product guarantees very low static and dynamic power consumption across entire voltage range. All inputs are implemented with hysteresis to allow for slower transition input signals and better switching noise immunity. 3.6V Over-Voltage Tolerant I/O’s at VCC from 2.3V to 3.6V Power-Off High-Impedance Inputs and Outputs Low Dynamic Power Consumption - CPD=2.7pF Typical at 3.3V Ultra-Small MicroPak™ Packages Low Static Power Consumption - ICC=0.9µA Maximum The 74AUP1T97 provides for multiple functions as determined by various configurations of the three inputs. The potential logic functions provided are MUX, AND, NAND, OR, and NOR, inverter and buffer. Refer to Figures 3 to 9. Ordering Information Part Number Top Mark Package Packing Method 74AUP1T97L6X AH 6-Lead MicroPak™, 1.0mm Wide 5000 Units on Tape & Reel 74AUP1T97FHX AH 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch 5000 Units on Tape & Reel © 2008 Fairchild Semiconductor Corporation 74AUP1T97 • Rev. 1.0.3 www.fairchildsemi.com 74AUP1T97 — TinyLogic® Low Power Configurable Gate with Voltage-Level Translation October 2010 A 3 4 B C 1 6 Figure 1. Logic Diagram (Positive Logic) Pin Configurations B 1 6 C GND 2 5 VCC A 3 4 Y Figure 2. MicroPak™ (Top Through View) Pin Definitions Pin # Name 1 B 2 GND 3 A Data Input 4 Y Output 5 VCC 6 C © 2008 Fairchild Semiconductor Corporation 74AUP1T97 • 1.0.3 Description Data Input Ground Supply Voltage Data Input Y 74AUP1T97 — TinyLogic® Low Power Configurable Gate with Voltage-Level Translator Logic Diagram www.fairchildsemi.com 2 Inputs 74AUPIT97 C B A Y=Output L L L L L L H L L H L H L H H H H L L L H L H H H H L L H H H H H = HIGH Logic Level L = LOW Logic Level Function Selection Table Logic Function Connection Configuration 2-to-1 MUX Figure 3 2-Input AND Gate Figure 4 2-Input OR Gate with One Inverted Input Figure 5 2-Input NAND Gate with One Inverted Input Figure 5 2-Input AND Gate with One Inverted Input Figure 6 2-Input NOR Gate with One Inverted Input Figure 6 2-Input OR Gate Figure 7 Inverter Figure 8 Buffer Figure 9 © 2008 Fairchild Semiconductor Corporation 74AUP1T97 • 1.0.3 74AUP1T97 — TinyLogic® Low Power Configurable Gate with Voltage-Level Translator Function Table www.fairchildsemi.com 3 implementation is next to the board-level physical implementation of how the pins of the function should be connected. Figure 3 through Figure 9 show the logical functions that can be implemented using the 74AUP1T97. The diagrams show the DeMorgan’s equivalent logic duals for a given two-input function. The logical VCC VCC C B B Y A A 1 6 2 5 3 4 C C Y Y A A GND Note: 1. When C is L, Y=B. 2. When C is H, Y=A. 1 6 2 5 3 4 C Y GND Figure 3. 2-to-1 MUX Figure 4. 2-Input AND Gate VCC VCC C C Y B Y B A C Y A A 1 6 2 5 3 4 C C Y B Y GND 1 6 2 5 3 4 C Y GND Figure 5. Input OR Gate with One Inverted Input Figure 6. 2-Input AND Gate with One Inverted Input 2-Input NAND Gate with One Inverted Input 2-Input NOR Gate with One Inverted Input VCC VCC C Y B B 1 6 2 5 3 4 C C Y Y GND 1 6 2 5 3 4 C Y 74AUP1T97 — TinyLogic® Low Power Configurable Gate with Voltage-Level Translator 74AUP1T97 Logic Configurations GND Figure 8. Figure 7. 2-Input OR Gate Inverter VCC B B Y 1 6 2 5 3 4 Y GND Figure 9. © 2008 Fairchild Semiconductor Corporation 74AUP1T97 • 1.0.3 Buffer www.fairchildsemi.com 4 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter VCC Supply Voltage VIN DC Input Voltage VOUT IIK IOK IOH / IOL IO ICC or IGND TSTG HIGH or LOW State DC Output Voltage (3) VCC=0V DC Input Diode Current DC Output Diode Current Min. Max. Unit -0.5 4.6 V -0.5 4.6 V -0.5 VCC + 0.5 -0.5 4.6 VIN < 0V -50 VOUT < 0V -50 VOUT > VCC +50 V mA mA DC Output Source / Sink Current ±50 mA Continuous Output Current ±20 mA DC VCC or Ground Current per Supply Pin ±50 mA +150 °C TJ Junction Temperature Under Bias +150 °C TL Junction Lead Temperature, Soldering 10s +260 °C PD ESD Storage Temperature Range Power Dissipation at +85°C -65 MicroPak-6 130 MicroPak2-6 120 Human Body Model, JEDEC:JESD22-A114 5000+ Charged Device Model, JEDEC:JESD22-C101 2000 mW V Note: 3. IO absolute maximum rating must be observed. Recommended Operating Conditions(4) The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VCC Supply Voltage VIN Input Voltage VOUT Output Voltage IOH/IOL Output Current TA Operating Temperature, Free Air θJA Thermal Resistance Conditions Min. Max. Unit 2.3 3.6 V 0 3.6 V VCC=0V 0 3.6 HIGH or LOW State 0 VCC VCC=3.0V to 3.6V ±4.0 VCC=2.3V to 2.7V ±3.1 -40 +85 MicroPak-6 500 MicroPak2-6 560 V 74AUP1T97 — TinyLogic® Low Power Configurable Gate with Voltage-Level Translator Absolute Maximum Ratings mA °C °C/W Note: 4. Unused inputs must be held HIGH or LOW. They may not float. © 2008 Fairchild Semiconductor Corporation 74AUP1T97 • 1.0.3 www.fairchildsemi.com 5 Symbol Parameter VCC VP Positive Threshold Voltage VN Negative Threshold Voltage VH Hysteresis Voltage HIGH Level Output Voltage Min. Max. 2.3V to 2.7V 0.60 1.10 0.60 1.10 3.0V to 3.6V 0.75 1.16 0.75 1.19 2.3V to 2.7V 0.35 0.60 0.35 0.60 3.0V to 3.6V 0.50 0.85 0.50 0.85 2.3V to 2.7V 0.23 0.60 0.10 0.60 3.0V to 3.6V 0.25 0.56 0.15 0.56 2.3V 2.3V ≤ VCC ≤ 3.6V LOW Level Output Voltage 2.3V 3.0V IIN IOFF Input Leakage Current Power Off Leakage Current 0V to 3.6V 0V ΔIOFF Additional Power Off Leakage Current 0V to 0.2V ICC Quiescent Supply Current 2.3V to 3.6V ΔICC IOH=-20µA VCC-0.1 VCC-0.1 IOH=-2.3mA 2.05 1.97 IOH=-3.1mA 1.90 1.85 IOH=-2.7mA 2.72 2.67 IOH=-4mA 2.60 Units V V V V 2.55 IOL=20µA 0.10 0.10 IOL=2.3mA 0.31 0.33 IOL=3.1mA 0.44 0.45 IOL=2.7mA 0.31 0.33 IOL=4.0mA 0.44 0.45 0 ≤ VIN ≤ 3.6 ±0.10 ±0.50 µA 0 ≤ (VIN,VO) ≤ 3.6 0.10 0.50 µA VIN or VO=0V to 3.6V 0.20 0.60 µA VIN=VCC or GND 0.50 0.90 VCC ≤ VIN ≤ 3.6V ±0.90 2.3V to 2.7V One Input at 0.3V or 1.1V, other Inputs at 0 or VCC 4 3.0V to 3.6V One Input at 0.45V or 1.2V, other Inputs at 0 or VCC 12 Increase in ICC per Input © 2008 Fairchild Semiconductor Corporation 74AUP1T97 • 1.0.3 TA=-40 to +85°C Max. 3.0V VOL TA=+25°C Min. 2.3V ≤ VCC ≤ 3.6V VOH Conditions V µA µA 74AUP1T97 — TinyLogic® Low Power Configurable Gate with Voltage-Level Translator DC Electrical Characteristics www.fairchildsemi.com 6 Symbol Parameter VCC TA=+25°C Conditions Min. Typ. Max. Typ. Max. 2.30V ≤ VCC ≤ 2.70V, VIN=1.65V to 1.95V 1.1 3.7 5.5 1.1 6.8 2.30V ≤ VCC ≤ 2.70V, VIN=2.30V to 2.70V 1.1 3.8 6.5 1.1 7.0 1.1 3.9 6.0 1.1 6.5 1.0 3.3 4.9 1.0 8.0 3.00V ≤ VCC ≤ 3.60V, VIN=2.30V to 2.70V 1.0 3.2 4.6 1.0 5.8 3.00V ≤ VCC ≤ 3.60V, VIN=3.00V to 3.60V 1.0 3.1 4.7 1.0 5.5 2.30V ≤ VCC ≤ 2.70V, VIN=1.65V to 1.95V 1.3 4.1 6.5 1.0 7.9 2.30V ≤ VCC ≤ 2.70V, VIN=2.30V to 2.70V 1.3 4.0 6.2 1.0 7.1 1.3 3.7 5.7 1.0 6.5 1.3 3.5 5.6 1.0 8.5 3.00V ≤ VCC ≤ 3.60V, VIN=2.30V to 2.70V 1.3 3.4 5.3 1.0 6.1 3.00V ≤ VCC ≤ 3.60V, VIN=3.00V to 3.60V 1.3 3.3 5.2 1.0 5.9 2.30V ≤ VCC ≤ 2.70V, VIN=1.65V to 1.95V 1.5 4.6 6.9 1.0 8.7 2.30V ≤ VCC ≤ 2.70V, VIN=2.30V to 2.70V 1.5 4.4 6.8 1.0 7.9 1.5 4.2 6.3 1.0 7.4 1.3 3.9 6.2 1.0 9.1 3.00V ≤ VCC ≤ 3.60V, VIN=2.30V to 2.70V 1.3 3.8 5.6 1.0 6.8 3.00V ≤ VCC ≤ 3.60V, VIN=3.00V to 3.60V 1.3 3.8 5.6 1.0 6.2 2.30V ≤ VCC ≤ 2.70V, VIN=1.65V to 1.95V 1.3 4.2 7.9 1.3 8.5 2.30V ≤ VCC ≤ 2.70V, VIN=2.30V to 2.70V 1.3 3.9 7.9 1.3 8.5 1.0 3.7 7.3 1.0 8.9 1.3 3.5 6.1 1.3 7.9 3.00V ≤ VCC ≤ 3.60V, VIN=2.30V to 2.70V 1.1 3.0 5.9 1.1 6.8 3.00V ≤ VCC ≤ 3.60V, VIN=3.00V to 3.60V 1.0 2.7 5.7 1.0 6.5 2.30V ≤ VCC ≤ 2.70V, VIN=3.0V to 3.60V CL=5pF, 3.00V ≤ VCC ≤ 3.60V, RL=1MΩ VIN=1.65V to 1.95V 2.30V ≤ VCC ≤ 2.70V, VIN=3.0V to 3.60V CL=10pF, 3.00V ≤ VCC ≤ 3.60V, RL=1MΩ VIN=1.65V to 1.95V tPHL, tPLH Propagation Delay TA=-40 to +85°C 2.30V ≤ VCC ≤ 2.70V, VIN=3.0V to 3.60V CL=15pF, 3.00V ≤ VCC ≤ 3.60V, RL=1MΩ VIN=1.65V to 1.95V 2.30V ≤ VCC ≤ 2.70V, VIN=3.0V to 3.60V CL=30pF, 3.00V ≤ VCC ≤ 3.60V, RL=1MΩ VIN=1.65V to 1.95V Units Figure ns Figure 10 Figure 11 CIN Input Capacitance 0 2.1 pF COUT Output Capacitance 0 3.0 pF Power Dissipation Capacitance 2.30V ≤ VCC ≤ 2.70V 2.0 CPD 3.00V ≤ VCC ≤ 3.60V 2.7 © 2008 Fairchild Semiconductor Corporation 74AUP1T97 • 1.0.3 74AUP1T97 — TinyLogic® Low Power Configurable Gate with Voltage-Level Translator AC Electrical Characteristics pF www.fairchildsemi.com 7 Figure 10. AC Test Circuit Figure 11. AC Waveforms VCC Symbol 3.3V ± 0.3V 2.5V ± 0.2V Vmi VIN/2 VIN/2 Vmo VCC/2 VCC/2 © 2008 Fairchild Semiconductor Corporation 74AUP1T97 • 1.0.3 74AUP1T97 — TinyLogic® Low Power Configurable Gate with Voltage-Level Translator AC Loadings and Waveforms www.fairchildsemi.com 8 2X 0.05 C 1.45 B 2X (1) 0.05 C (0.254) (0.49) 5X 1.00 (0.75) PIN 1 IDENTIFIER 5 (0.52) 1X A TOP VIEW 0.55MAX (0.30) 6X PIN 1 0.05 C 0.05 0.00 RECOMMENED LAND PATTERN 0.05 C C 0.25 0.15 6X 1.0 DETAIL A 0.10 0.05 0.45 0.35 0.10 0.00 6X C B A C 0.40 0.30 0.35 5X 0.25 0.40 5X 0.30 0.5 (0.05) 6X DETAIL A PIN 1 TERMINAL 0.075 X 45 CHAMFER (0.13) 4X BOTTOM VIEW Notes: 1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD 2. DIMENSIONS ARE IN MILLIMETERS 3. DRAWING CONFORMS TO ASME Y14.5M-1994 4. FILENAME AND REVISION: MAC06AREV4 5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY OTHER LINE IN THE MARK CODE LAYOUT. Figure 12. 6-Lead, MicroPak™, 1.0mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. 74AUP1T97 — TinyLogic® Low Power Configurable Gate with Voltage-Level Translator Physical Dimensions Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf. Package Designator L6X © 2008 Fairchild Semiconductor Corporation 74AUP1T97 • 1.0.3 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 9 0.89 0.35 0.05 C 1.00 2X B A 5X 0.40 PIN 1 MIN 250uM 0.66 1.00 1X 0.45 6X 0.19 0.05 C TOP VIEW RECOMMENDED LAND PATTERN FOR SPACE CONSTRAINED PCB 2X 0.90 0.05 C 0.35 0.55MAX C 5X 0.52 SIDE VIEW 0.73 (0.08) 4X 1 DETAIL A 2 1X 0.57 0.09 0.19 6X 3 0.20 6X ALTERNATIVE LAND PATTERN FOR UNIVERSAL APPLICATION (0.05) 6X 5X 0.35 0.25 6 5 4 0.35 0.60 (0.08) 4X 0.10 .05 C C B A 0.40 0.30 BOTTOM VIEW NOTES: A. COMPLIES TO JEDEC MO-252 STANDARD B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. LANDPATTERN RECOMMENDATION IS BASED ON FSC DESIGN. E. DRAWING FILENAME AND REVISION: MGF06AREV3 Figure 13. 0.075X45° CHAMFER DETAIL A PIN 1 LEAD SCALE: 2X 6-Lead, MicroPak2™, 1x1mm Body, .35mm Pitch Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. 74AUP1T97 — TinyLogic® Low Power Configurable Gate with Voltage-Level Translator Physical Dimensions Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. Tape and Reel Specifications Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications: http://www.fairchildsemi.com/packaging/MicroPAK2_6L_tr.pdf. Package Designator FHX © 2008 Fairchild Semiconductor Corporation 74AUP1T97 • 1.0.3 Tape Section Cavity Number Cavity Status Cover Type Status Leader (Start End) 125 (Typical) Empty Sealed Carrier 5000 Filled Sealed Trailer (Hub End) 75 (Typical) Empty Sealed www.fairchildsemi.com 10 74AUP1T97 — TinyLogic® Low Power Configurable Gate with Voltage-Level Translator © 2008 Fairchild Semiconductor Corporation 74AUP1T97 • 1.0.3 www.fairchildsemi.com 11