ONSEMI NUP4114UCW1

NUP4114UCW1
Transient Voltage
Suppressors
ESD Protection Diodes with Low
Clamping Voltage
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The NUP4114UCW1 transient voltage suppressor is designed to
protect high speed data lines from ESD. Ultra−low capacitance and
high level of ESD protection makes this device well suited for use in
USB 2.0 high speed applications.
MARKING
DIAGRAM
1
SC−88
W1 SUFFIX
CASE 419B
Features
• Low Capacitance 1.5 pF
• Low Clamping Voltage
• Small Body Outline Dimensions:
•
•
•
•
•
•
6
X4 MG
G
1
X4 = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
0.082″ x 0.078″ (2.10 mm x 1.25 mm)
Low Body Height: 0.043″ (1.10 mm)
Stand−off Voltage: 5.5 V
Low Leakage
Response Time is Typically < 1.0 ns
IEC61000−4−2 Level 4 ESD Protection
This is a Pb−Free Device
PIN CONFIGURATION
AND SCHEMATIC
Mechanical Characteristics:
CASE: Void-free, transfer-molded, thermosetting plastic
Epoxy Meets UL 94 V−0
LEAD FINISH: 100% Matte Sn (Tin)
MOUNTING POSITION: Any
QUALIFIED MAX REFLOW TEMPERATURE: 260°C
I/O 1
6 I/O
VN 2
5 VP
I/O 3
4 I/O
Device Meets MSL 1 Requirements
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
ORDERING INFORMATION
Rating
Symbol
Value
Unit
Operating Junction Temperature Range
TJ
−40 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
°C
±8
±15
kV
IEC 61000−4−2 (ESD)
Contact
Air
Device
NUP4114UCW1T2G
Package
Shipping
SC−88 3000/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
See Application Note AND8308/D for further description of survivability specs.
© Semiconductor Components Industries, LLC, 2010
January, 2010 − Rev. 1
1
Publication Order Number:
NUP4114UCW1/D
NUP4114UCW1
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise noted)
Symbol
I
Parameter
IF
IPP
Maximum Reverse Peak Pulse Current
VC
Clamping Voltage @ IPP
VRWM
IR
VBR
Working Peak Reverse Voltage
Test Current
IF
Forward Current
VF
Forward Voltage @ IF
Ppk
Peak Power Dissipation
V
IR VF
IT
Breakdown Voltage @ IT
IT
C
VC VBR VRWM
Maximum Reverse Leakage Current @ VRWM
IPP
Uni−Directional TVS
Capacitance @ VR = 0 and f = 1.0 MHz
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
VRWM
VBR
Conditions
Min
Typ
(Note 1)
IT = 1 mA, (Note 2)
Reverse Leakage Current
IR
VRWM = 5.5 V
Clamping Voltage
VC
IPP = 1 A (Note 3)
Clamping Voltage
VC
Clamping Voltage
Max
Unit
5.5
V
6.0
V
1.0
mA
8.0
11
V
IPP = 6 A (Note 3)
8.7
15
V
VC
IPP = 1 A (Note 4)
9.0
12
V
ESD Clamping Voltage
VC
Per IEC61000−4−2 (Note 5)
Maximum Peak Pulse Current
IPP
8 x 20 ms Waveform (Note 3)
12
A
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz between I/O Pins and GND
3.0
pF
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz between I/O Pins
1.5
pF
See Figures 1 & 2
1. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC
or continuous peak operating voltage level.
2. VBR is measured at pulse test current IT.
3. Nonrepetitive current pulse (Pin 5 to Pin 2).
4. Nonrepetitive current pulse (I/O to GND).
5. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
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2
NUP4114UCW1
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
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3
NUP4114UCW1
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test
Voltage
(kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
% OF PEAK PULSE CURRENT
100
PEAK VALUE IRSM @ 8 ms
tr
90
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
80
70
60
HALF VALUE IRSM/2 @ 20 ms
50
40
30
tP
20
10
0
0
20
40
t, TIME (ms)
60
Figure 5. 8 X 20 ms Pulse Waveform
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4
80
NUP4114UCW1
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE W
D
e
6
5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. 419B−01 OBSOLETE, NEW STANDARD 419B−02.
4
HE
−E−
1
2
3
b 6 PL
0.2 (0.008)
M
E
MILLIMETERS
MIN
NOM MAX
0.80
0.95
1.10
0.00
0.05
0.10
0.20 REF
0.10
0.21
0.30
0.10
0.14
0.25
1.80
2.00
2.20
1.15
1.25
1.35
0.65 BSC
0.10
0.20
0.30
2.00
2.10
2.20
DIM
A
A1
A3
b
C
D
E
e
L
HE
M
A3
INCHES
NOM MAX
0.037 0.043
0.002 0.004
0.008 REF
0.004 0.008 0.012
0.004 0.005 0.010
0.070 0.078 0.086
0.045 0.049 0.053
0.026 BSC
0.004 0.008 0.012
0.078 0.082 0.086
MIN
0.031
0.000
C
A
A1
L
SOLDERING FOOTPRINT*
0.50
0.0197
0.65
0.025
0.65
0.025
0.40
0.0157
1.9
0.0748
SCALE 20:1
mm Ǔ
ǒinches
SC−88/SC70−6/SOT−363
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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NUP4114UCW1/D