FR014H5JZ (14mΩ, -30V) High-Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression Features Description Up to -30V Reverse-Bias Protection +32V 24-Hour “Withstand” Rating Nano Seconds of Reverse-Bias Blocking Response Time 14mΩ Typical Series Resistance at 5V Integrated TVS Over Voltage Suppression MLP 3.3x3.3 Package Size RoHs Compliant USB Tested and Compatible USB 1.0, 2.0 and 3.0 Devices Automotive Peripherals Fairchild circuit protection is proud to offer a new type of reverse bias protection devices. The FR devices are low resistance, series switches that, in the event of a reverse bias condition, shut off power and block the negative voltage to help protect downstream circuits. The FR devices are optimized for the application to offer best in class reverse bias protection and voltage capabilities while minimizing size, series voltage drop, and normal operating power consumption. Applications Reverse bias is an increasingly common fault event that may be generated by user error, improperly installed batteries, automotive environments, erroneous connections to third-party chargers, negative “hot plug” transients, inductive transients, and readily available negatively biased rouge USB chargers. In the event of a reverse bias application, FR014H5JZ devices effectively provide a full voltage block and can easily protect -0.3V rated silicon. USB Charging Mobile Devices Mobile Medical POS Systems Toys Any DC Barrel Jack Powered Device Any DC Devices subject to Negative Hot Plug or Inductive Transients From a power perspective, in normal bias, a 14mΩ FR device in a 1.5A application will generate only 21mV of voltage drop or 32mW of power loss. In reverse bias, FR devices dissipate less then 20µW in a 16V reverse bias event. This type of performance is not possible with a diode solution. Benefits extend beyond the device. Due to low power dissipation, not only is the device small, but heat sinking requirements and cost can be minimized as well. Ordering Information Part Number Top Mark Package Packing Method FR014H5JZ 14H 8-Lead, Molded Leadless Package (MLP), Dual, 3.3mm Square 3000 on Tape & Reel; 13-inch Reel, 12mm Tape © 2012 Fairchild Semiconductor Corporation FR014H5JZ • Rev. C1 www.fairchildsemi.com FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression July 2012 FR014H5JZ OV Bypass Protection POS Inrush Reducer Startup Diode POS NEG CTL Power Source (USB Connector) Power Switch NEG I IN USB Device Circuit VIN CTL Protected USB Device Circuit Figure 1. Block Diagram Figure 2. Typical Schematic Pin Configuration Figure 3. Pin Assignments Pin Definitions Name Pin Description POS 5, 6, 7, 8 CTL 4 The control pin of the device. A negative voltage to the POS pin turns the switch on and a positive voltage turns the switch to a high-impedance state. NEG 1, 2, 3 The positive terminal of the load circuit to be protected. Current flows out of this pin during normal operation. The positive terminal of the power source. Current flows into this pin during normal operation. © 2012 Fairchild Semiconductor Corporation FR014H5JZ • Rev. C1 www.fairchildsemi.com 2 FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression Diagrams Values are at TA=25°C unless otherwise noted. Symbol V+ MAX_OP V+ 24 V- MAX_OP Parameter Steady-State Normal Operating Voltage between POS and CTL Pins (VIN = V+ MAX_OP, IIN = 1.5A, Switch On) +25 24-Hour Normal Operating Voltage Withstand Capability between POS (1) and CTL Pins (VIN = V+ 24, IIN = 1.5A, Switch On) +32 Steady-State Reverse Bias Standoff Voltage between POS and CTL Pins (VIN = V- MAX_OP) -30 IIN Input Current TJ Operating Junction Temperature PD Values Continuous Power Dissipation (2) (see Figure 4) TC = 25°C (2) A 150 °C 2.3 (see Figure 4) V 9 36 TA = 25°C Unit W (2) IDIODE_CONT Steady-State Diode Continuous Forward Current from POS to NEG (see Figure 4) IDIODE_PULSE Pulsed Diode Forward Current from POS to NEG (300µs Pulse) Figure 5) (2) (see Human Body Model, JESD22-A114 ESD 2 A 450 8 Charged Device Model, JESD22-C101 Electrostatic NEG is shorted to CTL Discharge and connected to GND System Model, Capability IEC61000-4-2 No external connection between NEG and CTL 2 Contact 8 Air 15 Contact 3 Air 4 kV Notes: 1. The V+24 rating is NOT a survival guarantee. It is a statistically calculated survivability reference point taken on qualification devices, where the predicted failure rate is less than 0.01% at the specified voltage for 24 hours. It is intended to indicate the device’s ability to withstand transient events that exceed the recommended operating voltage rating. Specification is based on qualification devices tested using accelerated destructive testing at higher voltages, as well as production pulse testing at the V+24 level. Production device field life results may vary. Results are also subject to variation based on implementation, environmental considerations, and circuit dynamics. Systems should never be designed with the intent to normally operate at V+24 levels. Contact Fairchild Semiconductor for additional information. 2. The device power dissipation and thermal resistance (Rθ) are characterized with device mounted on the following FR4 printed circuit boards, as shown in Figure 4 and Figure 5 Figure 4. 1 Square Inch of 2-ounce copper Figure 5. Minimum Pads of 2-ounce Copper Thermal Characteristics Symbol Parameter RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient © 2012 Fairchild Semiconductor Corporation FR014H5JZ • Rev. C1 Value 3.4 (2) (see Figure 4) 50 Unit °C/W www.fairchildsemi.com 3 FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression Absolute Maximum Ratings Values are at TA = 25°C unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. VIN = +4V, IIN = 1.5A 18 23 VIN = +5V, IIN = 1.5A 14 19 VIN = +5V, IIN = 1.5A, TJ = 125°C 20 VIN = +12V, IIN = 1.5A 11 14 2.4 3.0 Unit Positive Bias Characteristics RON Device Resistance, Switch On VON Input Voltage, VIN, at which Voltage at POS, VPOS, Reaches a Certain Level at Given Current ∆VON / ∆TJ VF IBIAS IIN = 100mA, VPOS - VNEG = 50mV, VCTL = 0V 2.0 Temperature Coefficient of VON mΩ -3.52 Diode Forward Voltage VCTL = VNEG, IDIODE = 0.1A, Pulse width < 300µs Bias Current Flowing into POS Pin during Normal Bias Operation VPOS = 5V, VCTL = 0V, No Load 0.57 0.63 V mV/°C 0.70 30 V nA Negative Bias Characteristics V- MAX_OP -30 Reverse Bias Breakdown Voltage Reverse Bias Breakdown Voltage Temperature Coefficient IIN = -250µA, VCTL = VNEG =0V I- Leakage Current from NEG to POS in Reverse-Bias Condition VPOS = -20V, VCTL = VNEG = 0V tRN Time to Respond to Negative Bias Condition VCTL = 5V, VPOS = 0V, CLOAD = 10µF, Reverse Bias Startup Inrush Current = 0.2A ∆V- MAX_OP / ∆TJ V 22.5 mV/°C 1 µA 50 ns 31.2 V Integrated TVS Performance VZ Breakdown Voltage @ IT IR Leakage Current from NEG to CTL IPPM Max Pulse Current from NEG to CTL VC Clamping Voltage form NEG to CTL at IPPM IEC61000-4-5 8x20µs pulse IT = 1mA, 300µs Pulse 28.5 30 VNEG = +25V, VCTL = 0V 1.5 10 VNEG = -25V, VCTL = 0V -1.5 -10 VNEG > VCTL 0.8 VNEG < VCTL -0.9 VNEG > VCTL 34 VNEG < VCTL -34 µA A V Dynamic Characteristics CI Input Capacitance between POS and CTL CS Switch Capacitance between POS and NEG CO Output Capacitance between NEG and CTL RC Control Internal Resistance © 2012 Fairchild Semiconductor Corporation FR014H5JZ • Rev. C1 2440 VIN = -5V, VCTL = VNEG = 0V, f = 1MHz 564 pF 2526 3.6 Ω www.fairchildsemi.com 4 FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression Electrical Characteristics 24 21 Input Voltage, VIN = 4V 18 15 5V 12 9 9V 6 12V 16V 3 0 0 2 4 6 8 10 12 14 16 18 20 3.6 3.4 ON THE SWITCH (V) VON, MINIMUM INPUT VOLTAGE TURNING RON, SWITCH ON-RESISTANCE (m) TJ = 25°C unless otherwise specified. 3.2 3.0 2.8 2.6 2.4 2.2 0.0 0.3 0.6 1.0 o IIN = 0.1A TJ = 25 C 0.8 0.9A 0.6 1.5A 0.4 0.2 1 3 5 7 9 11 13 15 17 19 21 2.1 21 IIN = 0.1A 18 VIN = 5V 15 12 9 12V 6 3 0 -75 -50 -25 0 25 50 75 100 125 150 o Figure 9. Switch On Resistance vs. Junction Temperature at 0.1A 24 1000 IIN = 1.5A PEAK PACKAGE POWER (W) RON, SWITCH ON-RESISTANCE (m) 1.8 TJ, JUNCTION TEMPERATURE ( C) Figure 8. Effective Switch Resistance RSW vs. Input Voltage VIN 18 VIN = 5V 15 12 9 12V 6 3 0 -75 1.5 24 VIN, INPUT VOLTAGE (V) 21 1.2 Figure 7. Minimum Input Voltage to Turn On Switch vs. Current at 50mV Switch Voltage Drop RON, SWITCH ON-RESISTANCE (m) RSW, EFFECTIVE SWITCH RESISTANCE () Figure 6. Switch On Resistance vs. Switch Current 0.0 0.9 IIN, INPUT CURRENT (A) IIN, INPUT CURRENT (A) -50 -25 0 25 50 75 10 1 0.1 1E-4 100 125 150 1E-3 0.01 0.1 1 10 100 1000 t, PULSE WIDTH (s) o TJ, JUNCTION TEMPERATURE ( C) Figure 10. Switch On Resistance vs. Junction Temperature at 1.5A © 2012 Fairchild Semiconductor Corporation FR014H5JZ • Rev. C1 100 Figure 11. Single-Pulse Maximum Power vs. Time www.fairchildsemi.com 5 FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression Typical Characteristics FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression Typical Characteristics IF, STARTUP DIODE FORWARD CURRENT (A) TJ = 25°C unless otherwise specified. 100 VNEG = VCTL = 0V 10 o TJ = 125 C 1 o 25 C 0.1 o -55 C 0.01 1E-3 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 VF, STARTUP DIODE FORWARD VOLTAGE (V) Figure 12. Startup Diode Current vs. Forward Voltage © 2012 Fairchild Semiconductor Corporation FR014H5JZ • Rev. C1 www.fairchildsemi.com 6 FR014H5JZ POS NEG I IN CTL Power Source (USB Connector) USB Device Circuit VIN Protected USB Device Circuit Figure 13. Typical Application Circuit for USB Applications Q1-1 FDS8858CZ 5,6 D2 3 S2 FR014H5JZ POS NEG iIN 4 G2 CTL R1 DC Power Supply C1 Q1-2 FDS8858CZ 7,8 D1 2 G1 Pulse Generator R2 R3 C2 1 S1 Figure 14. Startup Test Circuit – Normal Bias with FR014H5JZ © 2012 Fairchild Semiconductor Corporation FR014H5JZ • Rev. C1 www.fairchildsemi.com 7 FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression Application Test Configurations FR014H5JZ POS NEG iIN Pulse Generator CTL R2 1 S1 2 G1 DC Power Supply Q1-2 FDS8858CZ 7,8 D1 C1 R3 C2 R3 C2 R1 4 G2 3 S2 5,6 D2 Q1-1 FDS8858CZ Figure 15. Startup Test Circuit – Reverse Bias with FR014H5JZ Q1-1 FDS8858CZ 5,6 D2 3 S2 iIN 4 G2 R1 DC Power Supply Q1-2 7,8 D1 FDS8858CZ C1 2 G1 Pulse Generator R2 1 S1 Figure 16. Startup Test Circuit – without FR014H5JZ © 2012 Fairchild Semiconductor Corporation FR014H5JZ • Rev. C1 www.fairchildsemi.com 8 FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression Application Test Configurations (Continued) Typical USB3.0 conditions. ─ VIN, 2V/div. The input voltage between POS and CTL ─ VOUT, 2V/div. The output voltage between NEG and CTL ─ VD, 1V/div. The startup diode voltage between POS and NEG ─ iIN, 5A/div. The input current flowing from POS to NEG Time: 5µs/div Figure 17. Normal Bias Startup Waveform, DC Power Source=5V, C1=100µF, C2=10µF, R1=R2=10kΩ, R3=27Ω ─ VIN, 2V/div. The input voltage between POS and CTL ─ VD, 2V/div. The startup diode voltage between POS and NEG ─ VOUT, 1V/div. The output voltage between NEG and CTL ─ iIN, 0.1A/div. The input current flowing into POS Time: 100ns/div Figure 18. Reverse Bias Startup Waveform, DC Power Source=5V, C1=100µF, C2=10µF, R1=R2=10kΩ, R3=27Ω © 2012 Fairchild Semiconductor Corporation FR014H5JZ • Rev. C1 www.fairchildsemi.com 9 FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression Typical Application Waveforms Typical USB3.0 conditions. ─ VIN, 2V/div. The voltage applied on the load circuit ─ iIN, 2A/div. The input current Time: 5s/div Figure 19. Startup Waveform without FR014H5JZ, DC Power Source=5V, C1=100µF, C2=10uF, R1=R2=10kΩ, R3=27Ω Application Information Figure 17 shows the voltage and current waveforms when a virtual USB3.0 device is connected to a 5V source. A USB application allows a maximum source output capacitance of C1 = 120µF and a maximum device-side input capacitance of C2 = 10µF plus a maximum load (minimum resistance) of R3 = 27Ω. C1 = 100µF, C2 = 10µF and R3 = 27Ω were used for testing. USB3.0 device is reversely biased; the output voltage is near 0 and response time is less than 50ns. Figure 19 shows the voltage and current waveforms when no reverse bias protection is implemented. In Figure 17, while the reverse bias protector is present, the input voltage, VIN, and the output voltage, VO, are separated and look different. When this reverse bias protector is removed, VIN and VO merge, as shown in Figure 19 as VIN. This VIN is also the voltage applied to the load circuit. It can be seen that, with reverse bias protection, the voltage applied to the load and the current flowing into the load look very much the same as without reverse bias protection. When the DC power source is connected to the circuit (refer to Figure 13), the built-in startup diode initially conducts the current such that the USB device powers up. Due to the initial diode voltage drop, the FR014H5JZ effectively reduces the peak inrush current of a hot plug event. Under these test conditions, the input inrush current reaches about 6A peak. While the current flows, the input voltage increases. The speed of this input voltage increase depends on the time constant formed by the load resistance R3 and load capacitance C2. The larger the time constant, the slower the input voltage increase. As the input voltage approaches a level equal to the protector’s turn-on voltage, VON, the protector turns on and operates in Low-Resistance Mode as defined by VIN and operating current IIN. Benefits of Reverse Bias Protection The most important benefit is to prevent accidently reverse-biased voltage from damaging the USB load. Another benefit is that the peak startup inrush current can be reduced. How fast the input voltage rises, the input/output capacitance, the input voltage, and how heavy the load is determine how much the inrush current can be reduced. In a 5V USB application, for example, the inrush current can be 5% - 20% less with different input voltage rising rate and other factors. This can offer a system designer the option of increasing C2 while keeping “effective” USB device capacitance down. In the event of a negative transient, or when the DC power source is reversely connected to the circuit, the device blocks the flow of current and holds off the voltage, thereby protecting the USB device. Figure 18 shows the voltage and current waveforms when a virtual © 2012 Fairchild Semiconductor Corporation FR014H5JZ • Rev. C1 www.fairchildsemi.com 10 FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression Typical Application Waveforms (Continued) Figure 20. 8-Lead, Molded Leadless Package (MLP), 3.3mm Square Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2012 Fairchild Semiconductor Corporation FR014H5JZ Rev. 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Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I61 © 2012 Fairchild Semiconductor Corporation FR014H5JZ • Rev. C1 www.fairchildsemi.com 12 FR014H5JZ — High Side Reverse Bias / Reverse Polarity Protector With Integrated Over Voltage Transient Suppression TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks.