TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 ® PMIC FOR E Ink Vizplex™ ENABLED ELECTRONIC PAPER DISPLAY Check for Samples: TPS65180, TPS65181 FEATURES 1 • Single Chip Power Management Solution for E Ink® Vizplex™ Electronic Paper Displays • Generates Positive and Negative Gate and Source Driver Voltages and Back-Plane Bias from a Single, Low-Voltage Input Supply • 3-V to 6-V Input Voltage Range • Boost Converter for Positive Rail Base • Inverting Buck-Boost Converter for Negative Rail Base • Two Adjustable LDOs for Source Driver Supply – LDO1: 15 V, 120 mA (VPOS) – LDO2: –15 V, 120 mA (VNEG) • Accurate Output Voltage Tracking – VPOS - VNEG = ±50 mV • Two Charge Pumps for Gate Driver Supply – CP1: 22 V, 10 mA (VDDH) – CP2: –20 V, 12 mA, (VEE) • Adjustable VCOM Driver for Accurate Panel-Backplane Biasing – –0.3 V to –2.5 V – ±1.5% Accuracy (±18 mV) – 8-Bit Control (11-mV Nominal Step Size) – 15-mA Max Integrated Switch • Integrated 3.3-V Power Switch for Disabling System Power Rail • 2345 • • • • Thermistor Monitoring – –10°C to 85°C Temperature Range – ±1°C Accuracy from 0°C to 50°C I2C Serial Interface – Slave Address 0x48h (1001000) Flexible Power-Up Sequencing Interrupt and Sleep Mode Support Thermally Enhanced Package for Efficient Heat Management (48-Pin 7 mm x 7 mm x 0.9 mm QFN) APPLICATIONS • • • • • • Power Supply for Active Matrix E Ink® Vizplex™ Panels EPD Power Supply E-Book Readers EPSON® S1D13522 (ISIS) Timing Controller EPSON® S1D13521 (Broadsheet) Timing Controller Application Processors With Integrated or Software Timing Controller ( OMAP™) DESCRIPTION The TPS65180 and TPS65181 devices are single-chip power supplies designed to for E Ink® Vizplex™ displays used in portable e-reader applications and support panel sizes up to 9.7 inches. Two high efficiency DC/DC boost converters generate ±17-V rails which are boosted to 22 V and –20 V by two change pumps to provide the gate driver supply for the Vizplex™ panel. Two tracking LDOs create the ±15-V source driver supplies which support up to 120-mA of output current. All rails are adjustable through the I2C interface to accommodate specific panel requirements. Accurate back-plane biasing is provided by a linear amplifier and can be adjusted either by an external resistor or the I2C interface. The VCOM driver can source or sink current depending on panel condition. For automatic VCOM adjustment in production line, VCOM can be set from –0.3 V to –2.5 V with 8-bit control through the serial interface. The power switch is integrated to isolate VCOM driver from E Ink® panel. 1 2 3 4 5 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OMAP is a trademark of Texas Instruments. Vizplex is a trademark of E Ink Corporation. E Ink is a registered trademark of E Ink Corporation. EPSON is a registered trademark of Seiko Epson Corporation. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 www.ti.com The TPS65180/TPS65181 provides precise temperature measurement function to monitor the panel temperature during operation. The TPS65180 requires the host processor to trigger the temperature acquisition through an I2C write whereas the TPS65181 automatically updates the temperature every 60 s. This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. FUNCTIONAL BLOCK DIAGRAM 10uF 10uF VIN_P 2.2uH VB_SW From Input Supply (3.0V-6.0V) From Input Supply (3.0V-6.0V) 4.7uH 4.7uF DCDC1 PGND3 DCDC2 VB VN_SW VN 10uF PBKG 4.7uF VDDH_IN 4.7uF POSITIVE CHARGE PUMP VDDH_DRV 1M 10nF 4.7uF VEE_IN VDDH_D Gate driver Supply (22V, 10mA) VDDH_FB NEGATIVE CHARGE PUMP VEE_D Gate driver Supply (-20V, 12mA) VEE_DRV VEE_FB 1M 10nF 47.5k 4.7uF 53.6k PGND2 VPOS_IN VNEG_IN 4.7uF Source Driver Supply (15V, 120mA) 4.7uF VPOS 4.7uF LDO1 LDO2 VNEG Source Driver Supply (-15V, 120mA) 4.7uF 10k NTC TS TEMP SENSOR INT_LDO1 ADC INT_LDO2 INT_LDO1 4.7uF 43k INT_LDO2 4.7uF 10uF VIN From Input Supply (3.0V-6.0V) VREF VREF 4.7uF VCOM 4.7uF DAC MUX AGND1 VCOM_XADJ AGND2 VCOM_PWR DGND 4.7uF VIN3P3 GATE DRIVER To panel back -plane (-0.3 to -2.5V, 15mA) From uC or DSP From system GATE DRIVER VCOM_CTRL V3P3 PWR[3] PWR_GOOD PWR[2] From uC or DSP nINT PWR[1] From uC or DSP From uC or DSP 4.7uF VCOM_PANEL From uC or DSP From uC or DSP VNEG DIGITAL CORE PWR[0] SDA I2C WAKEUP SCL 10k VIO To system 10k VIO To uC or DSP 10k VIO To uC or DSP From uC or DSP From /to uC or DSP ORDERING INFORMATION (1) (1) (2) 2 TA PACKAGE (2) -10°C to 85°C RGZ ORDERABLE PART NUMBER TOP-SIDE MARKING TPS65180RGZR TPS65180 TPS65181RGZR TPS65181 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 DEVICE INFORMATION 25 - VN_SW 27 - VIN_P 26 - N/C 29 - VEE_IN 28 - VN 31 - VEE_D 30 - VEE_DRV 33 - PGND2 32 - VEE_FB 34 - VDDH_FB 36 - VDDH_DRV 35 - VDDH_D RGZ PACKAGE (TOP VIEW) 24 - PWR_GOOD 23 - PBKG VDDH_IN - 37 N/C - 38 22 - PWR0 N/C - 39 VB_SW - 40 21 - PWR1 20 - PWR2 PGND3 - 41 VB - 42 VPOS_IN - 43 19 - PWR3 18 - SDA 17 - SCL 16 - VCOM_PWR 15 - VCOM VPOS - 44 VIN3P3 - 45 V3P3 - 46 TS - 47 14 - VCOM_PANEL 13 - N/C VCOM_CTRL - 12 AGND1 - 8 INT_LDO1 -9 VIN – 10 VCOM_XADJ - 11 DGND - 6 INT_LDO2 - 7 VNEG - 3 VNEG_IN - 4 WAKEUP - 5 VREF - 1 nINT - 2 AGND2 - 48 TERMINAL FUNCTIONS (3) TERMINAL (3) I/O DESCRIPTION NAME NO. VREF 1 O Filter pin for 2.25-V internal reference to ADC nINT 2 O Open drain interrupt pin (active low) VNEG 3 O Negative supply output pin for panel source drivers VNEG_IN 4 I Input pin for LDO2 (VNEG) WAKEUP 5 I Wake up pin (active high). Pull this pin high to wake up from sleep mode. DGND 6 INT_LDO2 7 Digital ground O Internal supply (digital circuitry) filter pin AGND1 8 INT_LDO1 9 O Analog ground for general analog circuitry Internal supply (analog circuitry) filter pin VIN 10 I Input power supply to general circuitry VCOM_XADJ 11 I Analog input for conventional VCOM setup method. Tie this pin to ground if VCOM is set through I2C interface. VCOM_CTRL 12 I VCOM_PANEL gate driver enable (active high) N/C 13 Not connected There will be 0-ns, 93.75-µs, 62.52-µs of deglitch for PWRx, WAKEUP, and VCOM_CTRL, respectively. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 3 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 TERMINAL www.ti.com I/O DESCRIPTION NAME NO. VCOM_PANEL 14 O Panel common-voltage output pin VCOM 15 O Filter pin for panel common-voltage driver VCOM_PWR 16 I Internal supply input pin to VCOM buffer. Connect to the output of DCDC2. SCL 17 I Serial interface (I2C) clock input SDA 18 I/O PWR3 19 I Enable pin for CP1 (VDDH) (active high) PWR2 20 I Enable pin for LDO1 (VPOS) (active high) PWR1 21 I Enable pin for CP2 (VEE) (active high) PWR0 22 I Enable pin for LDO2 (VNEG) and VCOM (active high) PWR_GOOD 24 O Open drain power good output pin (active low) VN_SW 25 O Inverting buck-boost converter switch out (DCDC2) N/C 26 VIN_P 27 I Input power supply to inverting buck-boost converter (DCDC2) VN 28 I Feedback pin for inverting buck-boost converter (DCDC2) Serial interface (I2C) data input/output Not connected VEE_IN 29 I Input supply pin for CP1 (VEE) VEE_DRV 30 O Driver output pin for negative charge pump (CP2) VEE_D 31 O Base voltage output pin for negative charge pump (CP2) VEE_FB 32 I Feedback pin for negative charge pump (CP2) PGND2 33 VDDH_FB 34 I Feedback pin for positive charge pump (CP1) Power ground for CP1 (VDDH) and CP2 (VEE) charge pumps VDDH_D 35 O Base voltage output pin for positive charge pump (CP1) VDDH_DRV 36 O Driver output pin for positive charge pump (CP1) VDDH_IN 37 I Input supply pin for positive charge pump (CP1) N/C 38 N/C 39 VB_SW 40 PGND3 41 Not connected Not connected O Boost converter switch out (DCDC1) Power ground for DCDC1 VB 42 I Feedback pin for boost converter (DCDC1) VPOS_IN 43 I Input pin for LDO1 (VPOS) VPOS 44 O Positive supply output pin for panel source drivers VIN3P3 45 I Input pin to 3.3-V power switch V3P3 46 O Output pin of 3.3-V power switch TS 47 I Thermistor input pin. Connect a 10k NTC thermistor and a 43k linearization resistor between this pin and AGND2. AGND2 48 Reference point to external thermistor and linearization resistor PowerPad (PBKG) 23 Die substrate/thermal pad. Connect to VN with short, wide trace. Wide copper trace will improve heat dissipation. PowerPad must not be connected to ground. 4 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) Input voltage range at VIN, VINP, VIN3P3 VALUE UNIT –0.3 to 7 V Ground pins to system ground –0.3 to 0.3 V Voltage range at SDA, SCL, WAKEUP, PWR3, PWR2, PWR1, PWR0, VCOM_CTRL, VDDH_FB, VEE_FB, PWR_GOOD, nINT –0.3 to 3.6 V VCOM_XADJ –3.6 to 0.3 V Voltage on VB, VB_SW, VPOS_IN, VDDH_IN –0.3 to 20 V Voltage on VN, VNEG_IN, VEE_IN, VCOM_PWR –20 to 0.3 V Voltage from VINP to VN_SW Peak output current –0.3 to 30 V Internally limited mA Continuous total power dissipation 2 W qJA Junction-to-ambient thermal resistance (3) 23 °C/W TJ Operating junction temperature -10 to 125 °C TA Operating ambient temperature (4) -10 to 85 °C Tstg Storage temperature -65 to 150 °C ESD rating (1) (2) (3) (4) (HBM) Human body model ±2000 (CDM) Charged device model ±500 V Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltage values are with respect to network ground terminal. Estimated when mounted on high K JEDEC board per JESD 51-7 with thickness of 1.6 mm, 4 layers, size of 76.2 mm X 114.3 mm, and 2 oz. copper for top and bottom plane. Actual thermal impedance will depend on PCB used in the application. It is recommended that copper plane in proper size on board be in contact with die thermal pad to dissipate heat efficiently. Thermal pad is electrically connected to PBKG, which is supposed to be tied to the output of buck-boost converter. Thus wide copper trace in the buck-boost output will help heat dissipated efficiently. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX Input voltage range at VIN, VINP, VIN3P3 3 3.7 6 UNIT V Voltage range at SDA, SCL, WAKEUP, PWR3, PWR2, PWR1, PWR0, VCOM_CTRL, VDDH_FB, VEE_FB, VCOM_XADJ, PWR_GOOD, nINT 0 3.6 V TA Operating ambient temperature range –10 85 °C TJ Operating junction temperature range –10 125 °C RECOMMENDED EXTERNAL COMPONENTS PART NUMBER VALUE SIZE MANUFACTURER LQH44PN4R7MP0 4.7 µH 4 mm x 4 mm x 1.65 mm Murata VLS252012T-2R2M1R3 2.2 µH 2 mm x 2.5 mm x 1.2 mm TDK GRM21BC81E475KA12L 4.7 µF, 25 V, X6S 805 Murata GRM32ER71H475KA88L 4.7 µF, 50 V, X7R 1210 Murata INDUCTORS CAPACITORS All other caps X5R or better DIODES BAS3010 SOD-323 Infineon MBR130T1 SOD-123 ON-Semi 603 Murata THERMISTOR NCP18XH103F03RB 10 kW Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 5 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 www.ti.com ELECTRICAL CHARACTERISTICS VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 3 3.7 6 UNIT INPUT VOLTAGE VIN Input voltage range VUVLO Undervoltage lockout threshold VIN falling 2.9 V V VHYS Undervoltage lockout hysteresis VIN rising 400 mV INPUT CURRENT IQ Operating quiescent current into VIN Device switching, no load 5.5 mA ISTD Operating quiescent current into VIN Device in standby mode 130 µA ISLEEP Shutdown current Device in sleep mode 2.8 10 µA INTERNAL SUPPLIES VINT_LDO1 Internal supply 2.7 V VINT_LDO2 Internal supply 2.7 V VREF Internal supply 2.25 V DCDC1 (POSITIVE BOOST REGULATOR) VIN Input voltage range 3 Output voltage range VOUT Output current RDS(ON) MOSFET on resistance -5 VIN = 3.7 V Switch current limit ILIMIT Switch current accuracy fSW Switching frequency L Inductor C Capacitor ESR Capacitor ESR 6 17 DC set tolerance IOUT 3.7 V V 5 % 160 mA 350 mΩ 1.5 A -30 30 1 % MHz 2.2 µH 2x4.7 µF 20 mΩ DCDC2 (INVERTING BUCK-BOOST REGULATOR) VIN Input voltage range 3 Output voltage range VOUT DC set tolerance IOUT Output current RDS(ON) MOSFET on resistance -5 VIN = 3.7 V Inductor C Capacitor ESR Capacitor ESR V 5 % 160 mA V mΩ 1.5 Switch current accuracy L 6 350 Switch current limit ILIMIT 3.7 -17 -30 A 30 4.7 % µH 2x4.7 µF 20 mΩ LDO1 (VPOS) VPOS_IN Input voltage range VIN = 17 V, VPOS_SET[2:0] = 0x0h to 0x7h 16.15 17 17.85 V 14.25 15 15.75 V VSET Output voltage set value VINTERVAL Output voltage set resolution VPOS_OUT Output voltage range VSET = 15 V, ILOAD = 20 mA 14.85 VOUTTOL Output tolerance VSET = 15 V, ILOAD = 20 mA -1 VDROPOUT Dropout voltage VLOADREG Load regulation – DC ILOAD Load current range 6 VIN = 17 V 250 15 ILOAD = 120 mA ILOAD = 10% to 90% V 1 % 250 mV 1 120 Submit Documentation Feedback mV 15.15 % mA Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 ELECTRICAL CHARACTERISTICS (continued) VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted) PARAMETER TEST CONDITIONS ILIMIT Output current limit TSS Soft start time C Recommended output capacitor MIN TYP MAX 200 UNIT mA 1 ms 4.7 µF LDO2 (VNEG) VNEG_IN Input voltage range VIN = –17 V, VNEG_SET[2:0] = 0x0h to 0x7h -17.85 -17 -16.15 V -15.75 -15 -14.25 V VSET Output voltage set value VINTERVAL Output voltage set resolution VNEG_OUT Output voltage range VSET = –15 V, ILOAD = –20 mA -15.15 VOUTTOL Output tolerance VSET = –15 V, ILOAD = –20 mA -1 VDROPOUT Dropout voltage ILOAD = 120 mA VLOADREG Load regulation – DC ILOAD Load current range ILIMIT Output current limit TSS Soft start time C Recommended output capacitor VIN = –17 V 250 -15 ILOAD = 10% to 90% mV -14.85 V 1 % 250 mV 1 120 % mA 200 mA 1 ms 4.7 µF LD01 (POS) AND LDO2 (VNEG) TRACKING VDIFF Difference between VPOS and VNEG VSET = ±15 V, ILOAD = ±20 mA, 0°C to 60°C -50 50 VCOM_SET[7:0] = 0x74h (–1.25 V) VIN = 3.4 V to 4.2 V, no load -0.8 0.8 VCOM_SET[7:0] = 0x74h (–1.25 V) VIN = 3.0 V to 6.0 V, no load -1.5 1.5 mV VCOM DRIVER Accuracy VCOM Output voltage range -2.5 Resolution G % VCOM gain (VCOM_XADJ/VCOM) -0.3 VCOM_ADJ = 1 V, 1 LSB 11 VCOM_ADJ = 0 V 1 17 V mV V/V VCOM SWITCH TON Switch ON time RDS(ON) MOSFET ON resistance ILIMIT ISWLEAK VCOM = –1.25 V, VCOM_PANEL = 0 V CVCOM = 4.7 µF, CVCOM_PANEL = 4.7 µF VCOM = –1.245 V, ICOM = 30 mA 20 MOSFET current limit Not tested in production 200 Switch leakage current VCOM = 0 V, VCOM_PANEL = –2.5 V 1 ms 35 Ω mA 8.3 nA VIN3P3 TO V3P3 SWITCH RDS(ON) MOSFET ON resistance VIN3P3 = 3.3 V, ID = 2 mA Ω 50 CP1 (VDDH) CHARGE PUMP VDDH_IN VFB Input voltage range 16.15 Feedback voltage 17 17.85 V 3 % 23 V 1 Accuracy -3 VSET = 22 V, ILOAD = 2 mA 21 22 V VDDH_OUT Output voltage range ILOAD Load current range fSW Switching frequency CD Recommended driver capacitor 10 nF CO Recommended output capacitor 4.7 µF 10 560 mA KHz CP2 (VEE) NEGATIVE CHARGE PUMP VEE_IN Input voltage range -17.75 -17 -16.15 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 V 7 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VIN = 3.7 V, TA = –10°C to 85ºC, Typical values are at TA = 25ºC (unless otherwise noted) PARAMETER TEST CONDITIONS MIN Feedback voltage VFB TYP MAX UNIT -1 Accuracy -3 VSET = –20 V, ILOAD = 3 mA -21 V 3 -20 % VEE_OUT Output voltage range ILOAD Load current range -19 V 12 mA fSW Switching frequency CD Recommended driver capacitor 10 nF CO Recommended output capacitor 4.7 µF 560 KHz THERMISTOR MONITOR (1) ATMS Temperature to voltage ratio OffsetTMS Offset VTMS_HOT Not tested in production -0.0158 V/°C Temperature = 0°C 1.575 V Temp hot trip voltage (T = 50°C) TEMP_HOT_SET = 0x8C 0.768 V VTMS_COOL Temp hot escape voltage (T = 45°C) TEMP_COOL_SET = 0x82 0.845 V VTMS_MAX Maximum input level 2.25 V RNTC_PU Internal pull up resistor 7.307 KΩ RLINEAR External linearization resistor ADCRES ADC resolution ADCDEL ADC conversion time Not tested in production TMSTTOL Accuracy Not tested in production Not tested in production, 1 bit 43 KΩ 8.75 mV 19 -2 µs 2 LSB LOGIC LEVELS AND TIMING CHARTERISTICS (SCL, SDA, nINT, PWR_GOOD, PWRx, WAKEUP) IO = 3 mA, sink current (SDA, nINT, PWR_GOOD) VOL Output low threshold level VIL Input low threshold level VIH Input high threshold level I(bias) Input bias current VIO = 1.8 V tlow,WAKEUP WAKEUP low time minimum low time for WAKEUP pin fSCL SCL clock frequency 0.4 V 0.4 V 1.2 V 1 150 µA ms 400 KHz OSCILLATOR fOSC Oscillator frequency Frequency accuracy 9 TA = –40°C to 85°C -10 MHz 10 % THERMAL SHUTDOWN TSHTDWN Thermal trip point Thermal hysteresis (1) 8 150 °C 20 °C 10-kΩ Murata NCP18XH103F03RB thermistor (1%) in parallel with a linearization resistor (43kΩ, 1%) are used at TS pin for panel temperature measurement. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 MODES OF OPERATION The TPS65180/TPS65181 has three modes of operation, SLEEP, STANDBY, and ACTIVE. SLEEP mode is the lowest-power mode in which all internal circuitry is turned off. In STANDBY, all power rails are shut down but the device is ready to accept commands through PWR[3:0] pins and/or I2C interface. In ACTIVE mode one or more power rails are enabled. SLEEP This is the lowest power mode of operation. All internal circuitry is turned off, registers are reset to default values and the device does not respond to I2C communications. TPS65180/TPS65181 enters SLEEP mode whenever WAKEUP pin is pulled low. STANDBY In STANDBY all internal support circuitry is powered up and the device is ready to accept commands either through GPIO or I2C control but none of the power rails are enabled. To enter STANDBY mode the WAKEUP pin must be pulled high and all PWRx pins must be pulled low or the STANDBY bit of the ENABLE register must be set high. The device also enters STANDBY mode if input under voltage lock out (UVLO), positive boost under voltage (VB_UV), or inverting buck-boost under voltage (VN_UV) is detected, or thermal shutdown occurs. ACTIVE The device is in ACTIVE mode when any of the output rails are enabled and no fault condition is present. This is the normal mode of operation while the device is powered up. In ACTIVE mode, a falling edge on any PWRx pin shuts down and a rising edge powers up the corresponding rail. MODE TRANSISITONS SLEEP → ACTIVE WAKEUP pin is pulled high (rising edge) with any PWRx pin high. Rails come up in the order defined by the PWR_SEQx registers. SLEEP → STANDBY WAKEUP pin is pulled high (rising edge) with all PWRx pins low. Rails will remain down until one or more PWRx pin is pulled high. ACTIVE → SLEEP WAKEUP pin is pulled low (falling edge). Rails are shut down in the reverse power-up order defined by PWR_SEQ registers. ACTIVE → STANDBY WAKEUP pin is high. All PWRx pins are pulled low (falling edge). Rails shut down in the order in which PWRx pins are pulled low. In the event of thermal shut down (TSD), under voltage lock out (UVLO), positive boost or inverting buck-boost under voltage (UV), or when STANDBY bit is set to 1, the device shuts down all rails in the reverse power-up order defined by the PWR_SEQx registers. STANDBY → ACTIVE WAKEUP pin is high and any PWRx pin is pulled high (rising edge). Rails come up in the same order as PWRx pins are pulled high. Alternatively, if ACTIVE bit is set to 1, output rails will power up in the order defined by the PWR_SEQx registers. STANDBY → SLEEP WAKEUP pin is pulled low (falling edge) while none of the output rails are enabled. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 9 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 www.ti.com POWER DOWN Battery removed All rails = OFF I2C = NO Registers à default WAKEUP ( ) & any PWRx pin = high(*) ? WAKEUP ( ) & All PWRx pins= low WAKEUP (?) All rails I2C STANDBY = OFF = YES ? WAKEUP = high & (STANDBY bit = 1(*) || all PWRx pins= (?) (**) || (**) FAULT ) WAKEUP = high & (ACTIVE bit= 1(*) || any PWRx pin( ) (**)) ? WAKEUP (?) (*) SLEEP ACTIVE Rails I2C = ON = YES NOTES: ||, & = logic OR, logic AND. (?), ( ) = rising edge, falling edge. FAULT = UVLO || TSD (thermal shutdown)|| BOOST UV. (*) = Power sequencing is register controlled . (**) = Power sequencing is GPIO controlled . ? Figure 1. Global State Diagram WAKE-UP AND POWER UP SEQUENCING The TPS65180/TPS65181 supports flexible power-up sequencing through GPIO control using the PWR3, 2, 1, 0 pins or I2C control using the PWR_SEQ0, 1, 2 registers. Using GPIO control, the output rails are enabled/disabled in the order in which the PWRx pins are asserted/de-asserted, respectively, and the power-up timing is controlled by the host only. In I2C control mode the power-up/down order and timing are defined by user register settings. The default settings support the E Ink® Vizplex™ panel and typically do not need to be charged by the user. 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 GPIO CONTROL Under GPIO control the system host in E Ink® Vizplex™ panel module enables the TPS65180/TPS65181 output rails by asserting the PWR0, PWR1, PWR2, PWR3 signals and the host has full control over the order and timing in which the output rails are powered up and down. Rails are in regulation 2 ms after their respective PWRx pin has been asserted with the exception of the first rail, which takes 6 ms to power up. The additional time is needed to power up the positive and inverting buck-boost regulator which need to be turned on before any other rail can be enabled. Once all rails are enabled and in regulation the PWR_GOOD pin is released (pin status = HiZ and power good line is pulled high by external pull-up resistor). The PWRx pins are assigned to the rails as follows: • PWR0: LDO2 (VNEG) and VCOM • PWR1: CP2 (VEE) • PWR3: LDO2 (VPOS) • PWR4: CP1 (VDDH) Rails are powered down whenever the host de-asserts the respective PWRx pin, and once all rails are disabled the device enters STANDBY mode. The next step is then to de-assert the WAKEUP pin to enter SLEEP mode which is the lowest-power mode of operation. It is possible for the host to force the TPS65180/TPS65181 directly into SLEEP mode from ACTIVE mode by de-asserting the WAKEUP pin in which case the device follows the power-down sequence defined by the PWR_SEQx registers before entering SLEEP mode. I2C CONTROL Under I2C control the power-up sequence is defined by the PWR_SEQx registers rather than through GPIO control. In SLEEP mode the TPS65180/TPS65181 is completely turned off, the I2C registers are reset, and the device does not accept any I2C transaction. Pull the WAKEUP pin high while all PWRx pins are held low and the device will enter STANDBY mode which enables the I2C interface. Write to the PWR_SEQ0 register to define the order in which the output rails will be enabled at power-up and to the PWR_SEQ1 and PWR_SEQ2 registers to define the power-up delays between rails. Finally, set the ACTIVE bit in the ENABLE register to 1 to execute the power-up sequence and bring up all power rails. It is possible for the host to force the TPS65180/TPS65181 directly into ACTIVE mode from SLEEP mode by pulling the WAKEUP pin high while at least one of the PWRx pins is pulled high. In this case the default power-up sequence defined by the PWR_SEQx registers applies and the device will start powering up the rails 5.5 ms after the WAKEUP signal has been pulled high. To power-down the device, set the STANDBY bit of the ENABLE register to 1 and the TPS65180/TPS65181 will follow the reverse power-up sequence to bring down all power rails. While the sequencer is busy powering up the power rails, any activity on the PWRx pins is ignored. Once all rails are up, any of the output rails can be disabled by applying a negative edge on the PWRx input pins, i.e. if the host toggles the PWRx pin high-low or low-high-low, the respective rail will be disabled regardless of how it has been enabled. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 11 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 www.ti.com WAKEUP DLY0 + 5.5ms DLY1 STROBE 1 SEQ = 00 DLY2 STROBE 2 SEQ = 01 DLY3 STROBE 3 SEQ = 10 STROBE 4 SEQ = 11 WAKEUP DLY0 DLY3 STROBE 4 SEQ = 11 DLY2 STROBE 3 SEQ = 10 DLY1 STROBE 2 SEQ = 01 STROBE 1 SEQ = 00 TOP: Power-up sequence is defined by assigning strobes to individual rails. STROBE1 is the first strobe to occur after WAKEUP has been pulled high and STROBE4 is the last event in the sequence. STROBES are assigned to rails in PWR_SEQ0 register and delays between states are defined in PWR_SEQ1 and PWR_SEQ2 registers. BOTTOM: Power-down sequence follows reverse power-up sequence. Figure 2. I2C Control DEPENDENCIES BETWEEN RAILS Charge pumps, LDOs, and VCOM driver are dependent on the positive and inverting buck-boost converters and several dependencies exist that affect the power-up sequencing. These dependencies are listed below. 1. Inverting buck-boost (DCDC2) must be in regulation before positive boost (DCDC1) can be enabled. Internally, DCDC1 enable is gated by DCDC2 power good. 2. Positive boost (DCDC1) must be in regulation before LDO2 (VNEG) can be enabled. Internally LDO2 enable is gated DCDC1 power-good. 3. Positive boost (DCDC1) must be in regulation before VCOM can be enabled; Internally VCOM enable is gated by DCDC1 power good. 4. Positive boost (DCDC1) must be in regulation before negative charge pump (CP2) can be enabled. Internally CP2 enable is gated by DCDC1 power good. 5. Positive boost (DCDC1) must be in regulation before positive charge pump (CP1) can be enabled. Internally CP1 enable is gated by DCDC1 power good. 6. LDO2 must be in regulation before LDO1 can be enabled. Internally LDO1 enable is gated by LDO2 power good. 7. The minimum delay time between any two PWRx pins must be > 62.5 µs in order to follow the power up sequence defined by GPIO control. If any two PWRx pins are pulled up together (< 62.5 µs apart) or the sequencer tries to bring up the rails at the same time by assigning the same STROBE to rails in PWR_SEQ0 register, rails will be staggered in a manner that a subsequent rail’s enable is gated by PG of a preceding rail. In this case, the default order of power-up is LDO2 (VNEG), CP2 (VEE), LDO1 (VPOS), and CP1(VDDH). If any two PWRx pins are pulled low together or the sequencer tries to bring down the rails at the same time by assigning the same STROBE to rails in PWR_SEQ0 register, then all rails will go down at the same time. 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 VIN PWR0 PWR1 D0 1.8ms (1) D1 PWR2 D2 PWR3 D3 WAKEUP SLEEP STANDBY ACTIVE ACTIVE VN VB VNEG DLY 1 VCOM 6ms (2,5) DLY 0 + 4ms (2) DLY 2 VEE 1ms (5) DLY 1 DLY 3 VPOS 2ms (5) DLY 2 DLY 0 VDDH 1ms (5) DLY 3 PWR_GOOD 300 us (max) 11 .8ms (min) (1) Minimum delay time between WAKEUP rising edge and IC rady to accept I 2C transaction . (2) It takes 2ms minimum for each internal boost regulator to start up before VNEG can be enabled . (5) It takes up to 2ms for LDOs (VPOS,VNEG) and 1ms for charge pumps (VDDH,VEE), to reach their steady state after being enabled. DLY 0-DLY 3 are power up /down delays defined in register PWR _SEQ 1 and PWR _SEQ2. In this example the first power-up sequence is determined by GPIO control (WAKEUP is pulled high while PWRx pins are low). Power-down and 2nd power-up sequence is controlled by register settings (WAKEUP pin is toggled with at least one PWR pin held high). Figure 3. Power-Up and Power-Down Timing Diagram SOFTSTART Softstart for DCDC1, DCDC2, LDO1, and LDO2 is accomplished by lowering the current limits during start-up. If DCDC1 or DCDC2 are unable to reach power-good status within 10 ms, the corresponding UV flag is set in the interrupt registers, the interrupt pin is pulled low, and the device enters STANDBY mode. LDO1, LDO2, positive and negative charge pumps have a 5ms power-good time-out limit. If either rail is unable to power up within 5 ms after it has been enabled, the corresponding UV flag is set and the interrupt pin is pulled low. However, the device will remain in ACTIVE mode in this case. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 13 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 www.ti.com VCOM ADJUSTMENT Through the I2C interface the user can select between two methods of VCOM voltage adjustment: 1. Using the internal 8-bit DAC and register control. 2. Using an external voltage source (resistor divider) connected to the VCOM_XADJ pin. VCOM ADJUSTMENT THROUGH REGISTER CONTROL By default the TPS65180 is setup for internal VCOM control through the I2C interface. The default setting for the 8-bit DAC is 0x74h which results in 1.25 V ±0.8% for VCOM. VCOM can be adjusted up or down in steps of 11 mV (typ) by writing to the VCOM_ADJUST register. The output range for VCOM is limited to –0.3 V to –2.5 V. 10uF VIN From Input Supply (3.0V-6.0V) 4.7uF VREF (2.25V) VREF VCOM_SET[7:0] VCOM_ADJ 4.7uF -0.3...-2.5V VCOM -0.3...-2.5V -0.3...-2.5V MUX -0.3...-2.5V DAC -17V VCOM_XADJ VCOM_PWR VNEG 4.7uF GATE DRIVER 4.7uF To Eiink ® VIXPLEX TM VCOM_CTRL From DCDC 2 (-17V) From uC or DSP VCOM_PANEL Panel Figure 4. Block Diagram of VCOM Circuit VCOM ADJUSTMENT THROUGH EXTERNAL POTENTIOMETER VCOM can be adjusted by an external potentiometer by setting the VCOM_ADJ bit of the VN_ADJUST register to 0 and connecting a potentiometer to the VCOM_XADJ pin. The potentiometer must be connected between ground and a negative supply as shown in Figure 4. The gain from VCOM_XADJ to VCOM is 1 and therefore the voltage applied to VCOM_XADJ pin should range from –0.3 V to –2.5 V. VPOS / VNEG SUPPLY TRACKING LDO1 (VPOS) and LDO2 (VNEG) track each other in a way that they are of opposite sign but same magnitude. The sum of VLDO1 and VLOD2 is guaranteed to be < 50 mV. To ensure proper tracking of the supplies the VPOS_SET[2:0] bits of the VP_ADUST register must remain at the default setting of 010b. To adjust the VPOS/VNEG output voltage, write to the VN_ADJUST register only and keep the VPOS_SET[2:0] bits of the VP_ADUST register unchanged. FAULT HANDLING AND RECOVERY The TPS65180/1 monitors input and output voltages and die temperature and will take action if operating conditions are outside normal limits. Whenever the TPS65180/1 encounters: • Thermal Shutdown (TSD) • Positive Boost Under Voltage (VB_UV) • Inverting Buck-Boost Under Voltage (VN_UV) • Input Under Voltage Lock Out (UVLO) it will shut down all power rails and enter STANDBY mode. Shut down follows the reverse power-up sequence defined by the PWR_SEQx registers. Once a fault is detected, the PWR_GOOD and nINT pin are pulled low and the corresponding interrupt bit is set in the interrupt register. Whenver the TPS65180/1 encounters under voltage on VNEG (VNEG_UV), VPOS (VPOS_UV), VEE (VEE_UV) or VDDH (VDDH_UV) it will shut down the corresponding rail (plus any dependent rail) only and remain in ACTIVE mode, allowing the DCDC converters to remain up. Again, the PWR_GOOD and nINT pins will be pulled low and the corresponding interrupt bit will be set. 14 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 TPS65180 FAULT HANDLING Once a fault is detected the TPS65180 sets the appropriate interrupt flags in the INT_STATUS1 and INT_STATUS2 registers and pulls INT pin low to signal an interrupt to the host processor. None of the power rails can be re-enabled before the host has read the INT_STATUSx bits and the fault has been removed. As the PWRx inputs are edge sensitive, the host must also toggle the PWRx pins to re-enable the rails through GPIO control, i.e. it must bring the PWRx pins low before asserting them again. TPS65181 FAULT HANDLING The TPS65181 does not require the host processor to access the INT_STATUS registers before re-enabling the output rails. Rails can be re-enabled as soon as the fault condition has been removed. Again, as the PWRx inputs are edge sensitive, the host must also toggle the PWRx pins to re-enable the rails through GPIO control, i.e. it must bring the PWRx pins low before asserting them again. POWER GOOD PIN The power good pin (PWR_GOOD) is an open drain output that is pulled high when all four power rails (CP1, CP2, LDO1, LDO2) are in regulation and is pulled low if any of the rails encounters a fault. PWR_GOOD remains low if one of the rails is not enabled by the host and only after all rails are in regulation PWR_GOOD is released to HiZ state (pulled up by external resistor). INTERRUPT PIN The interrupt pin (nINT) is an open drain output that is pulled low whenever one or more of the INT_STATUS1 or INT_STATUS2 bits are set. The nINT pin is released (returns to HiZ state) and fault bits are cleared once the register with the set bit has been read by the host. If the fault persists, the INT_pin will be pulled low again after a maximum of 32 µs. Interrupt events can be masked by re-setting the corresponding enable bit in the INT_ENABLE1 and INT_ENABLE2 register, i.e. the user can determine which events cause the nINT pin to be pulled low. The status of the enable bits affects the nINT pin only and has no effect on any of the protection and monitoring circuits or the INT_STATUSx bits themselves. Note that persisting fault conditions such as thermal shutdown can cause the nINT pin to be pulled low for an extended period of time which can keep the host in a loop trying to resolve the interrupt. If this behavior is not desired, set the corresponding mask bit after receiving the interrupt and keep polling the INT_STATUSx register to see when the fault condition has disappeared. After the fault is resolved, unmask the interrupt bit again. PANEL TEMPERATURE MONITORING The TPS65180 and TPS65181 provide circuitry to bias and measure an external negative temperature coefficient resistor (NTC) to monitor device temperature in a range from –10°C to 85°C with and accuracy of ±1°C from 0°C to 50°C. The TPS65180 requires the host to trigger the temperature acquisition through an I2C command whereas the TPS65181 triggers the temperature acquisition automatically once every 60 s. NTC BIAS CIRCUIT Figure 5 below shows the block diagram of the NTC bias and measurement circuit. The NTC is biased from an internally generated 2.25-V reference voltage through an integrated 7.307-kΩ bias resistor. A 43-kΩ resistor is connected parallel to the NTC to linearize the temperature response curve. The circuit is designed to work with a nominal 10-kΩ NTC and achieves accuracy of ±1°C from 0°C to 50°C. The voltage drop across the NTC is digitized by a 10-bit SAR ADC and translated into an 8-bit two’s complement by digital per Table 1. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 15 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 www.ti.com Table 1. ADC Output Value vs Termperature TEMPERATURE TMST_VALUE[7:0] < -10°C 1111 0110 -10°C 1111 0110 -9°C 1111 0111 ... ... -2°C 1111 1110 -1°C 1111 1111 0°C 0000 0000 1°C 0000 0001 2°C 0000 0010 ... ... 25°C 0001 1001 ... 85°C 0101 0101 > 85°C 0101 0101 2.25V 7.307 kW 10 Digital 10 bit ADC 43 kW 10 kW NTC TPS6518x Figure 5. NTC Bias and Measurement Circuit TPS65180 TEMPERATURE ACQUISITION The TPS65180 requires the host to trigger the temperature acquisition before reading the temperature value from register TMST_VALUE. A standard temperature measurement involves the following steps: 1. The host sets the READ_THERM bit of the TMST_CONFIG register to 1. This enabled the NTC bias circuit and internal ADC. 2. The analog to digital conversion is automatically started after a fixed 250-µs delay. While the conversion is in progress the CONV_END bit of the TMST_CONFIG register is held low and returns to 1 after the conversion result is available. 3. After the conversion is complete the READ_THERM bit is automatically reset, the EOC bit of the INT_STATUS2 register is set, and the interrupt pin (nINT) is pulled low. 4. The host services the interrupt by reading the INT_STATUS2 register. This clears the interrupt pin (nINT pin returns high). The host sees the EOC bit set and knows that the temperature data is available in the TMST_VALUE register. 5. The host reads the temperature data from the TMST_VALUE register. TPS65181 TEMPERATURE ACQUISITION The TPS65181 triggers temperature acquisition once every 60s to reduce the number of required I2C writes. The host or display timing controller can read the temperature at any time by accessing the TMST_VALUE register 16 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 without having to set the READ_THERM bit first. However, the host can always trigger an additional temperature reading the same way as for the TPS65180. Please note that at the end of each temperature acquisition the EOC interrupt will be set and an interrupt will be issued. Although the interrupt is automatically cleared, the nINT pin will be pulled low for a short amount of time (6 µs). To avoid seeing the EOS interrupt every 60s it is recommended to mask the EOC interrupt by setting the EOC_EN bit of the INT_ENABLE2 register to 0. OVER TEMPERATURE REPORTING The user has the option of setting HOT and COOL (not HOT) temperature thresholds as well as controlling interrupt behavior as the NTC exceeds HOT and cools down below COOL (not-HOT) threshold. By default, TPS65180/1 compares the temperature conversion result to the HOT threshold after each conversion. If the NTC temperature is above the HOT threshold, the TMST_HOT bit in the INT_STATUS1 register is set to 1 and the interrupt pin (nINT) is pulled low. HOT temperature threshold is set by the host by writing to the TMST_OS register and the HOT interrupt can be disabled by setting the HOT_EN bit of the INT_ENABLE1 register to 0. Once the device has detected that the NTC is above the HOT threshold it will compare subsequent temperature acquisitions against the COOL threshold and pull the interrupt pin low when the NTC temperature drops below the COOL threshold. However, the interrupt will be issued only if the host has unmasked the COOL interrupt by setting TMST_COOL_EN bit of INT_ENABLE1 register to 1. The COOL threshold is set by the host by writing to the TMST_HYST register. To use the full functionality of the HOT/COOL interrupts the following actions are required: 1. The host sets the HOT and COOL (not HOT) thresholds by writing the TMST_OS and TMST_HYST registers. 2. (2) For TPS65180 only: The host sets the READ_THERM bit of the TMST_CONFIG register to ‘1’. This initiates the temperature acquisition. 3. TPS65180/1 compares the result against the TMST_OS threshold and will pull the nINT pin low if the NTC temperature exceeds the HOT threshold. 4. If the TPS65180/1 reports a HOT condition, the host unmasks the TMST_COOL_EN bit by setting it to 1 (INT_ENABLE1 register). 5. The host initiates a new temperature conversion by setting the READ_THERM bit of the TMST_CONFIG register to 1. If the new temperature is still above the HOT threshold, a new HOT interrupt will be issued. If the temperature is below HOT but above COOL threshold, no interrupt is issued (except for EOC which is issued at the end of each conversion). If the temperature is below COOL threshold, a COOL interrupt is issued. 6. After the temperature drops below the COOL threshold the host should set the TMST_COOL_EN bit in the INT_ENABLE1 register to 0 to mask additional COOL interrupts after subsequent temperature acquisitions. OVER-TEMPERATURE FAULT QUEUING The user can specify the number of consecutive HOT temperature reads required to issue a HOT interrupt. The user can set the FAULT_QUE[1:0] bits of the TMST_CONFIG register to specify 1, 2, 4, or 6 consecutive reads that all must be above the HOT threshold before a HOT interrupt is issued. The fault queue is reset each time the acquired temperature drops below the HOT threshold and can also be reset by the host by setting the FAULT_QUE_CLR bit 1. Only if the specified number of readings have been detected which all need to be above the HOT threshold, a HOT interrupt is issued. This function is useful to reduce noise in the temperature measurements. TPS65181 TEMPERATURE SENSOR The TPS65181 automates the temperature monitoring process and is specifically designed to operate in multi-host systems where one of the I2C hosts, e.g. the display controller, has limited I2C capability. Standard I2C protocol requires the following steps to read data from a register: 1. Send device and register address, R/nW bit set low (write command). 2. Send device address, R/nW set high (read command). 3. The slave will respond with data from the specified register address. Some display controllers support I2C read commands only and need to access the temperature data from the Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 17 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 www.ti.com TPS65181 TMST_VALUE register. To support these systems the TPS65181 automatically triggers temperature acquisition every 60s (for other acquisition intervals contact the factory) and stores the result in TMST_VALUE register. With the FIX_RD_PTR bit in the FIX_RD_POINTER register set to 1 the device will respond to any I2C read command with data from the TMST_VALUE register. No write command with the register address is required and address auto increment feature is disabled in this mode. Therefore reading the temperature data is reduced to two steps: 1. Send device address, R/nW set high (read command). 2. Read the data from the slave. The slave will respond with data from TMST_VALUE register address. Write functionality is not affected by the FIX_RD_PTR bit and the main controller in the system maintains full control of the PMIC. Interrupts and error flags are issued and need to be handled the same way as for the TPS65180 with two exceptions: 1. The FIX_RD_PTR bit in the FIX_RD_POINTER register needs to be set to 0 before the main controller can read any register different from the TMST_VALUE register. 2. Thermal shutdown (TSD), positive boost under voltage (VB_UV), inverting buck-boost under voltage (VN_UV), and input under voltage lock out (UVLO) interrupt bits do not have to be cleared before output rails can be re-enabled. At system power-up the main processor sets up the PMIC by accessing the I2C registers and setting the control parameters as needed. When the system is setup correctly the main controller sets the FIX_READ_POINTER bit and the display controller can start accessing the temperature information. During normal operation the main controller can write to the PMIC at any time but before it can read access registers the FIX_READ_POINTER bit must be written 0. The temperature range and representation of the temperature data is the same between the TPS65180 and TPS65181. THE FIX_RD_PTR BIT The TPS65181 supports a special I2C mode making it compatible with the EPSON Broadsheet S1D13521 timing controller. Standard I2C protocol requires the following steps to read data from a register: 1. Send device slave address, R/nW bit set low (write command) 2. Send register address 3. Send device slave address, R/nW set high (read command) 4. The slave will respond with data from the specified register address. The EPSON Broadsheet S1D13521 controller does not support I2C writes nor I2C reads from addressed registers (step 1. and 2. above) but needs to access the temperature data from the TPS65181’s TMST_VALUE register. To support Broadsheet based systems, the TPS65181 automatically triggers temperature acquisition every 60s and stores the result in TMST_VALUE register. With the FIX_RD_PTR bit in the FIX_RD_POINTER register set to 1 the device will respond to any I2C read command with data from the TMST_VALUE register. No write command with the register address is required and address auto increment feature is disabled in this mode. Therefore reading the temperature data is reduced to two steps: 1. Send device address, R/nW set high (read command) 2. Read the data from the slave. The slave will respond with data from TMST_VALUE register address. Write functionality is not affected by the FIX_RD_PTR bit and the main controller in the system maintains full control of the PMIC. Interrupts and error flags are issued and need to be handled the same way as for the TPS65180 with two exceptions: 1. The FIX_RD_PTR bit in the FIX_RD_POINTER register needs to be set to 0 before the main controller can read any register different from the TMST_VALUE register. 2. Thermal Shutdown (TSD), positive boost Under Voltage (VB_UV), inverting buck-boost Under Voltage (VN_UV), and input Under Voltage Lock Out (UVLO) interrupt bits do not have to be cleared before output rails can be re-enabled. 18 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 At system power-up the main processor sets up the PMIC by accessing the I2C registers and setting the control parameters as needed. When the system is setup correctly the main controller sets the FIX_READ_POINTER bit and the display controller can start accessing the temperature information. During normal operation the main controller can write to the PMIC at any time but before it can read access registers the FIX_READ_POINTER bit must be written 0. I2C BUS OPERATION The TPS65180/1 hosts a slave I2C interface that supports data rates up to 400 kbit/s and auto-increment addressing and is compliant to I2C standard 3.0. Slave Address + R/nW Sub Address S A6 A5 A4 A3 A2 A1 A0 S Start Condition A Acknowledge A6 ... A0 Device Address Read / not Write P Stop Condition S7 ... S0 Sub-Address R/nW R/nW A S7 S6 S5 S4 S3 S2 S1 S0 Data A D7 D6 D5 D4 D3 D2 D1 D0 A P D7 ... D0 Data Figure 6. Subaddress in I2C Transmission Start – Start condition ACK – Acknowledge G(3:0) – Group ID: Address fixed at 1001. S(7:0) – Subaddress: defined per register map. A(2:0) – Device Address: Address fixed at 000. D(7:0) – Data; Data to be loaded into the device. R/nW – Read / not Write Select Bit Stop – Stop condition The I2C Bus is a communications link between a controller and a series of slave terminals. The link is established using a two-wired bus consisting of a serial clock signal (SCL) and a serial data signal (SDA). The serial clock is sourced from the controller in all cases where the serial data line is bi-directional for data communication between the controller and the slave terminals. Each device has an open Drain output to transmit data on the serial data line. An external pull-up resistor must be placed on the serial data line to pull the drain output high during data transmission. Data transmission is initiated with a start bit from the controller as shown in Figure 8. The start condition is recognized when the SDA line transitions from high to low during the high portion of the SCL signal. Upon reception of a start bit, the device will receive serial data on the SDA input and check for valid address and control information. If the appropriate group and address bits are set for the device, then the device will issue an acknowledge pulse and prepare the receive subaddress data. Subaddress data is decoded and responded to as per the Register Map section of this document. Data transmission is completed by either the reception of a stop condition or the reception of the data word sent to the device. A stop condition is recognized as a low to high transition of the SDA input during the high portion of the SCL signal. All other transitions of the SDA line must occur during the low portion of the SCL signal. An acknowledge is issued after the reception of valid address, sub-address and data words. The I2C interface will auto-sequence through register addresses, so that multiple data words can be sent for a given I2C transmission. Reference Figure 8. Please note that auto-increment is not supported when the FIX_RD_PTR bit is set (TPS65181 only). Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 19 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 S SLAVE ADDRESS W A www.ti.com SUB ADDRESS A S SLAVE ADDRESS R A DATA SUBADDR +n A DATA SUBADDR A DATA SUBADDR +n+1 Ā P n bytes + ACK S SLAVE ADDRESS R A DATA 0 A DATA 0 A DATA 0 Ā P n bytes + ACK From master to slave R Read S Start Ā Not Acknowlege From slave to master W Write (not read) P Stop A Acknowlege Figure 7. TOP: Standard I2C READ data transmission with address auto-increment. Bottom: I2C READ data transmission with FIX_RD_PTR bit set for EPSON Broadsheet support. Only address 0x00h can be read. FIX_RD_PTR bit has no impact on WRITE transaction. SDA SCL 1-7 8 9 ADDRESS R/W ACK 1-7 8 9 1-7 8 9 S START P DATA ACK DATA ACK/ nACK STOP Figure 8. I2C Start/Stop/Acknowledge Protocol SDA tf tLOW tr tSU;DAT tHD;STA tSP tr tBUF SCL tHD;STA S tHD;DAT tHIGH tSU;STA tSU;STO Sr tf P S Figure 9. I2C Data Transmission Timing 20 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 DATA TRANSMISSION TIMING VBAT = 3.6 V ±5%, TA = 25ºC, CL = 100 pF (unless otherwise noted) PARAMETER TEST CONDITIONS f(SCL) Serial clock frequency tHD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated. TYP 100 tLOW LOW period of the SCL clock tHIGH HIGH period of the SCL clock tSU;STA Set-up time for a repeated START condition tHD;DAT MIN Data hold time tSU;DAT Data set-up time tr Rise time of both SDA and SCL signals tf Fall time of both SDA and SCL signals tSU;STO Set-up time for STOP condition tBUF Bus Free Time Between Stop and Start Condition tSP Pulse width of spikes which mst be suppressed by the input filter Cb Capacitive load for each bus line MAX 400 UNIT KHz SCL = 100 KHz 4 µs SCL = 400 KHz 600 ns SCL = 100 KHz 4.7 SCL = 400 KHz 1.3 µs SCL = 100 KHz 4 µs SCL = 400 KHz 600 ns SCL = 100 KHz 4.7 µs SCL = 400 KHz 600 SCL = 100 KHz 0 3.45 µs SCL = 400 KHz 0 900 ns SCL = 100 KHz 250 SCL = 400 KHz 100 ns ns SCL = 100 KHz 1000 SCL = 400 KHz 300 SCL = 100 KHz 300 SCL = 400 KHz 300 ns ns SCL = 100 KHz 4 µs SCL = 400 KHz 600 ns SCL = 100 KHz 4.7 SCL = 400 KHz 1.3 SCL = 100 KHz n/a n/a SCL = 400 KHz 0 50 µs SCL = 100 KHz 400 SCL = 400 KHz 400 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 ns pF 21 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 www.ti.com REGISTER ADDRESS MAP 22 DEFAULT VALUE REGISTER ADDRESS (HEX) NAME 0 0x00 TMST_VALUE N/A Thermistor value read by ADC 1 0x01 ENABLE 0001 1111 Enable/disable bits for regulators 2 0x02 VP_ADJUST 0010 0011 Voltage settings for VPOS, VDDH 3 0x03 VN_ADJUST 1010 0011 Voltage settings for VNEG, VEE 4 0x04 VCOM_ADJUST 0111 0100 Voltage settings for VCOM 5 0x05 INT_ENABLE1 0111 0100 Interrupt enable group1 6 0x06 INT_ENABLE2 1111 1011 Interrupt enable group2 7 0x07 INT_STATUS1 0xxx xx00 Interrupt status group1 8 0x08 INT_STATUS2 xxxx x0xx Interrupt status group2 9 0x09 PWR_SEQ0 1110 0100 Power up sequence 10 0x0A PWR_SEQ1 0010 0010 DLY0, DLY1 time set 11 0x0B PWR_SEQ2 0010 0010 DLY2, DLY3 time set 12 0x0C TMST_CONFIG 0010 0000 Thermistor configuration 13 0x0D TMST_OS 0011 0010 Thermistor hot temp set 14 0x0E TMST_HYST 0010 1101 Thermistor cool temp set 15 0x0F PG_STATUS 0000 0000 Power good status each rails 16 0x10 REVID 0100 0001 Device revision ID information 17 0x11 FIX_READ_POINTER 0000 0000 I2C read pointer control Submit Documentation Feedback DESCRIPTION Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 THERMISTOR READOUT (TMST_VALUE) Address – 0x00h DATA BIT D7 D6 D5 D4 READ/WRITE R R R R R R R R RESET VALUE N/A N/A N/A N/A N/A N/A N/A N/A FIELD NAME D3 D2 D1 D0 TMST_VALUE[7:0] FIELD NAME BIT DEFINITION Temperature read-out 1111 0110 – < -10°C 1111 0110 – -10°C 1111 0111 – -9°C ... 1111 1110 – -2°C 1111 1111 – -1 °C TMST_VALUE[7:0] 0000 0000 – 0 °C 0000 0001 – 1°C 0000 0010 – 2°C ... 0001 1001 – 25°C ... 0101 0101 – 85°C 0101 0101 – > 85°C ENABLE (ENABLE) Address – 0x01h DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 VCOM_EN VDDH_EN VPOS_EN VEE_EN VNEG_EN FIELD NAME ACTIVE STANDBY V3P3_SW _EN READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 0 0 0 1 1 1 1 1 BIT DEFINITION (1) FIELD NAME STANDBY to ACTIVE transition bit ACTIVE 1 – Transition from STANDBY to ACTIVE mode. Rails power up as defined by PWR_SEQx registers. 0 – No effect NOTE: After transition bit is cleared automatically. ACTIVE to STANDBY transition bit STANDBY 1 – Transition from ACTIVE to STANDBY mode. Rails power down as defined by PWR_SEQx registers. 0 – No effect NOTE: After transition bit is cleared automatically. STANDBY bit has priority over AVTIVE. VIN3P3 to V3P3 switch enable V3P3_SW_EN 1 – Switch is ON 0 – Switch id OFF VCOM buffer enable VCOM_EN 1 – Enabled 0 – Disabled (1) Enable/disable bits for regulators are AND’d with PWRx signals. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 23 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 www.ti.com BIT DEFINITION (1) FIELD NAME VDDH charge pump enable VDDH_EN 1 – Enabled 0 – Disabled VPOS LDO regulator enable VPOS_EN 1 – Enabled 0 – Disabled NOTE: VPOS cannot be enabled before VNEG is enabled. VEE charge pump enable VEE_EN 1 – Enabled 0 – Disabled VNEG LDO regulator enable VNEG_EN 1 – Enabled 0 – Disabled NOTE: When VNEG is disabled VPOS will also be disabled. 24 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 POSITIVE VOLTAGE RAIL ADJUSTMENT (VP_ADJUST) Address – 0x02h DATA BIT D7 D6 D5 D4 VDDH_SET[2:0] D3 D2 D0 FIELD NAME Not used READ/WRITE R R/W R/W R/W R R/W R/W R/W RESET VALUE 0 0 1 0 0 0 1 1 VPOS_SET[2:0] BIT DEFINITION (1) FIELD NAME Not used not used D1 N/A VDDH voltage setting 000 – VDDH increase by 10% 001 – VDDH increase by 5% 010 – Nominal VDDH_SET[2:0] 011 – VDDH decrease by 5% 100 – VDDH decrease by 10% 101 – Reserved 110 – Reserved 111 – Reserved Not used N/A VPOS voltage setting 000 : |VNEG| - 0.75 V 001 : |VNEG| - 0.5 V 010 : |VNEG| - 0.25 V 011 : |VNEG| VPOS_SET[2:0] 100 : |VNEG| + 0.25 V 101 : |VNEG| + 0.5 V 110 : |VNEG| + 0.75 V 111 – Reserved NOTE: For proper tracking of the VPOS and VNEG supply these bits must remain set at their default value of 011b. VPOS will track VNEG automatically when VNEG_SET[2:0] bits of VN_ADJUST register are changed. (1) VDDH will be decreased from set value defined by resistor divider. Decreased VDDH value should be within spec range. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 25 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 www.ti.com NEGATIVE VOLTAGE RAIL ADJUSTMENT (VN_ADJUST) Address – 0x03h (1) DATA BIT D7 D6 D5 D4 VEE_SET[2:0] D3 D2 Not used D1 D0 FIELD NAME VCOM_ADJ READ/WRITE R/W R/W R/W R/W R R/W VNEG_SET[2:0] R/W R/W RESET VALUE 1 (1) 0 1 0 0 0 1 1 TPS65180: Bit defaults to 1; TPS65181: Bit defaults to 0 FIELD NAME BIT DEFINITION VCOM output adjustment method VCOM_ADJ 0 – VCOM_XADJ pin 1 – I2C interface VDDH voltage setting 000 – VEE decrease by 10% 001 – VEE decrease by 5% 010 – Nominal VEE_SET[2:0] (1) 011 – VEE increase by 5% 100 – VEE increase by 10% 101 – Reserved 110 – Reserved 111 – Reserved not used N/A VNEG voltage setting 000 – -15.75 V 001 – -15.50 V 010 – -15.25 V VNEG_SET[2:0] 011 – -15.00 V 100 – -14.75 V 101 – -14.50 V 110 – -14.25 V 111 – Reserved (1) 26 VEE will be decreased from set value defined by resistor divider. Decreased VEE value should be within spec range. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 VCOM ADJUSTMENT (VCOM_ADJUST) Address – 0x04h DATA BIT D7 D6 D5 D4 READ/WRITE R/W R/W R/W R/W RESET VALUE 0 1 1 1 FIELD NAME D3 D2 D1 D0 R/W R/W R/W R/W 0 1 0 0 VCOM_SET[7:0] FIELD NAME BIT DEFINITION VCOM voltage adjustment 0000 0000 – 0 V 0000 0001 – 11 mV 0000 0010 – 22 mV ... 0111 0011 – 1239 mV VCOM_SET[7:0] 0111 0100 – 1250 mV 0111 0101 – 1261 mV ... 1111 1111 – 2750 mV NOTE: step size is rounded to 11 mV. Theoretical step size is 2750 mV / 255 mV = 10.78 mV. Parametric performance is guranteed from -0.3 V to -2.5 V only. INTERRUPT ENABLE 1 (INT_ENABLE1) Address – 0x05h DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 TMST_COOL _EN UVLO_EN Not used Not used FIELD NAME Not used TSD_EN HOT_EN TMST_HOT _EN READ/WRITE R R/W R/W R/W R/W R/W R R RESET VALUE 0 1 1 1 0 1 0 0 FIELD NAME Not used BIT DEFINITION N/A Thermal shutdown interrupt enable TSD_EN 1 – Enabled 0 – Disabled Thermal shutdown early warning enable HOT_EN 1 – Enabled 0 – Disabled Thermistor hot warning enable TMST_HOT_EN 1 – Enabled 0 – Disabled Thermistor hot escape interrupt enable TMST_COOL_EN 1 – Enabled 0 – Disabled VIN under voltage detect interrupt enable UVLO_EN 1 – Enabled 0 – Disabled Not used N/A Not used N/A Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 27 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 www.ti.com INTERRUPT ENABLE 2 (INT_ENABLE2) Address – 0x06h DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 FIELD NAME VB_UV_EN VDDH_UV _EN VN_UV_EN VPOS_UV _EN VEE_UV _EN not used VNEG_UV _EN EOC_EN READ/WRITE R/W R/W R/W R/W R/W R R/W R/W RESET VALUE 1 1 1 1 1 0 1 1 FIELD NAME BIT DEFINITION Positive boost converter under voltage detect interrupt enable VB_UV_EN 1 – Enabled 0 – Disabled VDDH under voltage detect interrupt enable VDDH_UV_EN 1 – Enabled 0 – Disabled Inverting buck-boost converter under voltage detect interrupt enable VN_UV_EN 1 – Enabled 0 – Disabled VPOS under voltage detect interrupt enable VPOS_UV_EN 1 – Enabled 0 – Disabled VEE under voltage detect interrupt enable VEE_UV_EN 1 – Enabled 0 – Disabled not used N/A VNEG under voltage detect interrupt enable VNEG_UV_EN 1 – Enabled 0 – Disabled ADC end of conversion interrupt enable EOC_EN 1 – Enabled 0 – Disabled INTERRUPT INT_STATUS1 (INT_STATUS1) Address – 0x07h DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 FIELD NAME Not used TSDN HOT TMST_HOT TMST_COOL UVLO Not used Not used READ/WRITE R R R R R R R R RESET VALUE 0 N/A N/A N/A N/A N/A 0 0 FIELD NAME Not used TSD Thermal shutdown interrupt HOT Thermal shutdown early warning TMST_HOT TMST_COOL UVLO 28 BIT DEFINITION N/A Thermistor hot warning Thermistor hot escape interrupt VIN under voltage detect interrupt Not used N/A Not used N/A Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 INTERRUPT STATUS 2 (INT_STATUS2) Address – 0x08h DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 EOC FIELD NAME VB_UV VDDH_UV VN_UV VPOS_UV VEE_UV Not used VNEG_UV READ/WRITE R R R R R R R R RESET VALUE N/A N/A N/A N/A N/A 0 N/A N/A BIT DEFINITION (1) FIELD NAME VB_UV VDDH_UV VN_UV VPOS_UV VDDH under voltage detect interrupt Inverting buck-boost converter under voltage detect interrupt VPOS under voltage detect interrupt VEE_UV VEE under Voltage detect interrupt not used N/A VNEG_UV EOC (1) Positive boost converter under voltage detect interrupt VNEG under voltage detect interrupt ADC end of conversion interrupt Under voltage detect bit is set if the corresponding rail does not come up 5 ms after it is enabled except for DCDC1 and 2 which are set 10 ms after they are enabled. POWER SEQUENCE REGISTER 0 (PWR_SEQ0) Address – 0x09h DATA BIT D7 D6 D5 D4 D3 D2 VEE_SEQ[1:0] D1 D0 FIELD NAME VDDH_SEQ[1:0] VPOS_SEQ[1:0] VNEG_SEQ[1:0] READ/WRITE R/W R/W R/W R/W R/W R/W R/W R/W RESET VALUE 1 1 1 0 0 1 0 0 BIT DEFINITION (1) FIELD NAME VDDH power-up/down order 00 – Power-up/down on STROBE1 VDDH_SEQ[1:0] 01 – Power-up/down on STROBE2 10 – Power-up/down on STROBE3 11 – Power-up/down on STROBE4 VPOS power-up/down order 00 – Power-up/down on STROBE1 VPOS_SEQ[1:0] 01 – Power-up/down on STROBE2 10 – Power-up/down on STROBE3 11 – Ppower-up/down on STROBE4 VEE power-up/down order 00 – Power-up/down on STROBE1 VEE_SEQ[1:0] 01 – Power-up/down on STROBE2 10 – Power-up/down on STROBE3 11 – Power-up/down on STROBE4 VNEG power-up/down order 00 – Power-up/down on STROBE1 VNEG_SEQ[1:0] 01 – Power-up/down on STROBE2 10 – Power-up/down on STROBE3 11 – Power-up/down on STROBE4 (1) Power-down sequence follows the reverse order of power-up. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 29 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 www.ti.com POWER SEQUENCE REGISTER 1 (PWR_SEQ1) Address – 0x0Ah DATA BIT D7 D6 D5 D4 D3 D2 READ/WRITE R/W R/W R/W R/W R/W RESET VALUE 0 0 1 0 0 FIELD NAME D1 D0 R/W R/W R/W 0 1 0 DLY1[3:0] FIELD NAME DLY0[3:0] BIT DEFINITION DLY1 delay time set; defines the delay time from STROBE1 to STROBE2 during power-up and from STROBE2 to STROBE1 during power-down. 0000 – 0 ms 0001 – 1 ms DLY1[3:0] 0010 – 2 ms 0011 – 3 ms ... 1110 – 14 ms 1111 – 15 ms DLY0 delay time set; defines the delay time from WAKEUP high to STROBE1 during power-up and from WAKEUP low to STROBE4 during power-down. 0000 – 0 ms 0001 – 1 ms DLY0[3:0] 0010 – 2 ms 0011 – 3 ms ... 1110 – 14 ms 1111 – 15 ms 30 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 POWER SEQUENCE REGISTER 2 (PWR_SEQ2) Address – 0x0Bh DATA BIT D7 D6 D5 D4 D3 D2 READ/WRITE R/W R/W R/W R/W R/W RESET VALUE 0 0 1 0 0 FIELD NAME D1 D0 R/W R/W R/W 0 1 0 DLY3[3:0] FIELD NAME DLY2[3:0] BIT DEFINITION DLY3 delay time set; defines the delay time from STROBE3 to STROBE4 during power-up and from STROBE4 to STROBE3 during power-down. 0000 – 0 ms 0001 – 1 ms DLY3[3:0] 0010 – 2 ms 0011 – 3 ms ... 1110 – 14 ms 1111 – 15 ms DLY2 delay time set; defines the delay time from STROBE2 to STROBE3 during power-up and from STROBE3 to STROBE2 during power-down. 0000 – 0 ms 0001 – 1 ms DLY2[3:0] 0010 – 2 ms 0011 – 3 ms ... 1110 – 14 ms 1111 – 15 ms Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 31 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 www.ti.com THERMISTOR CONFIGURATION REGISTER (TMST_CONFIG) Address – 0x0Ch DATA BIT D7 D6 D5 FIELD NAME READ_ THERM Not used CONV_END READ/WRITE R/W R R R/W RESET VALUE 0 0 1 0 FIELD NAME D4 D3 D2 D1 D0 FAULT_QUE _CLR Not used Not used R/W R/W R R 0 0 0 0 FAULT_QUE [1:0] BIT DEFINITION Read thermistor value READ_THERM 1 – Initiates temperature acquisition 0 – No effect NOTE: bit is self-cleared after acquisition is completed Not used N/A ADC conversion done flag CONV_END 1 – Conversion is finished 0 – Conversion is not finished Number of faults to detect before TMST_HOT interrupt is asserted 00 – 1 time FAULT_QUE [1:0] 01 – 2 times 10 – 4 times 11 – 6 times Fault counter clear FAULT_QUE_CLR 1 – Clears fault counter 0 – Fault counter is cleared automatically if thermistor reading is less than TMST_HOT_SET[7:0] 32 Not used N/A Not used N/A Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 THERMISTOR HOT THRESHOLD (TMST_OS) Address – 0x0Dh DATA BIT D7 D6 D5 READ/WRITE R/W R/W R/W R/W RESET VALUE 0 0 1 1 FIELD NAME D4 D3 D2 D1 D0 R/W R/W R/W R/W 0 0 1 0 TMST_HOT_SET[7:0] FIELD NAME BIT DEFINITION Defined the thermistor HOT threshold 1000 0000 – Reserved ... 1111 0101 – Reserved 1111 0110 – -10°C 1111 0111 – -9°C ... 1111 1110 – -2°C 1111 1111 – -1°C 0000 0000 – 0°C TMST_HOT_SET[7:0] 0000 0001 – 1°C 0000 0010 – 2°C ... 0001 1001 – 25°C ... 0011 0010 – 50°C ... 0101 0101 – 85°C 0101 0110 – Reserved ... 0111 1111 – Reserved Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 33 TPS65180, TPS65181 SLVSA76D – MARCH 2010 – REVISED JULY 2010 www.ti.com THERMISTOR COOL THRESHOLD (TMST_HYST) Address – 0x0Eh DATA BIT D7 D6 D5 D4 READ/WRITE R/W R/W R/W R/W RESET VALUE 0 0 1 0 FIELD NAME D3 D2 D1 D0 R/W R/W R/W R/W 1 1 0 1 TMST_COOL_SET[7:0] FIELD NAME BIT DEFINITION Defined the thermistor HOT threshold 1000 0000 – Reserved ... 1111 0101 – Reserved 1111 0110 – -10°C 1111 0111 – -9°C ... 1111 1110 – -2°C 1111 1111 – -1°C 0000 0000 – 0°C TMST_HOT_SET[7:0] 0000 0001 – 1°C 0000 0010 – 2°C ... 0001 1001 – 25°C ... 0010 1101 – 45°C ... 0101 0101 – 85°C 0101 0110 – Reserved ... 0111 1111 – Reserved POWER GOOD STATUS (PG_STATUS) Address – 0x0Fh DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 FIELD NAME VB_PG VDDH_PG VN_PG VPOS_PG VEE_PG Not used VNEG_PG Not used READ/WRITE R R R R R R R R RESET VALUE 0 0 0 0 0 0 0 0 FIELD NAME VB_PG VDDH_PG VN_PG VPOS_PG VDDH power good Inverting buck-boost power good VPOS power good VEE_PG VEE power good not used N/A VNEG_PG not used 34 BIT DEFINITION Positive boost converter power good VNEG power good N/A Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 TPS65180, TPS65181 www.ti.com SLVSA76D – MARCH 2010 – REVISED JULY 2010 REVISION AND VERSION CONTROL (REVID) Address – 0x10h DATA BIT D7 FIELD NAME D6 D5 MJREV[1:0] D4 D3 D2 MNREV[1:0] D1 D0 VERSION[3:0] READ/WRITE R R R R R R R R RESET VALUE 0 1 0 0 N/A N/A N/A N/A FIELD NAME BIT DEFINITION Major revision 00 – Not used MJREV[1:0] 01 – 1px release 10 – 2px release 11 – 3px release Minor revision 00 – xp0 release MNREV[1:0] 01 – xp1 release 1 10 – xp2 release 2 11 – xp3 release 3 Version ID VERSION[4:0] 0000 – TPS65180 0001 – TPS65181 I2C READ POINTER CONTROL (FIX_READ_POINTER) Address – 0x11h DATA BIT D7 D6 D5 D4 D3 D2 D1 D0 FIELD NAME Not used Not used Not used Not used Not used Not used Not used FIX_RD_PTR READ/WRITE R R R R R R R R/W RESET VALUE 0 0 0 0 0 0 0 0 FIELD NAME BIT DEFINITION Not used N/A Not used N/A Not used N/A Not used N/A Not used N/A Not used N/A Not used N/A I2C read pointer control FIX_RD_PTR 1 – Read pointer is fixed to 0x00 0 – read pointer is controlled through I2C Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TPS65180 TPS65181 35 PACKAGE OPTION ADDENDUM www.ti.com 17-Jul-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TPS65180RGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples TPS65180RGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Contact TI Distributor or Sales Office TPS65181RGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Request Free Samples TPS65181RGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Contact TI Distributor or Sales Office (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS65180RGZR VQFN RGZ 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 TPS65180RGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 TPS65181RGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 TPS65181RGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65180RGZR VQFN RGZ 48 2500 346.0 346.0 33.0 TPS65180RGZT VQFN RGZ 48 250 190.5 212.7 31.8 TPS65181RGZR VQFN RGZ 48 2500 346.0 346.0 33.0 TPS65181RGZT VQFN RGZ 48 250 190.5 212.7 31.8 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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