Ordering number : ENA0015 Monolithic Linear IC LA72700V US MTS (Multi Channel Television Sound) Decoder Overview LA72700V is a US MTS (Multi Channel Television Sound) decoder. Features • With SIF circuit, STEREO channel separation is alignment-free. • Built-in filters are adjustment free. • SAP output level is selectable 2 levels. • Included control function for STEREO and SAP detection sensitivity. Functions • SIF FM-Demodulator. • STEREO decoder. • ALC function is included. • dbx Noise Reduction system. • SAP demodulator. • STEREO detection. • SAP detection. Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Maximum power supply voltage VCC max Allowable power dissipation Pd max Conditions Ta≤70°C * Ratings Unit 9.6 V 810 mW Operating temperature Topr -10 to +70 °C Storage temperature Tstg -55 to +150 °C * ON board (114.3 × 76.1 × 1.6 mm Glass Epoxy resin board) Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. N2206 / O2505 MS OT B8-8873 No.A0015-1/16 LA72700V Operating Conditions at Ta = 25°C Parameter Recommended operating Symbol Conditions Ratings VCC Unit 9.0 V 8.5 to 9.5 V voltage Operating voltage range VCC op Electrical Characteristics at Ta = 25°C, VCC = 9.0V Parameter Symbol Ratings Conditions min Current dissipation ICC No signal Inflow current at pin 31 typ Unit max 50 60 70 mA (80) (90) (100) dBµV -6.0 -5.0 dBV 0.15 0.6 % -2 0 2 dB 55 65 -7.0 -6.0 -5.0 dBV 1.0 2.5 % -3 0 3 dB 50 60 dB 20 25 dB 20 25 dB 52 57 62 % 62 67 72 % * Default condition SIF input level VILIM (Reference) fc = 4.5MHz Deviation MONO (300Hz, Mod = 100%, Pre-emphasis ON) Æ ±25kHz Base band input level VILIMB (Reference) MONO output level 100% Modulation MONO(L+R): 530mVp-p (300Hz, Pre-emphasis ON) VOMON SUB(L-R): 380mVp-p (300Hz, dbx-NR ON), Pilot: 110mVp-p SAP: 300mVp-p (300Hz, dbx-NR ON) Input: fm = 1kHz, 100% Mod, MONORAL -7.0 Measure OUT (L), OUT (R) MONO distortion THDMON Input: fm = 1kHz, 100% Mod, MONORAL Measure OUT (L), OUT (R) MONO frequency characteristics FCM1 Input: fm = 8kHz, 30% Mod, MONORAL Measure OUT(L), OUT(R), Ratio from fm = 1kHz level. MONO S/N ratio SNM S = VOMON, N = 0% Mod dB Measure OUT (L), OUT (R) With 15kHz LPF, JIS-A STEREO output level VOST Input: fm = 1kHz, 100% Mod, STEREO Measure OUT (L), OUT(R) STEREO distortion THDS Input: fm = 1kHz, 100% Mod, STEREO Measure OUT (L), OUT (R) STEREO frequency FCS1 characteristics fm = 8kHz, 30% Mod, STEREO Measure OUT (L), OUT (R), Ratio from fm = 1kHz level. STEREO S/N ratio SNS S = VOST, N = 0% Mod Measure OUT (L), OUT (R) With 15kHz LPF, JIS-A STEREO separation 1 STSE1 f = 300Hz (R/L), 30% Mod Measure ratio OUT (L) with OUT (R) STEREO separation 2 STSE2 f = 3kHz (R/L), 30% Mod Measure ratio OUT (L) with OUT (R) STEREO Detection level-1 VINSD1 Except Stereo Detection Æ Stereo Detection Measure PILOT level, at STERO det. STEREO Detection level-2 VINSD2 Except Stereo Detection Æ Stereo Detection * Insert Resistor pin 14 to GND (ex. 51kΩ) Measure PILOT level, at STERO det. Continued on next page. No.A0015-2/16 LA72700V Continued from preceding page. Parameter Symbol Ratings Conditions min STEREO detection hysteresis HYST Input Mod. Difference at Stereo /Except Stereo Det. typ Unit max 10 15 25 % -7.5 -6.5 -5.5 dBV -5.5 -4.5 -3.5 dBV 1.5 3.5 % * at default condition SAP output level-1 VOSA Fm = 1kHz, 100% Mod, SAP Measure OUT (L), OUT * at bit6 = 0 SAP output level-2 VOSA2 Fm = 1kHz, 100% Mod, SAP Measure OUT (L), OUT * at bit6 = 1 SAP distortion THDSA Fm = 1kHz, 100% Mod, SAP Measure OUT (L), OUT SAP S/N ratio SNSA S = VOSA, N = 0% Mod, 55 65 dB 13 18 23 % (5) (10) (15) % (20) (25) (30) % 2 5 10 % 0.7 1 1.3 V 1.7 2 2.3 V 2.7 3 3.3 V 3.5 3.8 4.2 V 0.3 0.5 % Measure OUT (L), OUT (R) With 15kHz LPF, JIS-A SAP detection level-1 VINSA1 Measure SAP carrier level, when SAP det * Default condition SAP detection level-2 VINSA2 (Reference) Measure SAP carrier level, when SAP det * pin15 to GND (ex 33kΩ) SAP detection level-3 VINSA3 (Reference) Measure SAP carrier level, when SAP det * pin15 to GND (ex 8.2kΩ) SAP detection hysteresis HYSA Input Mod. Difference at SAP/Except SAP Det. * at default condition MODE output MONO MODMO Input = MONO: f = 1kHz, 0% Mod Measure pin32 MODE output SAP MODSA Input = SAP: Carrier Measure pin32 MODE output STEREO MODST Input = STEREO: Pilot Measure pin32 MODE output ST + SAP MODSS Input = STEREO: Pilot, SAP: Carrier Measure pin32 Distortion THDALC MONO 1kHz Mod 100% * ALC on Measure OUT (L), OUT (R) * Normally measurement condition is Input = SIF mode (-90dBµV), ALC = OFF * " Reference " Items are reference levels, their specs are no-guarantee. Package Dimensions unit : mm 3247B No.A0015-3/16 LA72700V Block Diagram and Application Circuit Example No.A0015-4/16 LA72700V 00p-1 ( Normally use : group-1 only ) D8 D7 D6 D5 D4 D3 D2 * * * D1 Condition 0 0 0 1 SAP 1 0 Both 1 1 Normal (Auto det) 1 Forced Mono Normal (MUTE off) 1 MUTE 0 ALC off (Through) 1 * * * Prohibit 0 0 * Stereo ALC on 0 SAP LEVEL-1 1 SAP LEVEL-2 0 SIF mode 1 Base Band mode 0 Fix 1 Prohibit (TEST MODE) *: Initial condition Read out data D8 D7 D6 0 D5 0 D4 0 D3 0 D2 D1 0 0 Condition Fixed 0 Normal 1 SAP det 0 Normal 1 Stereo det Test mode condition When STOP condition transform at Grp-1 data-end, controlled NORMAL mode. Grp-2(Only test condition: Normally, this data is no-need) D8 D7 D6 D5 D4 D3 D2 D1 Condition/Monitor position 0 0 0 0 0 0 0 0 Normal (Usually, Fixed) 0 0 0 0 0 0 0 1 TEST-1 SIF output 0 0 0 0 0 0 1 0 TEST-2 SAP BPF 0 0 0 0 0 0 1 1 TEST-3 SAP VCO 0 0 0 0 0 1 0 0 TEST-4 ST VCO 0 0 0 0 0 1 0 1 TEST-5 ADJ VCO 0 0 0 0 0 1 1 0 TEST-6 dbx input 0 0 0 0 0 1 1 1 TEST-7 L-R Demod output 0 0 0 0 1 0 0 0 TEST-8 Pilot cancel 0 0 0 0 1 0 0 1 TEST-9 dbx 2.19k LPF 0 0 0 0 1 0 1 0 TEST-10 dbx 408 LPF 0 0 0 0 1 0 1 1 TEST-11 dbx DET 10k LPF 0 0 0 0 1 1 0 0 TEST-12 dbx SPEC 7.6k LPF 0 0 0 0 1 1 0 1 TEST-13 dbx SPEC output 0 0 0 0 1 1 1 0 TEST-14 (No operation) 0 0 0 0 1 1 1 1 TEST-15 (No operation) No.A0015-5/16 LA72700V Pin Functions DC voltage No. Pin function Input/output form Reference AC level 1 PC_DC_IN DC: 3.8V AC coupling (Input) AC: 2.4Vp-p 2 PC_DCOUT DC: 3.8V AC coupling (Output) AC: 2.4Vp-p 3 PCSTFILT DC: 3.8V Stereo VCO PLL filter 4 PCPLDET DC: 3.8V Pilot level detect 5 PISIF DC: 3.7V Signal input Continued on next page. No.A0015-6/16 LA72700V Continued from preceding page. No. Pin function DC voltage Input/output form Reference AC level 6 GND CSAPDET DC: 2.8V SAP carrier level detect 8 NC No connect 9 PC FIL DC: 2.9V SIF offset cancel 10 MUTE DC: 0V MUTE = 5V 11 SDA Serial data input 12 SCL Serial clock input Continued on next page. No.A0015-7/16 LA72700V Continued from preceding page. No. Pin function DC voltage Input/output form Reference AC level 13 PC DBXIN DC: 2.5V Offset cancel filter 14 PSTSENS DC: 3.1V Stereo det sensitivity change OPEN = default Insert resistor(30k or over) = Low sensitivity 15 PSAPSENS DC: 3.1V SAP detect sensitivity control OPEN = default controlled by insert resistor * see electrical reference 16 PCTNWID DC: 4.0V dbx RMS detect(wide band) 17 PCDETWID DC: 3.8V dbx wide detect Continued on next page. No.A0015-8/16 LA72700V Continued from preceding page. No. Pin function DC voltage Input/output form Reference AC level 18 PCTIMSPE DC: 3.8V dbx spectral detect 18 5kΩ OMP05019 19 PCDETSPE DC: 3.8V dbx RMS detect (Spectral band) 20 PCSPECIN DC: 3.8V dbx main signal V/I convert filter 21 PCDOSPE DC: 3.8V Offset cancel filter AC: 220mVp-p 22 PCDBXOUT DC: 3.8V AC coupling (Output) AC: 220mVp-p 23 PCDBX_IN AC coupling (Input) Continued on next page. No.A0015-9/16 LA72700V Continued from preceding page. No. Pin function DC voltage Input/output form Reference AC level 24 PCALCFIL DC: 0.6V ALC filter * When ALC function no-use, this terminal is open. 25 PORCH DC: 3.8V Line out R AC: 1.4mVp-p 26 POLCH DC: 3.8V Line out L AC: 1.4mVp-p 27 PCREG DC: 3.8V Reference Voltage Continued on next page. No.A0015-10/16 LA72700V Continued from preceding page. No. Pin function DC voltage Input/output form Reference AC level 28 PMAIN_IN DC: 3.5V AC coupling (Input) AC: 220mVp-p 29 PMAINOUT DC: 3.8V AC coupling (Output) AC: 220mVp-p 30 PCREG76 31 VCC 32 POLED DC: 1.2V Regulator DC* Mode out * See Mode MONO = 0.9V table SAP = 2.0V STEREO = 3.0V STEREO+SAP = 3.8V 33 PICLKFSC DC: 0V Fsc input AC* 3.579545MHz, 200mVp-p * 200mVp-p Recommend Continued on next page. No.A0015-11/16 LA72700V Continued from preceding page. No. Pin function DC voltage Input/output form Reference AC level 34 PCDJFIL DC: 2.5V Filter adjustment signal detect 35 PCPLC DC: 6.3V Pilot canceller reference-1 36 PCPLC2 DC: 6.3V Pilot canceller reference-2 No.A0015-12/16 LA72700V Serial Control (I2C) (1) Data Transfer Manual This LSI adopts control method (I2C -BUS) with serial data, and controlled by two terminals which called SCL (serial clock) and SDA (serial data). At first, set up *1 the condition of starting data transfer, and after that, input 8 bit data to SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of Bit), and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes ‘H’, this LSI pull down the SDA terminal. After transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition, thus the transfer comes to close. *1 Defined by SCL rise down SDA during ‘H’ period. *2 Defined by SCL rise up SDA during ‘H’ period. (2) Transfer Data Format After transfer start condition, transfers slave address (1000000*) to SDA terminal, control data, then, stop condition (See figure 1). Slave address is made up of 7bits, *3 8th bit shows the direction of transferring data, if it is “L”, takes write mode (As this LSI side, this is input operation mode), and in case of ‘H’, reading mode (As this LSI side, this is output operation mode). Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be canceled the transfer dates. *3 It is called R/W bit. Fig.1 DATA STRUCTURE " WRITE " mode START Condition Slave Address R/W L ACK Control data ACK STOP condition ACK Internal Data* ACK STOP condition Fig.2 DATA STRUCTURE " READ " mode START condition Slave Address R/W H * Output 5bits data as follows; bit8 is result of STERO DET (H: STEREO) bit7 is result of SAP DET (H: SAP) bit6 to bit1 are fixed to “L” No.A0015-13/16 LA72700V (3) Initialize This LSI is initialized for circuit protection. Initial condition is “0 (all bits)”. Symbol Min Max LOW level input voltage Parameter VIL -0.5 1.5 V HIGH level input voltage VIIH 3.0 5.5 V 3.0 mA fSCL 0 100 kHz tSU: STA 4.7 µs tHD: STA 4.0 µs tLOW 4.7 tR 0 tHIGH 4.0 tF 0 tHD: DAT 0 Data set-up time tSU: DAT 250 ns Set-up time for STOP condition tSU: STO 4.0 µs tBUF 4.7 µs LOW level output current SCL clock frequency Set-up time for a repeated START condition Hold time START condition. After this period, the first clock pulse is generated LOW period of the SCL clock Rise time of both SDA and SDL signals HIGH period of the SCL clock Fall time of both SDA and SDL signals Data hold time BUS free time between a STOP and START condition IOL Unit µs 1.0 µs µs 1.0 µs µs Timing Chart No.A0015-14/16 LA72700V Measurement Circuit No.A0015-15/16 LA72700V Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. 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Specifications and information herein are subject to change without notice. PS No.8340-16/16