Ordering number : ENA0645 Monolithic Linear IC For US TV LA72702VA BTSC Decoder Overview The LA72702VA is a US TV BTSC Decoder. Features • With SIF circuit, alignment-free* STEREO channel separation. * When Base Band signal input, separation is adjusted by input level. • Dual Slave address. Functions • IF FM-Demodulator. • STEREO decoder. • dbx Noise Reduction. • STEREO detection. • STEREO detection sensitivity change function. • SAP demodulator. • SAP detection. • SAP output select 2-levels. • SAP detection sensitivity change function. Specifications Maximum Ratings at Ta = 25°C Parameter Symbol Maximum power supply voltage VCC max Allowable power dissipation Pd max Conditions Ta ≤ 70°C * Ratings Unit 7.0 V 290 mW Operating temperature Topr -10 to +70 °C Storage temperature Tstg -55 to +150 °C ∗ When mounted on a 114.3mm×76.1mm×1.6mm glass epoxy board. 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To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. 22107 MS PC B8-9054 No.A0645-1/11 LA72702VA Operating Ranges at Ta = 25°C Parameter Symbol Recommended operating voltage VCC Allowable operating voltage range VCC op Conditions Ratings Unit 5.0 V 4.5 to 5.5 V Caution : Please use this IC under license contract with THAT Corporation, because this IC is included dbx noise reduction system. Electrical Characteristics at Ta = 25°C, VDD = 5.0V Parameter Symbol Ratings Conditions min Current dissipation SIF input level ICC VILIM (Reference) No signal Inflow current at pin 19, default condition fc = 4.5MHz typ Unit max 30 40 50 (80) (90) (100) dBμV mA -5.5 -4.5 dBV 0.15 0.6 % 0 2 dB Deviation MONO (300Hz, Mod = 100%, Pre-emphasis ON) Æ ±25kHz Base band input level VILIMB (Reference) MONO output level MONO distortion 100% Modulation MONO(L+R) : 530mVp-p (300Hz, Pre-emphasis ON) VOMON SUB(L-R) : 380mVp-p (300Hz, dbx-NR ON), Pilot : 110mVp-p SAP : 300mVp-p (300Hz, dbx-NR ON) fm = 1kHz, 100% Mod, 15kHz LPF THDMON fm = 1kHz, 100% Mod, 15kHz LPF MONO frequency characteristics FCM1 fm = 3kHz, 30% Mod, Ore-em. ON MONO S/N ratio SNM S = VOMON, N = 0% Mod, 15kHz LPF STEREO output level VOST fm = 1kHz, 100% Mod, 15kHz LPF STEREO distortion THDS fm = 1kHz, 100% Mod, 15kHz LPF STEREO frequency characteristics FCS1 -6.5 -2 * Measure ratio from fm = 1kHz level. 55 65 -7.0 -5.5 -3.0 dBV 1.0 2.5 % -3 0 3 dB S = VOST, N = 0% Mod, 15kHz LPF 50 60 dB dB fm = 3kHz, 30% Mod, 15kHz LPF dB * Measure ratio from fm = 1kHz level. STEREO S/N ratio SNS STEREO separation 1 STSE1 f = 300Hz (R/L), 30% Mod, 15kHz LPF 15 25 STEREO separation 2 STSE2 f = 3kHz (R/L), 30% Mod, 15kHz LPF 15 25 STEREO Detection level-1 VINSD1 Except Stereo Detection Æ Stereo Detection 30 35 40 % 40 45 50 % 10 20 30 % -14.0 -11.0 -8.0 dBV -12.0 -9.0 -6.0 dBV 2.5 3.5 dB * serial control 1 “SENS HI” Pilot (fH) = 15.73kHz * Measure Pilot level. STEREO Detection level-2 VINSD2 Except Stereo Detection Æ Stereo Detection * serial control “SENS LO” STEREO Detection hysteresis HYST Input Mod. Difference at Stereo/Except Stereo Det. * serial control 1 “SENS HI” SAP output level-1 VOSA1 fm = 1kHz, 100% Mod, 15kHz LPF * SAP-1 (serial control) SAP output level-2 VOSA2 fm = 1kHz, 100% Mod, 15kHz LPF * SAP-2 (serial control) SAP distortion THDSA SAP S/N ratio SNSA SAP detection level-1 VINSA1 fm = 1kHz, 100% Mod, 15kHz LPF % S = VOSA, N = 0% Mod, 15kHz LPF 50 60 dB Except SAP → SAP Det. 10 15 20 % 15 20 25 % 2 5 10 % V * serial control 1 “SENS HI” SAP Carrier = 5fH only * Measure Output level. SAP detection level-2 VINSA2 (Reference) Except SAP → SAP Det. * serial control 1 “SENS LO” * Measure Output level. SAP detection hysteresis HYSA Input Mod. Difference at SAP/Except SAP Det. * SAP carrier only. * serial control 1 “SENS HI” MODE output MONO MODMO Input = MONO : f = 1kHz, 0% Mod 0.7 1 1.3 MODE output SAP MODSA Input = SAP : Carrier 1.6 1.9 2.2 V MODE output STEREO MODST Input = STEREO : Pilot 2.5 2.8 3.1 V MODE output ST + SAP MODSS Input = STEREO : Pilot, 3.5 3.8 4.2 V SAP : Carrier * Normally measurement condition is Input = SIF mode (90dBµV) * " Reference " Items are reference levels, their specs are no-guarantee. No.A0645-2/11 LA72702VA Package Dimensions unit : mm (typ) 3287 6.5 24 0.5 6.4 4.4 13 12 1 0.5 0.15 0.22 0.1 (1.3) 1.5max (0.5) SANYO : SSOP24(225mil) No.A0645-3/11 4.7kΩ 1μF + 1μF + 1 PILOT DET STEREO PLL 24 2 1μF + 3 SAP BPF 4 from Tuner 4.5M BPF 1μF + 5 SIF DEMOD 1μF + LPF SAP DEMOD L-R DEMOD MODE OUT 20 47μF PILOT CANCELLER REGULATOR 21 2.2μF + -6dB 22 1μF + PILOT LEVEL DET 23 1μF + 0.1μF + 6 GND ST/SAP SW MUTE MUTE 19 1μF + 7 SAP DET LPF LPF 18 L+R 8 Address 17 16 + 14 I2C CLOCK 10 0.1μF ST SAP 11 Offset Cancell dbx processor 13 + 4.7μF 12 22μF + 22μF + SLAVE ADDRESS = 80h (1000 000*) : Pin8 = OPEN SLAVE ADDRESS = 84h (1000 010*) : Pin8 = H I2C DATA 9 I2C DECODE + 4.7μF 15 SYSTEM CONTROL Control 4.7μF L-R/SAP 10μF + Address Control MATRIX 10μF 0.1μF + 100μF Offset Cancel Package : SSOP24(225mil) Spectral In VCC 5V Wide RMS DET OUT(R) Spectral DET OUT(L) Spectral RMS DET MODE Monitor out LA72702VA Block Diagram and Application No.A0645-4/11 LA72702VA Pin Functions Pin No. 1 Pin Name PCPLDET Function Pilot level detect For Stero Detection DC voltage Equivalent Circuit AC level DC : 2.4V 40kΩ 40kΩ 1 1kΩ 160kΩ 2 PC DC IN AC coupling (Input) DC : 2.4V AC : 2.4Vp-p 3 PC DCOUT AC coupling (Output) DC : 2.4V 500Ω 3 2 1kΩ AC : 2.4Vp-p 4 PISIF Signal input DC : 3.7V Common input at SIF, Baseband 4 5kΩ 500Ω 1kΩ 5 PC FIL SIF offset cancel DC : 2.6V 1kΩ 1kΩ 5 6 GND 7 CSAPDET SAP carrier level detect For SAP detection DC : 2.8V 70kΩ 1kΩ 2kΩ 1kΩ 1kΩ 7 8 ADDSEL Slave Address change control OPEN/GND : 80h 5V DC : 0V 8 : 84h 1kΩ 100kΩ Continued on next page No.A0645-5/11 LA72702VA Continued from preceding page. Pin No. 9 Pin Name SDA Function DC voltage Equivalent Circuit AC level Serial data input 5V 9 1kΩ 0V 10 SCL Serial clock input 5V 10 1kΩ 0V 11 PC DBXIN Offset cancel Feedback filter DC : 1.6V 450kΩ 11 500Ω 12 PCDETSPE Spectral band RMS detect DC : 2.3V 1kΩ 200Ω 12 13 PCTIMSPE dbx spectral detect DC : 2.4V 13 14 PCTNWID dbx RMS detect (wide band) 5kΩ DC : 2.4V 1kΩ 200Ω 14 15 PCSPECIN dbx main signal V/I convert filter DC : 2.4V 15 10kΩ 16 PC KE6B Offset cancel filter DC : 2.4V AC : 220mVp-p 250Ω 500Ω 16 500Ω Continued on next page No.A0645-6/11 LA72702VA Continued from preceding page. Pin No. 17 Pin Name PORCH Function Line out R DC voltage Equivalent Circuit AC level DC : 2.4V AC : 1.4Vp-p 50kΩ 300Ω 300Ω 17 50kΩ 18 POLCH Line out L DC : 2.4V AC : 1.4Vp-p 50kΩ 300Ω 300Ω 18 50kΩ 19 VCC 20 POLED MONO = 3.0V DC : See Right SAP = 2.0V AC STEREO = 1.0V Test only STEREO + SAP = 3.8V 20 1kΩ Mode out 21 PCREG Reference Voltage DC : 2.4V 10kΩ 9.6kΩ 500Ω 21 1kΩ 23 PCPLC Pilot level detect For Pilot canceller DC : 2.4V 40kΩ 40kΩ 1kΩ 160kΩ 23 24 PCPLDET Pilot level detect For ST PLL filter DC : 2.4V 40kΩ 40kΩ 1kΩ 160kΩ 24 No.A0645-7/11 LA72702VA I2C BUS serial interface specification (1) Data Transfer Manual This IC adopts control method(I2C-BUS) with serial data, and controlled by two terminals which called SCL(serial clock) and SDA (serial data).At first, set up*1 the condition of starting data transfer, and after that, input 8 bit data to SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of Bit), and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes ‘H’, this IC pull down the SDA terminal. After transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition, thus the transfer comes to close. *1 Defined by SCL rise down SDA during ‘H’ period. *2 Defined by SCL rise up SDA during ‘H’ period. (2) Transfer Data Format After transfer start condition, transfers slave address (1000 000*) to SDA terminal, control data, then, stop condition (See figure 1). Slave address is made up of 7bits, 8th bit*3 shows the direction of transferring data, if it is ‘L’ takes write mode (As this IC side, this is input operation mode), and in case of ‘H’ reading mode (As this IC side, this is output operation mode). Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be canceled the transfer dates. *3 It is called R/W bit. Fig.1 DATA STRUCTURE “WRITE” mode START Condition Slave Address R/WL ACK Control data ACK STOP condition ACK Internal Data * ACK STOP condition Fig.2 DATA STRUCTURE “READ” mode START condition Slave Address R/WH ∗ Output data as follows ; bit8 is result of STERO DET (H : STEREO), bit7 is result of SAP DET (H : SAP), bit6 to bit1 are fixed to ‘L’ (3) Initialize This IC is initialized for circuit protection. Initial condition is “0 (All bits) ”. No.A0645-8/11 LA72702VA I2C Timing Specifications Parameter Symbol min max unit LOW level input voltage VIL -0.5 1.5 HIGH level input voltage VIH 3.0 5.5 V LOW level output current IOL 3.0 mA 100 kHz SCL clock frequency fSCL 0 V Set-up time for a repeated START condition tSU : STA 4.7 μs Hold time START condition. After this period, the first clock pulse is generated tHD : STA 4.0 μs tLOW 4.7 μs LOW period of the SCL clock Rise time of both SDA and SDL signals tR HIGH period of the SCL clock 0 tHIGH Fall time of both SDA and SDL signals tF 1.0 0 μs μs 4.0 1.0 μs μs Data hold time : tHD : DAT 0 Data set-up time tSU : DAT 250 ns Set-up time for STOP condition tSU : STO 4.0 μs tBUF 4.7 μs BUS free time between a STOP and START condition Definition of timing tR t HI G H tF S CL t HD : S TA t SU : S TA t LO W t HD : D AT A t SU : D AT t SU : S TO t BU F S DA No.A0645-9/11 LA72702VA I2C Control Table Grp-1 (Normally use : group-1 only) D8 D7 D6 D5 D4 D3 * * * D2 D1 Condition 0 0 Stereo 0 1 SAP 1 0 Both 1 1 MUTE 0 Normal (Auto det) 1 Forced Mono 0 SAP SENS LO 1 * * * * SAP SENS HI 0 Stereo SENS LO 1 Stereo SENS HI 0 SAP Level-1 1 SAP Level-2 0 SIF mode 1 Base Band mode 0 Fix 1 Prohibit (TEST MODE) * : Shows Initial condition Read out data D8 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 Condition Fixed 0 Normal 1 SAP det 0 Normal 1 Stereo det Test mode condition When STOP condition transform at Grp-1 data-end, controlled NORMAL mode. Grp-2 (Only test condition : Normally, this data is no-need) D8 D7 D6 D5 D4 D3 D2 D1 Condition/Monitor position 0 0 0 0 0 0 0 0 Normal (Usually, Fixed) 0 0 0 0 0 0 0 1 TEST-1 SIF output 0 0 0 0 0 0 1 0 TEST-2 SAP BPF 0 0 0 0 0 0 1 1 TEST-3 (reserved) 0 0 0 0 0 1 0 0 TEST-4 ST VCO 0 0 0 0 0 1 0 1 TEST-5 (reserved) 0 0 0 0 0 1 1 0 TEST-6 SAP monitor 0 0 0 0 0 1 1 1 TEST-7 ST monitor 0 0 0 0 1 0 0 0 TEST-8 Pilot cancel monitor 0 0 0 0 1 0 0 1 TEST-9 dbx 2.19k LPF 0 0 0 0 1 0 1 0 TEST-10 dbx 408 LPF 0 0 0 0 1 0 1 1 TEST-11 dbx DET 10k LPF 0 0 0 0 1 1 0 0 TEST-12 dbx SPEC 7.6k LPF 0 0 0 0 1 1 0 1 TEST-13 dbx SPEC output 0 0 0 0 1 1 1 0 TEST-14 (reserved) 0 0 0 0 1 1 1 1 TEST-15 dbx 2.09k LPF Blanc Bit are no-care No.A0645-10/11 LA72702VA Mode Condition Detection SIGNAL ST control SAP output Mode Condition System Mute Mono 18 17 20 L ch R ch Mode 3.8V STEREO ST SAP STEREO L : NORM L : NORM STEREO L R + DET DET BOTH L : NORM L : NORM MULTI LR SAP SAP L : NORM L : NORM SAP SAP SAP STEREO L : NORM H : MONO MONO L+R L+R BOTH L : NORM H : MONO MONO L+R L+R SAP L : NORM H : MONO MONO L+R L+R ST STEREO L : NORM L : NORM STEREO L R DET BOTH L : NORM L : NORM STEREO L R SAP L : NORM L : NORM STEREO L R STEREO L : NORM H : MONO MONO L+R L+R BOTH L : NORM H : MONO MONO L+R L+R SAP L : NORM H : MONO MONO L+R L+R SAP STEREO MONO SAP STEREO L : NORM L : NORM MONO L+R L+R + DET BOTH L : NORM L : NORM MULTI L+R SAP SAP L : NORM L : NORM SAP SAP SAP STEREO L : NORM H : MONO MONO L+R L+R BOTH L : NORM H : MONO MONO L+R L+R SAP L : NORM H : MONO MONO L+R L+R STEREO L : NORM L : NORM MONO L+R L+R BOTH L : NORM L : NORM MONO L+R L+R SAP L : NORM L : NORM MONO L+R L+R STEREO L : NORM H : MONO MONO L+R L+R BOTH L : NORM H : MONO MONO L+R L+R SAP L : NORM H : MONO MONO L+R L+R * H : MUTE * MUTE OFF OFF SAP MONO * * * 3.0V 2.0V 1.0V Each * : no problem SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of February, 2007. Specifications and information herein are subject to change without notice. PS No.A0645-11/11