SANYO LB1991V_09

Ordering number : EN5792B
Monolithic Digital IC
LB1991V
For Fan Motor
3-phase Brushless Motor Driver
Overview
The LB1991V is a 3-phase brushless motor driver IC that is optimal for driving the DC fan motor.
Functions
• 3-phase full-wave voltage drive technique (120° voltage-linear technique)
• Torque ripple correction circuit (overlap correction)
• Speed control technique based on motor voltage and current control
• Built-in FG comparators
• Built-in thermal shutdown circuit
Specifications
Absolute Maximum Ratings at Ta = 25°C
Parameter
Maximum supply voltage
Symbol
Conditions
Ratings
Unit
VCC1 max
10
V
VCC2 max
11
V
V
VS max
11
Applied output voltage
VO max
VS+2
V
Maximum output current
IO max
1.0
A
Allowable power dissipation
Pd max
440
mW
Operating temperature
Topr
-20 to +75
°C
Storage temperature
Tstg
-55 to +150
°C
Independent IC
Allowable Operating Ranges at Ta = 25°C
Parameter
Supply voltage
Symbol
VCC1
Conditions
VCC1 ≤ VCC2
VCC2
VS
Hall input amplitude
VHALL
Ratings
Unit
2.7 to 6.0
V
3.5 to 9.0
V
Up to VCC2
Between Hall effect element inputs
±20 to ±80
V
mVp-p
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
10709 MS/73099TH (OT)/53098RM (OT) No.5792-1/7
LB1991V
Electrical Characteristics at Ta = 25°C, VCC1 = 3V, VCC2 = 4.75V, VS = 1.5V
Parameter
Symbol
Ratings
Conditions
min
typ
Unit
max
Supply Current
VCC1 current drain
ICC1
IOUT = 100mA
3
5
mA
VCC2 current drain
ICC2
IOUT = 100mA
7.0
10.0
mA
VCC1 quiescent current
ICC1Q
VSTBY = 0V
1.5
3.0
mA
VCC2 quiescent current
ICC2Q
VSTBY = 0V
100
µA
VS quiescent current
ISQ
VSTBY = 0V
75
100
µA
VX1
High side residual voltage
VXH1
IOUT = 0.2A
0.15
0.22
0.29
V
Low side residual voltage
VXL1
IOUT = 0.2A
0.15
0.20
0.25
V
VX2
High side residual voltage
VXH2
IOUT = 0.5A
0.25
0.40
V
Low side residual voltage
VXL2
IOUT = 0.5A
0.25
0.40
V
Output saturation voltage
VO(sat)
IOUT = 0.8A, Sink + Source
1.4
V
Overlap
O.L
RL = 39Ω × 3, Rangle = 20kΩ *2
72
High/low overlap difference
∆O.L
(Average upper side overlap) –
(Average lower side overlap) *2
-8
Input offset voltage
VHOFF
Design target *1
Common-mode input voltage range
VHCM
Rangle = 20kΩ
I/O voltage gain
VGVH
Rangle = 20kΩ
25.5
80
87
%
+8
%
-5
+5
mV
0.95
2.1
V
31.5
dB
Hall Amplifiers
28.5
Standby Pin
High-level voltage
VSTH
Low-level voltage
VSTL
2.5
Input current
ISTIN
VSTBY = 3V
Leakage current
ISTLK
VSTBY = 0V
V
25
0.4
V
40
µA
-30
µA
FRC Pin
High-level voltage
VFRCH
Low-level voltage
VFRCL
2.5
Input current
IFRCIN
VFRC = 3V
Leakage current
IFRCLK
VFRC = 0V
Hall supply voltage
VHALL
IH = 5mA, VH(+) − VH(−)
0.85
(−) pin voltage
VH(−)
IH = 5mA
0.81
V
0.4
V
30
µA
-30
µA
0.95
1.05
V
0.88
0.95
V
25
VH
FG Comparator
Input offset voltage
VFGOFF
Input bias voltage
IbFG
-3
Input bias current offset
∆IbFG
Common-mode input voltage range
VFGCM
Output high-level voltage
VFGOH
At the internal pull-up resistors
Output low-level voltage
VFGOL
At the internal pull-up resistors
Voltage gain
VGFG
Design target *1
Output current (sink)
IFGOS
For the output pin low level
Operating temperature
TSD
Design target *1
180
°C
Temperature hysteresis
∆TSD
Design target *1
20
°C
VFGIN+ = VFGIN− = 1.5V
VFGIN+ = VFGIN− = 1.5V
+3
mV
500
nA
-100
+100
nA
1.2
2.5
2.8
V
V
0.2
100
V
dB
5
mA
Thermal shutdown
*1: Design target values in the conditions column are not tested.
*2: The standard for overlap is the value as measured.
No.5792-2/7
LB1991V
Package Dimensions
unit : mm (typ)
3175C
Pd max -- Ta
Allowable power dissipation, Pd max -- W
0.5
7.8
24
0.5
5.6
7.6
13
12
1
0.65
(0.33)
0.15
1.5max
(1.3)
0.22
0.44
0.4
0.3
0.264
0.2
0.1
0
-20
0
20
40
60
75 80
100
0.1
Ambient temperature, Ta -- °C
SANYO : SSOP24(275mil)
FGOUT
FGIN−
FGIN+
WIN2
WIN1
VIN2
VIN1
UIN2
UIN1
STBY
FRC
GND
Pin Assignment
24
23
22
21
20
19
18
17
16
15
14
13
LB1991V
UOUT
9
10
11
12
ANGLE
NC
8
VH−
VS
7
VH+
VCC2
6
WOUT
5
RF
4
VOUT
3
RF
2
VCC1
Top view
1
Truth Table
Hall input
Source phase → Sink phase
1
2
3
4
5
6
V→W
W→V
U→W
W→U
U→V
V→U
W→V
V→W
W→U
U→W
V→U
U→V
FRC
U
V
W
H
H
L
H
L
H
L
L
H
L
H
L
H
H
L
L
L
H
H
L
L
H
H
H
L
L
H
L
H
L
Note: The “H” entries in the FRC column indicate a voltage of 2.50V or higher, and the “L” entries indicate a voltage of 0.4V or lower. (When VCC1 is 3V.)
At the Hall inputs, for each phase a high-level input is the state where the (+) input is 0.02V or higher than the (−) input. Similarly, a low-level input is the
state where the (+) input is 0.02V or lower than the (−) input.
No.5792-3/7
W
V
U
GND 13
VS/4
Vx
R2
Hall input synthesis (matrix)
R3
R4
VO1
Vx+α
1
1
VO1= 1
4 VS+( 4 VS-Vx)= 2 VS-Vx
R3
O.L=
R3+R4
R2
VCC2
I=O.L×VO1/(1.5×R5)
1.5×R5
Drive signal current generation block
R1
R1
2×R1
VS/2
U-V
V-W
W-U
SBD
+Vf
VO2
Vx+Vf
(VS/2)+α
VO3
R6
B
B
B
FG amplifier
VCC1
Hall power-supply
voltage output
circuit
Bias supply
1.2V reference
voltage and bias
startup circuit
23
22
FGIN+ FGIN−
R6
VS−Vx−Vf+2α
SBD
TSD
R5
R5
R5
1
VO3= 1
2 VS+α−(Vx+Vf)+ 2 VS+α=VS−Vx−Vf+2α
Vx+Vf
O.L×VO1
SBD
R5
R5
R5
2
Upper/lower
amplitude
limiters
3I Current
0 distribution
3I
Power to the hatch blocks is supplied from VCC2.
Synthesized signal level shifters
Hall amplifiers
ANGLE 12
WIN2 21
WIN1 20
VIN2 19
VIN1 18
UIN2 17
UIN1 16
FRC 14
Forward/
reverse
switching
VCC2
24 FGOUT
11 VH−
10 VH+
15 STBY
1 VCC1
8 RF
6 RF
9 WOUT
7 VOUT
5 UOUT
3 VS
LB1991V
Block Diagram
No.5792-4/7
LB1991V
Pin Function
Pin No.
1
Pin name
VCC1
Pin function
Equivalent circuit
Supply voltage for all circuits other than the IC internal
output block and the amplitude control block.
2
VCC2
Supply voltage for the IC internal output control block and
the amplitude control block.
3
VS
2 VCC2
Motor drive power supply. The voltage applied to this pin
must not exceed VCC2.
5
UOUT
U phase output.
7
VOUT
V phase output.
9
WOUT
W phase output.
10kΩ
3 VS
1/2×VS
5kΩ
1/4×VS
Each
5
OUT
(7,9)
5kΩ
6 RF
(8)
(These outputs include built-in spark killer diodes.)
6,8
RF
Ground for the output power transistors.
10
VH+
Hall element bias voltage supply.
1 VCC1
A voltage that is typically 0.95V is generated between the
VH+ and VH− pins (When IH is 5mA).
VH−
20kΩ
About
1.9V
13
GND
10
VH+
20kΩ
11
11 VH−
About
0.9V
Ground for circuits other than the output transistor.
The RF pin potential is the lowest output transistor potential.
14
FRC
Forward/reverse selection. Applications can select motor
forward or reverse direction rotation using this pin. (This pin
VCC1
VCC1
has hysteresis characteristics.)
STBY
Selects the bias supply for all circuits other than the FG
FRC
14
The bias supply is cut when this pin is set to the low level.
17
18
19
UIN1
UIN2
VIN1
VIN2
100kΩ
100kΩ
comparators.
16
STBY
15
50kΩ
100kΩ
15
U phase Hall element input.
The logic high level is the state where the IN+ voltage is
greater than the IN− voltage.
1 VCC1
0.3V
V phase Hall element input.
The logic high level is the state where the IN+ voltage is
greater than the IN− voltage.
4kΩ
4kΩ
(18,20)
Each
16 input of 1
200Ω
VCC1
21
12
WIN1
W phase Hall element input.
WIN2
The logic high level is the state where the IN+ voltage is
greater than the IN− voltage.
ANGLE
200Ω
1.2V typ
20
400Ω 400Ω
17
200Ω
Each
input of 2
(19,21)
ANGLE 17
Hall input/output gain control. The gain is controlled by the
resistor connected between this pin and ground.
22
FGIN+
FG comparator non-inverting inputs.
VCC1
There is no internally applied bias.
FGOUT
FGIN−
23
200Ω
200Ω
FGIN+
22
20kΩ
FG comparator inverting inputs.
There is no internally applied bias.
24
15kΩ
FGIN−
FGOUTN
24
FG comparator outputs.
There is an internal 20kΩ resistor load.
50kΩ
23
1
No.5792-5/7
LB1991V
Overlap Generation and Calculation Method
VS
VS
Upper side
residual voltage VXH
Upper side clamp potential
VS−VXH
Vα
Absolute voltage
Electrical A
angle
B
VS−VXH
VS
O.L × ( 2 −VXH)
VS
−
2 VXH
180°
Calculated center point
VN
C
D
Vβ
Lower side clamp
potential
Lower side
residual voltage VXL
VXL
0
VXL
Time
Overlap Generation
Since the voltage generated in the amplitude control block is, taking the center point as the reference, 2 × <overlap> ×
(1/2 VS − VX) on one side, the intersection point of the waveform will be <overlap> × (1/2 VS − VX) from the center
point.
To clamp that waveform at (1/2 VS − VX) referenced to the center point the overlap must be:
A/B × 100 = <overlap> × 100 (%).
Overlap Calculation
• Upper side overlap
(VS − VXH − VXL)
(VS − VXH + VXL)
+ VXL =
2
2
Since A = Vα − VN, B = VS − VXH − VN, the upper side overlap will be:
Vα − ((VS − VXH + VXL)/2)
A
<overlap> = B =
×100
VS − VXH − ((VS − VXH + VXL)/2)
Calculated center point: VN =
Which can be calculated as:
=
2Vα − (VS − VXH) − VXL
×100(%)
(VS − VXH) − VXL
• Lower side overlap
Since C = VN − Vβ, and D = VN − VXL, the lower side overlap will be:
((VS − VXH + VXL)/2) − Vβ
C
<overlap> = D =
×100
((VS − VXH + VXL)/2) − VXL
Which can be calculated as:
=
(VS − VXH) + VXL − 2Vβ
×100(%)
(VS − VXH) − VXL
No.5792-6/7
LB1991V
Test Circuit
±15V
1kΩ
1µF
100kΩ
3
2
1
3
3
SV
Im6
SW
2
1
2 1
3
3
SO
2
1
SL
SK
A
SJ
Im5
Im7
1kΩ
SU
3
IOUT3
5mA
2 1 3
1
1
VIN
f=1kHz
−50dBm
LA6358
VH3
SM
SN
VH2
VH1
0.1µF
1
2
100kΩ
A
3
SP
SR
1kΩ
1
1
SQ
2
A
2
2
VSTBY
A
1
100kΩ
Im4
VFRC
2
ST
Vm4 V
2
SS
VFG1
LB1991V
1
VFG2
2
SA
Im1
VCC1
3V
V
A
SB
Im2
SH
A
VCC2
4.75V
2
SC
Im3
Vm3
S1
IOUT2
2
20kΩ
1
4mA
A
VS
1.5V
SD
Vm1 V
IOUT1
100mA
200mA
500mA
800mA
1
1 2 3
1 2 3
SE
SF
SG
The following hold
unless otherwise specified:
VCC1=3V
VCC2=4.75V
VS =1.5V
V
Vm2
39Ω × 3
V
Vm5
VH1=1.4V
VH2=4.75V
VH3=1.5V
VFRC=3V
VSTBY=3V
VFG1=VFG2=1.5V
Switch status:
0 : CLOSED
X : OPEN
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellctual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of January, 2009. Specifications and information herein are subject
to change without notice.
PS No.5792-7/7