SANYO LC875932A

Ordering number : ENA0125B
LC875932A
LC875924A
LC875916A
CMOS IC
Internal 32K/24K/16K-byte ROM and 1024-byte RAM
8-bit 1-chip Microcontroller
Overview
The SANYO LC875932A/24A/16A are 8-bit microcomputer that, centered around a CPU running at a minimum bus
cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 32K/24K/16K-byte ROM,
1024-byte RAM, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be
divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a time-ofday clock, a high-speed clock counter, a synchronous SIO interface (with automatic block transmission/reception
capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), an 8-bit 11-channel AD
converter, two 12-bit PWM channels, a system clock frequency divider, ROM correction function, and a 23-source
10-vector interrupt feature.
Features
„ROM
• 32768 × 8 bits (LC875932A)
• 24576 × 8 bits (LC875924A)
• 16384 × 8 bits (LC875916A)
„RAM
• 1024 × 9 bits (LC875932A/24A/16A)
„Minimum Bus Cycle
• 83.3ns (12MHz)
VDD=3.0 to 5.5V
• 125ns (8MHz)
VDD=2.5 to 5.5V
• 500ns (2MHz)
VDD=2.2 to 5.5V
Note: The bus cycle time here refers to the ROM read speed.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
Ver.1.04
62508HKIM 20080530-S00002 No.A0125-1/23
LC875932A/24A/16A
„Minimum Instruction Cycle Time
• 250ns (12MHz)
VDD=3.0 to 5.5V
• 375ns (8MHz)
VDD=2.5 to 5.5V
• 1.5µs (2MHz)
VDD=2.2 to 5.5V
„Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units
Ports whose I/O direction can be designated in 4-bit units
• Normal withstand voltage input ports
• Dedicated oscillator ports
• Reset pins
• Power pins
46 (P1n, P2n, P70 to P73, P80 to P86, PBn, PCn,
PWM2, PWM3, XT2)
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
6 (VSS1 to 3, VDD1 to 3)
„Timers
• Timer 0: 16-bit timer/counter with a capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) + 8-bit counter
(with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs)
+ 8-bit timer/counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(the lower-order 8 bits can be used as PWM)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
„High-speed Clock Counter
• Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz)
• Can generate output real-time
„SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle =4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
No.A0125-2/23
LC875932A/24A/16A
„UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator
„AD Converter: 8 bits × 11 channels
„PWM: Multifrequency 12-bit PWM × 2 channels
„Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
• Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
„Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
„Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
„Interrupts
• 23 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
1
00003H
X or L
INT0
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/INT5/base timer0/base timer1
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/UART1 receive
8
0003BH
H or L
SIO1/UART1 transmit
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0/T4/T5/PWM2, PWM3
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
„Subroutine Stack Levels: 512 levels (the stack is allocated in RAM)
„High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
„Oscillation Circuits
• RC oscillation circuit (internal):
• CF oscillation circuit:
• Crystal oscillation circuit:
For system clock
For system clock, with internal Rf
For low-speed system clock, with internal Rf
No.A0125-3/23
LC875932A/24A/16A
„System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs,
and 76.8μs (at a main clock rate of 10MHz).
„Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer
(3) Occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4, or INT5
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are five ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4, or INT5
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0
(5) Having an interrupt source established in the base timer circuit
„ROM Correction Function
• Executes the correction program on detection of a match with the program counter value.
• Correction program area size: 128 bytes
„Package Form
• QIP64E (14 × 14):
Lead-free type
• TQFP64J (7 × 7):
Lead-free type
• FLGA68K (6.0 × 6.0): Lead-free type
„Development Tools
• Onchip debugger: LC87F5932A+TCB87 TypeA/TypeB
No.A0125-4/23
LC875932A/24A/16A
Package Dimensions
Package Dimensions
unit : mm (typ)
3159A
unit : mm (typ)
3289
17.2
14.0
9.0
64
17
49
32
64
17
7.0
32
14.0
49
33
1
1
0.8
16
0.4
16
0.35
0.15
0.16
9.0
48
0.5
7.0
0.8
33
17.2
48
0.125
(0.5)
0.1
0.1
3.0max
1.2max
(2.7)
(1.0)
(1.0)
SANYO : TQFP64J(7X7)
SANYO : QIP64E(14X14)
Package Dimensions
unit : mm (typ)
3326
BOTTOM VIEW
6.0
1 2 3 4 56 7
8 9 10 11
0.5
0.5
0.3
0.5
6.0
(0.45)
TOP VIEW
L K J H G F ED C BA
0.3
0.5
0.4
0.0NOM
SIDE VIEW
0.85MAX
(0.45)
SANYO : FLGA68K(6.0X6.0)
No.A0125-5/23
LC875932A/24A/16A
PB1
PB0
VSS3
VDD3
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
P86/AN6
P85/AN5
P84/AN4
P83/AN3
Pin Assignments
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P70/INT0/T0LCP/AN8
49
32
PB2
P71/INT1/T0HCP/AN9
50
31
PB3
P72/INT2/T0IN
51
30
PB4
P73/INT3/T0IN
52
29
PB5
RES
53
28
PB6
XT1/AN10
54
27
PB7
XT2/AN11
55
26
P27/INT5/T1IN
VSS1
56
25
P26/INT5/T1IN
CF1
57
24
P25/INT5/T1IN
CF2
58
23
P24/INT5/T1IN
LC875932A
LC875924A
LC875916A
P21/URX/INT4/T1IN
19
P20/UTX/INT4/T1IN
P10/SO0
63
18
P07/T7O
P11/SI0/SB0
64
17
P06/T6O
9 10 11 12 13 14 15 16
P04
8
P05/CKO
7
P03
6
P02
5
P01
4
P00
3
VSS2
2
VDD2
1
PWM3
20
62
PWM2
61
P82/AN2
P16/T1PWML
P81/AN1
P17/T1PWMH/BUZ
P22/INT4/T1IN
P15/SCK1
P23/INT4/T1IN
21
P13/SO1
22
60
P14/SI1/SB1
59
P12/SCK0
VDD1
P80/AN0
Top view
SANYO: QIP64E (14 × 14)
SANYO: TQFP64J (7 × 7)
“Lead-free Type”
“Lead-free Type”
No.A0125-6/23
LC875932A/24A/16A
11
51
49
47
45
43
41
39
37
35
48
46
44
42
40
38
36
33
34
10
52
50
9
54
53
31
32
8
56
55
29
30
7
58
57
27
28
6
60
59
25
26
5
62
61
23
24
4
64
63
21
22
3
66
65
19
20
2
68
67
2
4
6
8
10
12
14
16
18
1
3
5
7
9
11
13
15
17
B
C
D
E
F
G
H
J
K
1
A
LC875932A
LC875924A
LC875916A
L
Top view
Pin
Pin Name
No.
Pin
Pin Name
No.
Pin
No.
Pin Name
Pin
Pin Name
No.
1
P12/SCK0
18
P06/T6O
35
PB1
52
P70/INT0/T0LCP/AN8
2
P13/SO1
19
P07/T7O
36
PB0
53
P71/INT1/T0HCP/AN9
3
P14/SI1/SB1
20
P20/UTX/INT4/T1IN
37
VSS3
54
P72/INT2/T0IN
4
P15/SCK1
21
P21/URX/INT4/T1IN
38
VDD3
55
P73/INT3/T0IN
5
P16/T1PWML
22
P22/INT4/T1IN
39
PC7
56
RES
6
P17/T1PWMH/BUZ
23
P23/INT4/T1IN
40
PC6
57
XT1/AN10
7
PWM2
24
P24/INT5/T1IN
41
PC5
58
XT2/AN11
8
PWM3
25
P25/INT5/T1IN
42
PC4
59
VSS1
9
VDD2
26
P26/INT5/T1IN
43
PC3
60
CF1
10
VSS2
27
P27/INT5/T1IN
44
PC2
61
CF2
11
P00
28
PB7
45
PC1
62
VDD1
12
P01
29
PB6
46
PC0
63
P80/AN0
13
P02
30
PB5
47
P86/AN6
64
P81/AN1
14
P03
31
PB4
48
P85/AN5
65
P82/AN2
15
P04
32
PB3
49
P84/AN4
66
P10/SO0
16
P05/CKO
33
PB2
50
P83/AN3
67
P11/SI0/SB0
17
No Connect
34
No Connect
51
No Connect
68
No Connect
Note: Pin number 17, 34, 51, 68 of NC terminals are not connected electrically. Also, A1, A11, L1, L11 are dummy
terminals for the package. These terminals need to be bonded with foot pattern for the secure bonding of
the package.
SANYO: FLGA68K (6.0 × 6.0)
“Lead-free Type”
No.A0125-7/23
LC875932A/24A/16A
System Block Diagram
Interrupt control
IR
Standby control
ROM correct
CF
ROM
Clock
generator
RC
PLA
X’tal
PC
SIO0
Bus interface
SIO1
Port 0
ACC
Timer 0
Port 1
B register
Timer 1
Port 2
C register
Timer 4
Port 7
ALU
Timer 5
Port 8
Timer 6
ADC
PSW
Timer 7
INT0 to INT5
Noise filter
RAR
Base timer
Port B
RAM
PWM2/3
Port C
Stack pointer
UART1
Watchdog timer
Onchip debugger
(LC87F5932A)
No.A0125-8/23
LC875932A/24A/16A
Pin Description
Pin Name
VSS1
VSS2
VSS3
VDD1
I/O
Description
Option
-
-Power supply pin
No
-
+Power supply pin
No
• 8-bit I/O port
Yes
VDD2
VDD3
Port 0
I/O
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units.
• HOLD reset input
• Port 0 interrupt input
• Shared pins
P05: Clock output (system clock/can selected from sub clock)
P06: Timer 6 toggle output
P07: Timer 7 toggle output
Port 1
I/O
Yes
• 8-bit I/O port
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1PWML output
P17: Timer 1PWMH output/beeper output
Port 2
P20 to P27
I/O
Yes
• 8-bit I/O port
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P20: UART transmit
P21: UART receive
P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
• Interrupt acknowledge type
Rising
Falling
INT4
enable
enable
INT5
enable
enable
Rising &
H level
L level
enable
disable
disable
enable
disable
disable
Falling
Continued on next page.
No.A0125-9/23
LC875932A/24A/16A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD reset input/timer 0H capture input
P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/
High speed clock counter input
P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input
AD converter input port: AN8 (P70), AN9 (P71)
• Interrupt acknowledge type
Port 8
I/O
Rising
Falling
INT0
enable
enable
INT1
enable
enable
INT2
enable
INT3
enable
Rising &
H level
L level
disable
enable
enable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
• 7-bit I/O port
No
• I/O specifiable in 1-bit units
P80 to P86
• Shared pins
AD converter input port: AN0 (P80) to AN6 (P86)
PWM2,
I/O
PWM3
Port B
• PWM2 and PWM3 output ports
No
• General-purpose I/O available
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
PB0 to PB7
• Pull-up resistors can be turned on and off in 1-bit units.
Port C
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
PC0 to PC7
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins (for LC87F5932A)
On-chip debugger pins: DBGP0 to DBGP2 (PC5 to PC7)
RES
Input
Reset pin
No
XT1
Input
• 32.768kHz crystal oscillator input pin
No
• Shared pins
General-purpose input port
AD converter input port : AN10
Must be connected to VDD1 if not to be used.
XT2
I/O
• 32.768kHz crystal oscillator output pin
No
• Shared pins
General-purpose I/O port
AD converter input port: AN11
Must be set for oscillation and kept open if not to be used.
CF1
Input
CF2
Output
Ceramic resonator input pin
No
Ceramic resonator output pin
No
No.A0125-10/23
LC875932A/24A/16A
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
Option Selected
in Units of
Option Type
P00 to P07
1 bit
1
P10 to P17
1 bit
P20 to P27
1 bit
Output Type
Pull-up Resistor
CMOS
Programmable (Note 1)
2
Nch-open drain
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
Programmable
P70
-
No
Nch-open drain
Programmable
P71 to P73
-
No
CMOS
Programmable
P80 to P86
-
No
Nch-open drain
No
PWM2, PWM3
-
No
CMOS
No
PB0 to PB7
1 bit
1
CMOS
Programmable
2
Nch-open drain
Programmable
PC0 to PC7
1 bit
1
CMOS
Programmable
2
Nch-open drain
Programmable
Input for 32.768 kHz crystal oscillator
No
XT1
-
No
(Input only)
XT2
-
No
Output for 32.768kHz crystal oscillator
No
(Nch-open drain when in general-purpose
output mode)
Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1: Connect the IC as shown below to minimize the noise input to the VDD1 pin.
Be sure to electrically short the VSS1, VSS2, and VSS3 pins.
LSI
VDD1
Power
supply
For backup *2
VDD2
VDD3
VSS1
VSS2
VSS3
*2: The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at the
ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus
shortening the backup time.
Make sure that the port outputs are held at the low level in the HOLD backup mode.
No.A0125-11/23
LC875932A/24A/16A
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD [V]
Maximum supply
VDD max
VDD1, VDD2, VDD3
Input voltage
VI(1)
XT1, CF1
Input/output
VIO(1)
Ports 0, 1, 2
VDD1=VDD2=VDD3
voltage
voltage
min
typ
max
-0.3
+6.5
-0.3
VDD+0.3
unit
V
Ports 7, 8
-0.3
Ports B, C
VDD+0.3
PWM2, PWM3 XT2
Peak output
IOPH(1)
current
High level output current
Mean output
CMOS output select
Per 1 applicable pin
PWM2, PWM3
Per 1 applicable pin
-20
IOPH(3)
P71 to P73
Per 1 applicable pin
-5
IOMH(1)
Ports 0, 1, 2
CMOS output select
Ports B, C
Per 1 applicable pin
IOMH(2)
PWM2, PWM3
Per 1 applicable pin
IOMH(3)
P71 to P73
Per 1 applicable pin
Total output
ΣIOAH(1)
P71 to P73
Total of all applicable pins
current
ΣIOAH(2)
Port 1
Total of all applicable pins
PWM2, PWM3
ΣIOAH(3)
Ports 0, 2
Total of all applicable pins
ΣIOAH(4)
Ports 0, 1, 2
Total of all applicable pins
PWM2, PWM3
Peak output
-10
IOPH(2)
current
(Note 1-1)
Ports 0, 1, 2
Ports B, C
-7.5
-15
-3
-10
-25
-25
-45
ΣIOAH(5)
Port B
Total of all applicable pins
-25
ΣIOAH(6)
Port C
Total of all applicable pins
-25
ΣIOAH(7)
Ports B, C
Total of all applicable pins
-45
IOPL(1)
P02 to P07
Per 1 applicable pin
current
Ports 1, 2
20
Ports B, C
PWM2, PWM3
Low level output current
Mean output
IOPL(2)
P00, P01
IOPL(3)
IOML(1)
mA
Per 1 applicable pin
30
Ports 7, 8, XT2
Per 1 applicable pin
10
P02 to P07
Per 1 applicable pin
current
Ports 1, 2
(Note 1-1)
Ports B, C
15
PWM2, PWM3
Total output
IOML(2)
P00, P01
Per 1 applicable pin
20
IOML(3)
Ports 7, 8, XT2
Per 1 applicable pin
7.5
ΣIOAL(1)
Port 7
Total of all applicable pins
current
15
P83 to P86, XT2
ΣIOAL(2)
P80 to P82
Total of all applicable pins
15
ΣIOAL(3)
Ports 7, 8, XT2
Total of all applicable pins
20
ΣIOAL(4)
Port 1
Total of all applicable pins
45
PWM2, PWM3
ΣIOAL(5)
Ports 0, 2
Total of all applicable pins
ΣIOAL(6)
Ports 0, 1, 2
Total of all applicable pins
45
80
PWM2, PWM3
Power dissipation
Operating ambient
ΣIOAL(7)
Port B
Total of all applicable pins
45
ΣIOAL(8)
Port C
Total of all applicable pins
45
ΣIOAL(9)
Ports B, C
Total of all applicable pins
Pd max
QIP64E(14 × 14)
Ta=-30 to +70°C
TQFP64J(7 × 7)
170
FLGA68K(6.0 × 6.0)
121
Topr
temperature
Storage ambient
80
375
Tstg
temperature
-30
+70
-55
+125
mW
°C
Note 1-1: The mean output current is a mean value measured over 100ms.
No.A0125-12/23
LC875932A/24A/16A
Allowable Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD [V]
Operating
VDD(1)
VDD1=VDD2=VDD3
supply voltage
Memory
VHD
VDD1=VDD2=VDD3
0.245μs ≤ tCYC ≤ 200μs
typ
max
3.0
unit
5.5
0.367μs ≤ tCYC ≤ 200μs
2.5
5.5
1.47μs ≤ tCYC ≤ 200μs
2.2
5.5
2.0
5.5
RAM and register contents
sustained in HOLD mode.
sustaining
min
supply voltage
High level input
VIH(1)
voltage
Ports 1, 2
P71 to P73
2.2 to 5.5
P70 port input
0.3VDD
VDD
+0.7
/interrupt side
VIH(2)
Ports 0, 8, B, C
2.2 to 5.5
PWM2, PWM3
VIH(3)
Port 70 watchdog
timer side
VIH(4)
Low level input
VIL(1)
voltage
XT1, XT2, CF1
RES
Ports 1, 2
P71 to P73
P70 port input
/interrupt side
VIL(2)
Ports 0, 8, B, C
PWM2, PWM3
VIL(3)
Port 70 watchdog
timer side
VIL(4)
Instruction cycle
XT1, XT2, CF1
RES
tCYC
time
(Note 2-1)
External system
FEXCF(1)
CF1
clock frequency
0.3VDD
+0.7
VDD
2.2 to 5.5
0.9VDD
VDD
2.2 to 5.5
0.75VDD
VDD
4.0 to 5.5
VSS
2.2 to 4.0
VSS
4.0 to 5.5
VSS
2.2 to 4.0
VSS
2.2 to 5.5
VSS
2.2 to 5.5
VSS
0.25VDD
3.0 to 5.5
0.245
200
2.5 to 5.5
0.367
200
V
0.1VDD
+0.4
0.2VDD
0.15VDD
+0.4
0.2VDD
0.8VDD
-1.0
2.2 to 5.5
1.47
200
• CF2 pin open
3.0 to 5.5
0.1
12
• System clock frequency
2.5 to 5.5
0.1
8
2.2 to 5.5
0.1
2
μs
division ratio=1/1
• External system clock duty
=50±5%
• CF2 pin open
3.0 to 5.5
0.2
24.4
• System clock frequency
2.5 to 5.5
0.2
16
2.2 to 5.5
0.2
4
division ratio=1/2
Oscillation
FmCF(1)
CF1, CF2
frequency range
(Note2-2)
12MHz ceramic oscillation
See Fig. 1.
FmCF(2)
CF1, CF2
8MHz ceramic oscillation
See Fig. 1.
FmCF(3)
CF1, CF2
4MHz ceramic oscillation
See Fig. 1.
FmRC
FsX’tal
Internal RC oscillation
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
3.0 to 5.5
12
2.5 to 5.5
8
2.2 to 5.5
4
2.2 to 5.5
2.2 to 5.5
0.3
1.0
32.768
MHz
2.0
kHz
Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-2: See Tables 1 and 2 for the oscillation constants.
No.A0125-13/23
LC875932A/24A/16A
Electrical Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD [V]
High level input
IIH(1)
current
IIH(2)
Ports 0, 1, 2
Output disabled
Ports 7, 8
Pull-up resistor off
Ports B, C
RES
VIN=VDD
(Including output Tr's off leakage
PWM2, PWM3
current)
XT1, XT2
For input port specification
VIN=VDD
Low level input
IIH(3)
CF1
VIN=VDD
IIL(1)
Ports 0, 1, 2
Output disabled
Ports 7, 8
Pull-up resistor off
Ports B, C
RES
VIN=VSS
(Including output Tr's off leakage
PWM2, PWM3
current)
current
IIL(2)
XT1, XT2
For input port specification
VIN=VSS
min
typ
1
2.2 to 5.5
1
2.2 to 5.5
15
2.2 to 5.5
-1
2.2 to 5.5
-1
-15
IIL(3)
CF1
VIN=VSS
2.2 to 5.5
VOH(1)
Ports 0, 1, 2
IOH=-1mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
Ports B, C
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
IOH=-0.4mA
3.0 to 5.5
VDD-0.4
IOH=-0.2mA
2.2 to 5.5
VDD-0.4
IOH=-10mA
4.5 to 5.5
VDD-1.5
VOH(7)
IOH=-1.6mA
3.0 to 5.5
VDD-0.4
VOH(8)
IOH=-1mA
2.2 to 5.5
VDD-0.4
VOH(4)
P71 to P73
VOH(5)
VOH(6)
PWM2, PWM3
unit
2.2 to 5.5
High level output
VOH(3)
max
V
Low level output
VOL(1)
Ports 0, 1, 2
IOL=10mA
4.5 to 5.5
1.5
voltage
VOL(2)
Ports B, C
IOL=1.6mA
3.0 to 5.5
0.4
VOL(3)
PWM2, PWM3
IOL=1mA
2.2 to 5.5
0.4
VOL(4)
Ports 7, 8
IOL=1.6mA
3.0 to 5.5
0.4
VOL(5)
XT2
IOL=1mA
2.2 to 5.5
0.4
VOL(6)
P00, P01
IOL=30mA
4.5 to 5.5
1.5
VOL(7)
IOL=5mA
3.0 to 5.5
0.4
VOL(8)
IOL=2.5mA
2.2 to 5.5
0.4
Pull-up
Rpu(1)
Ports 0, 1, 2, 7
resistance
Rpu(2)
Ports B, C
Hysteresis
VHYS
RES
voltage
Pin capacitance
VOH=0.9VDD
CP
All pins
4.5 to 5.5
15
35
80
2.2 to 5.5
18
50
150
2.2 to 5.5
Ports 1, 2, 7
μA
0.1
VDD
kΩ
V
For pins other than that under test:
VIN=VSS
f=1MHz
2.2 to 5.5
10
pF
Ta=25°C
No.A0125-14/23
LC875932A/24A/16A
Serial I/O Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter
Symbol
Pin/Remarks
Specification
Conditions
Input clock
VDD [V]
Frequency
tSCK(1)
Low level
tSCKL(1)
SCK0(P12)
See Fig. 6.
tSCKH(1)
pulse width
tSCKHA(1)
2.2 to 5.5
tCYC
4
Output clock
• (Note 4-1-2)
Frequency
tSCK(2)
Low level
tSCKL(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 6.
1/2
pulse width
High level
tSCK
tSCKH(2)
1/2
2.2 to 5.5
pulse width
tSCKHA(2)
• Continuous data
transmission/reception mode
tSCKH(2)
+2tCYC
• CMOS output selected
• See Fig. 6.
Data setup time
Serial input
unit
1
• Continuous data
transmission/reception mode
tsDI(1)
SI0(P11),
SB0(P11)
tSCKH(2)
+(10/3)
tCYC
tCYC
• Must be specified with respect
to rising edge of SIOCLK.
2.2 to 5.5
0.03
2.2 to 5.5
0.03
• See Fig. 6.
Data hold time
Output clock
Input clock
Output delay
Serial output
max
1
• See Fig. 6.
Serial clock
typ
2
pulse width
High level
min
thDI(1)
tdD0(1)
time
SO0(P10),
SB0(P11)
• Continuous data
transmission/reception mode
2.2 to 5.5
• (Note 4-1-3)
tdD0(2)
• Synchronous 8-bit mode
• (Note 4-1-3)
tdD0(3)
2.2 to 5.5
(1/3)tCYC
+0.05
μs
1tCYC
+0.05
(Note 4-1-3)
2.2 to 5.5
(1/3)tCYC
+0.15
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock
is "H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning
of output state change in open drain output mode. See Fig. 6.
No.A0125-15/23
LC875932A/24A/16A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter
Symbol
Pin/Remarks
Specification
Conditions
Input clock
Frequency
tSCK(3)
Low level
tSCKL(3)
SCK1(P15)
See Fig. 6.
Frequency
SCK1(P15)
• CMOS output selected
tSCKL(4)
1
2
2.2 to 5.5
pulse width
High level
1/2
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
SI1(P14),
SB1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
2.2 to 5.5
0.03
2.2 to 5.5
0.03
• See Fig. 6.
Data hold time
Output delay time
Serial output
tsDI(2)
unit
1
• See Fig. 6.
Low level
max
tCYC
tSCKH(3)
tSCK(4)
typ
2
2.2 to 5.5
pulse width
High level
min
pulse width
Output clock
Serial clock
VDD [V]
thDI(2)
tdD0(4)
SO1(P13),
SB1(P14)
μs
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the time
to the beginning of output state
2.2 to 5.5
change in open drain output
(1/3)tCYC
+0.05
mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0125-16/23
LC875932A/24A/16A
Pulse Input Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD [V]
High/low level
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P71),
• Event inputs for timer 0 or 1
INT2(P72),
are enabled.
min
typ
2.2 to 5.5
1
2.2 to 5.5
2
2.2 to 5.5
64
2.2 to 5.5
256
2.2 to 5.5
200
max
unit
INT4(P20 to P23),
INT5(P24 to P27)
tPIH(2)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(2)
noise filter time
• Event inputs for timer 0 are
constant is 1/1
tPIH(3)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(3)
noise filter time
• Event inputs for timer 0 are
constant is 1/32
enabled.
tPIH(4)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(4)
noise filter time
• Event inputs for timer 0 are
constant is 1/128
tPIL(5)
RES
tCYC
enabled.
enabled.
Resetting is enabled.
μs
AD Converter Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/Remarks
Specification
Conditions
VDD [V]
Resolution
N
AN0(P80) to
Absolute
ET
AN6(P86),
(Note 6-1)
accuracy
AN8(P70),
Conversion
AN9(P71),
AD conversion time=32 × tCYC
AN10(XT1),
(when ADCR2=0) (Note 6-2)
TCAD
time
typ
4.5 to 5.5
3.0 to 5.5
AD conversion time=64 × tCYC
(when ADCR2=1) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
VAIN
3.0 to 5.5
voltage range
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
max
unit
8
bit
±1.5
3.0 to 5.5
AN11(XT2)
Analog input
min
3.0 to 5.5
15.68
97.92
(tCYC=
(tCYC=
0.49μs)
3.06μs)
23.52
97.92
(tCYC=
(tCYC=
0.735μs)
3.06μs)
18.82
97.92
(tCYC=
(tCYC=
0.294μs)
1.53μs)
47.04
97.92
(tCYC=
(tCYC=
0.735μs)
1.53μs)
VSS
VDD
LSB
1
-1
μs
V
μA
Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued
till the time the complete digital value corresponding to the analog input value is loaded in the required
register.
No.A0125-17/23
LC875932A/24A/16A
Consumption Current Characteristics at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Normal mode
Symbol
IDDOP(1)
consumption
current
(Note 7-1)
IDDOP(2)
Pin/
Specification
Conditions
Remarks
VDD [V]
VDD1
=VDD2
• FmCF=12MHz ceramic oscillation mode
=VDD3
• System clock set to 12MHz side
min
typ
max
4.5 to 5.5
8
13.5
3.0 to 3.6
4.5
8.5
4.5 to 5.5
5.5
9
3.0 to 3.6
2.9
6.8
• 1/1 frequency division ratio
2.5 to 3.0
2.3
5.3
• FmCF=4MHz ceramic oscillation mode
4.5 to 5.5
2
3.2
3.0 to 3.6
0.95
2.3
2.2 to 3.0
0.66
1.8
4.5 to 5.5
0.55
2.1
3.0 to 3.6
0.29
1.3
• FmX’tal=32.768kHz crystal oscillation mode
• Internal RC oscillation stopped.
unit
• 1/1 frequency division ratio
IDDOP(3)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
IDDOP(4)
IDDOP(5)
IDDOP(6)
IDDOP(7)
IDDOP(8)
• System clock set to 8MHz side
• Internal RC oscillation stopped.
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal RC oscillation stopped.
• 1/2 frequency division ratio
IDDOP(9)
IDDOP(10)
mA
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
IDDOP(11)
• 1/2 frequency division ratio
2.2 to 3.0
0.2
0.96
IDDOP(12)
• FmCF=0Hz (oscillation stopped)
4.5 to 5.5
27
65
3.0 to 3.6
11
38
2.2 to 3.0
7.7
28
4.5 to 5.5
2.7
5.5
3.0 to 3.6
1.4
3
4.5 to 5.5
2
4.2
3.0 to 3.6
1.0
2.5
2.5 to 3.0
0.77
1.9
4.5 to 5.5
1
2.1
3.0 to 3.6
0.48
1.2
2.2 to 3.0
0.3
0.88
• FmX’tal=32.768kHz crystal oscillation mode
IDDOP(13)
IDDOP(14)
• System clock set to 32.768kHz side
• 1/2 frequency division ratio
HALT mode
IDDHALT(1)
HALT mode
consumption
• FmCF=12MHz ceramic oscillation mode
current
• FmX’tal=32.768kHz crystal oscillation mode
(Note 7-1)
IDDHALT(2)
µA
• Internal RC oscillation stopped.
• System clock set to 12MHz side
• Internal RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(3)
HALT mode
• FmCF=8MHz ceramic oscillation mode
IDDHALT(4)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz side
IDDHALT(5)
• Internal RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(6)
HALT mode
• FmCF=4MHz ceramic oscillation mode
IDDHALT(7)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
IDDHALT(8)
mA
• Internal RC oscillation stopped.
• 1/2 frequency division ratio
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.A0125-18/23
LC875932A/24A/16A
Continued from preceding page.
Parameter
Symbol
HALT mode
IDDHALT(9)
consumption
current
IDDHALT(10)
Pin/
VDD [V]
VDD1
=VDD2
HALT mode
=VDD3
• FmX’tal=32.768 kHz crystal oscillation mode
(Note 7-1)
3.0 to 3.6
0.17
0.73
2.2 to 3.0
0.12
0.56
4.5 to 5.5
19
50
3.0 to 3.6
7.6
26
2.2 to 3.0
4.7
18
HOLD mode
4.5 to 5.5
0.07
10
• CF1=VDD or open
3.0 to 3.6
0.04
8
2.2 to 3.0
0.03
6
IDDHALT(12)
HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 32.768kHz side
• 1/2 frequency division ratio
IDDHOLD(2)
current
VDD1
(External clock mode)
IDDHOLD(3)
Timer HOLD
IDDHOLD(4)
mode
VDD1
Timer HOLD mode
IDDHOLD(5)
• CF1=VDD or open
IDDHOLD(6)
• FmX’tal=32.768 kHz crystal oscillation mode
(External clock mode)
consumption
current
unit
mA
• Internal RC oscillation stopped.
IDDHALT(14)
IDDHOLD(1)
max
1
• 1/2 frequency division ratio
consumption
typ
0.28
IDDHALT(11)
HOLD mode
min
4.5 to 5.5
• FmCF=0Hz (oscillation stopped)
• System clock set to internal RC oscillation
IDDHALT(13)
Specification
Conditions
Remarks
4.5 to 5.5
16
45
3.0 to 3.6
6.3
22
2.2 to 3.0
3.8
15
µA
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
UART (Full Duplex) Operating Conditions at Ta = -30°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Symbol
Pin/remarks
Specification
Conditions
VDD [V]
Transfer rate
UBR
Data length :
Stop bits :
Parity bits :
P20, P21
2.2 to 5.5
min
typ
max
16/3
8192/3
unit
tCYC
7, 8, and 9 bits (LSB first)
1 bit (2-bit in continuous data transmission)
None
Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H)
Start bit
Start of
transmission
Stop bit
Transmit data (LSB first)
End of
transmission
UBR
Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H)
Stop bit
Start bit
Start of
reception
Receive data (LSB first)
End of
reception
UBR
No.A0125-19/23
LC875932A/24A/16A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a
SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values
with which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Vendor
Frequency
Name
12MHz
8MHz
4MHz
MURATA
MURATA
MURATA
Circuit Constant
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
Remarks
C1
C2
Rf1
Rd1
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[ms]
[ms]
CSTCE12M0G52-R0
(10)
(10)
Open
470
2.8 to 5.5
0.05
0.15
CSTCE8M00G52-R0
(10)
(10)
Open
2.2k
2.7 to 5.5
0.05
0.15
Internal
CSTLS8M00G53-B0
(15)
(15)
Open
680
2.5 to 5.5
0.05
0.15
C1, C2
Internal
C1, C2
CSTCR4M00G53-R0
(15)
(15)
Open
3.3k
2.2 to 5.5
0.05
0.15
Internal
CSTLS4M00G53-B0
(15)
(15)
Open
3.3k
2.2 to 5.5
0.05
0.15
C1, C2
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Figure 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Operating Voltage
Circuit Constant
Nominal
Vendor Name
Frequency
Oscillator Name
C3
C4
Rf2
Rd2
[pF]
[pF]
[Ω]
[Ω]
18
18
Open
560k
Range
[V]
Oscillation Stabilization
Time
typ
max
[s]
[s]
1.3
3.0
Remarks
Applicable
32.768kHz
SEIKO EPSON
MC-306
2.2 to 5.5
CL value
=12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note : The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
XT1
CF2
XT2
Rf2
Rf1
Rd2
Rd1
C1
C2
C3
C4
CF
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A0125-20/23
LC875932A/24A/16A
VDD
Operating VDD
lower limit
0V
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Reset
Unpredictable
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal
absent
HOLD reset signal valid
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A0125-21/23
LC875932A/24A/16A
VDD
RRES
Note :
Determine the value of CRES and RRES so that the
reset signal is present for a period of 200μs after the
supply voltage goes beyond the lower limit of the IC’s
operating voltage.
RES
CRES
Figure 5 Reset Circuit
SIOCLK :
DATAIN :
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DATAOUT :
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DI7
DI8
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKH
tSCKL
SIOCLK :
tsDI
thDI
DATAIN :
tdDO
DATAOUT :
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK :
tsDI
thDI
DATAIN :
tdDO
DATAOUT :
Figure 6 Serial I/O Output Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A0125-22/23
LC875932A/24A/16A
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to change without notice.
PS No.A0125-23/23