Ordering number : ENA1795 LC878496PB,LC8784C8PB LC8784G0PB,LC8784G1PB LC8784J2PB,LC8784J3PB LC8784M4PB,LC8784P6PB LC8784P7PB CMOS IC FROM 256K byte, RAM 12K byte on-chip 8-bit ETR Microcontroller Overview The LC8784XXPB series is an 8-bit ETR microcomputer that, centered around a CPU running at a minimum bus cycle time of 74.07 ns (CF = 13.5MHz), integrate on a single chip a number of hardware features such as direct control function of CD mechanism and CD-DSP for car audio, 256K-byte ROM (max), 12K-byte RAM (max), two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, two synchronous SIO ports (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports (full duplex), four 12-bit PWM channels, an 8-bit 10-channel AD converter, a high-speed clock counter, a system clock frequency divider, and a 29-source 10-vector interrupt feature. Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. Ver.1.07 20211HKPC 20100618-S00013, S00012, S00011, S00010, S00009, S00008, S00007, S00006, S00005 No.A1795-1/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB ROM for each model/Table RAM capacity Type No. ROM (byte) RAM (byte) LC878496PB 96K 6K LC8784C8PB 128K 6K LC8784G0PB 160K 6K LC8784G1PB 160K 8K LC8784J2PB 192K 8K 10K LC8784J3PB 192K LC8784M4PB 224K 10K LC8784P6PB 256K 10K LC8784P7PB 256K 12K Features ■Minimum Bus Cycle Time • 74.04ns (CF = 13.5MHz) Note: Bus cycle time indicates the speed to read ROM. ■Minimum Instruction Cycle Time (tCYC) • 222ns (CF = 13.5MHz) Note: The minimum instruction cycle time: Minimum bus cycle time × 3 ■Ports • Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1 bit units: 57 (P1n, P2n, P30 to P35, P70 to P73, P8n, PBn, PCn, SI2Pm, PWM0, PWM1, XT2, n=0 to 7, m=0 to 3) Ports whose I/O direction can be designated in 2 bit units: 16 (PEn, PFn n=0 to 7) Ports whose I/O direction can be designated in 4 bit units: 8 (P0n n=0 to 7) • Normal withstand voltage input ports: 1 (XT1) • Internal low voltage output ports: 1 (VREG) • Dedicated oscillator ports: 2 (CF1, CF2) • Reset pin: 1 (RES) • Digital power pins: 6 (VSSn, VDDn n=1, 2, 4) ■Timers • Timer 0: 16-bit programmable timer/counter with capture register Mode 0: 8-bit programmable timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2 channels Mode 1: 8-bit programmable timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit programmable counter (with two 8-bit capture registers) Mode 2: 16-bit programmable timer with an 8-bit programmable prescaler (with two 16-bit capture registers) Mode 3: 16-bit programmable counter (with 2 16-bit capture registers) • Timer 1: 16-bit programmable timer/counter that support PWM/ toggle output Mode 0: 8-bit programmable timer with an 8-bit prescaler (with toggle outputs) + 8-bit programmable timer/counter (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels Mode 2: 16-bit programmable timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also from the lower-order 8 bits) Mode 3: 16-bit programmable timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) • Timer 4: 8-bit programmable timer with a 6-bit prescaler • Timer 5: 8-bit programmable timer with a 6-bit prescaler • Timer 6: 8-bit programmable timer with a 6-bit prescaler (with toggle outputs) • Timer 7: 8-bit programmable timer with a 6-bit prescaler (with toggle outputs) • Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillator), cycle clock (tCYC), and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes. No.A1795-2/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB ■High Speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz) (When High-speed clock counter is used, timer 0 cannot be used). 2) Can generate output real time. ■SIO: 3 channels • SIO 0: 8 bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (4/3 to 512/3 tCYC transfer clock cycle) 3) Automatic continuous data transmission (1 to 256 bits) • SIO 1: 8 bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2 to or 3 to wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (Half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect) • SIO2: 8 bit synchronous serial interface 1) LSB first mode 2) Built-in 3-bit baudrate generator (4/3 to 512/3 tCYC transfer clock cycle) 3) Automatic continuous data transmission (1 to 32 bytes) ■UART: 2 channels 1) Full duplex 2) 7/8/9 bit data bits selectable 3) 1 stop bit (2 bits in continuous transmission mode) 4) Built-in 8-bit baudrate generator (with baudrates of 16/3 to 8192/3 tCYC) ■AD Converter: 8 bits × 10 channels ■PWM: Multifrequency 12-bit PWM × 4 channels ■Remote Control Receiver Noise Filtering Function (sharing pins with P73, INT3, and T0IN) 1) Noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC 2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an instruction, the signal level at that pin is read regardless of the availability of the noise filtering function. ■Watchdog Timer • External RC watchdog timer • Interrupt and reset signals selectable No.A1795-3/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB ■Interrupts • 29 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence. No. Vector Address Level 1 00003H X or L INT0 Interrupt Source 2 0000BH X or L INT1 3 00013H H or L INT2/T0L/INT4 4 0001BH H or L INT3/INT5/Base timer (BT0, 1) 5 00023H H or L T0H/INT6 6 0002BH H or L T1L/T1H/INT7 7 00033H H or L SIO0/UART1 receive/UART2 receive 8 0003BH H or L SIO1/SIO2/UART1 transmit/UART2 transmit 9 00043H H or L ADC/T6/T7/PWM4, PWM5 10 0004BH H or L Port 0/T4/T5/PWM0, PWM1 • Priority levels X > H > L • Of interrupts of the same level, the one with the smallest vector address takes precedence. • The Base timers are two interrupt sources of BT0 and BT1, it is one interrupt source by PWM0 and 1, it is one interrupt source by PWM4 and 5. ■Subroutine Stack Levels • 6144 levels maximum (1/2 of capacity of RAM, the stack is allocated in RAM.) ■High-speed Multiplication/Division Instructions • 16 bits × 8 bits • 24 bits × 16 bits • 16 bits ÷ 8 bits • 24 bits ÷ 16 bits (5 tCYC execution time) (12 tCYC execution time) (8 tCYC execution time) (12 tCYC execution time) ■Oscillation Circuits • RC oscillator circuit (internal): • CF oscillator circuit: • Crystal oscillator circuit: For system clock For system clock with internal Rf and external Rd For time-of-day clock, for low-speed system clock with internal Rf and external Rd • Multifrequency RC oscillator circuit (internal): For system clock ■System Clock Divider Function • Can run on low current. • The minimum instruction cycle selectable from 222ns, 444ns, 888ns, 1.78μs, 3.55μs, 7.10μs, 14.2μs, 28.4μs, and 56.8μs.(at a main clock of 13.5MHz) No.A1795-4/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB ■Standby Function • HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. 1) Oscillation is not halted automatically. 2) Canceled by system reset, detection VDET0 or occurrence of interrupt. • HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF oscillators, RC, and crystal oscillators automatically stop operation. 2) There are four ways of resetting the HOLD mode. (1) Setting the Reset pin to the lower level. (2) Voltage descent detection (VDET1) (3) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level. (4) Having an interrupt source established at port 0. • X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer. 1) The CF oscillators, and RC oscillators automatically stop operation. 2) The state of crystal oscillation established when X’tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the Reset pin to the low level. (2) Voltage descent detection (VDET0) (3) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level. (4) Having an interrupt source established at port 0. (5) Having an interrupt source established in the base timer circuit. ■Reset • External reset • Voltage descent detection (VDET0, VDET1) reset circuit (internal) ■Shipping Form • QIP100E (Lead Free Product) ■Flash ROM Version • LC87F83P7PB • LC87F83P7PBU (User writing) No.A1795-5/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Symbol Pins/Remarks Specification Conditions VDD[V] Maximum Supply VDD max VDD1, VDD2, VDD3, VDD4 Input voltage VI(1) CF1, XT1, Input/Output VIO(1) Ports 0, 1, 2 voltage voltage VDD1=VDD2=VDD3 =VDD4 min typ max -0.3 +6.5 -0.3 VDD+0.3 unit V Ports 3, 7, 8 Ports B, C, E, F -0.3 VDD+0.3 SI2P0 to SI2P3 PWM0, PWM1, XT2 Peak output IOPH(1) current Ports 0, 1, 2, 3 CMOS output select per 1 Ports 71 to 73 application pin Ports B, C, E, F -10 SI2P0 to SI2P3 IOPH(2) PWM0, PWM1 Per 1 application pin. IOMH(1) Ports 0, 1, 2, 3 CMOS output select per 1 output current Ports 71 to 73 application pin (Note 1-1) Ports B, C, E, F Average -20 -7.5 High level output current SI2P0 to SI2P3 IOMH(2) PWM0, PWM1 Per 1 application pin. -15 Total output ΣIOAH(1) P71 to P73 Total of all applicable pins -25 current ΣIOAH(2) PWM0, PWM1 Total of all applicable pins SI2P0 to SI2P3 ΣIOAH(3) Ports 0 Total of all applicable pins ΣIOAH(4) Port 0 Total of all applicable pins PWM0, PWM1 -25 mA -25 -45 SI2P0 to SI2P3 ΣIOAH(5) Ports 2, 3, B Total of all applicable pins ΣIOAH(6) Ports C Total of all applicable pins -25 ΣIOAH(7) Ports 2, 3, B, C Total of all applicable pins -45 ΣIOAH(8) Ports F Total of all applicable pins -25 ΣIOAH(9) Ports 1, E Total of all applicable pins -25 ΣIOAH(10) Ports 1, E, F Total of all applicable pins -45 -25 Note 1-1: Average output current is average of current in 100ms interval. Continued on next page. No.A1795-6/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Continued from preceding page. Parameter Symbol Pins/Remarks Specification Conditions VDD[V] Peak output IOPL(1) current Ports 0, 1, 2, 3, 8 min typ max unit Per 1 application pin. Ports B, C, E, F 10 SI2P0 to SI2P3 XT2 Average IOPL(2) PWM0, PWM1 Per 1 application pin. IOML(1) Ports 0, 1, 2, 3, 7 Per 1 application pin. output current Ports 8, B, C, E, F (Note 1-1) SI2P0 to SI2P3 20 7.5 Low level output current XT2 IOML(2) PWM0, PWM1 Per 1 application pin. 20 Total output ΣIOAL(1) Port 7, XT2 Total of all applicable pins 25 current ΣIOAL(2) Port 8 Total of all applicable pins 25 45 ΣIOAL(3) Ports 7, 8, XT2 Total of all applicable pins ΣIOAL(4) PWM0, PWM1 Total of all applicable pins ΣIOAL(5) Port 0 Total of all applicable pins ΣIOAL(6) Port 0 Total of all applicable pins mA 25 SI2P0 to SI2P3 25 45 PWM0, PWM1 SI2P0 to SI2P3 Maximum power ΣIOAL(7) Ports 2, 3, B Total of all applicable pins 25 ΣIOAL(8) Ports C Total of all applicable pins 25 ΣIOAL(9) Ports 2, 3, B, C Total of all applicable pins 45 ΣIOAL(10) Port F Total of all applicable pins 25 ΣIOAL(11) Ports 1, E Total of all applicable pins 25 ΣIOAL(12) Ports 1, E, F Total of all applicable pins 45 Pd max QIP100E Ta = -40 to +85°C 400 mW -40 +85 °C -45 +125 °C consumption Operating Topr temperature range Storage Tstg temperature range Note 1-1: Average output current is average of current in 100ms interval. No.A1795-7/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Recommended operating range at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Symbol Pins/Remarks Specification Conditions VDD[V] Operating VDD(1) VDD1=VDD2=VDD3 =VDD4 CPU operation VHD VDD1=VDD2=VDD3 RAM and register contents in HOLD mode. VIH(1) =VDD4 Ports 1, 2 supply voltage Memory sustaining supply voltage High level input voltage SI2P0 to 3 P71 to P73 3.0 to 5.5 P70 port input/ min typ max 3.0 5.5 1.0 5.5 0.35VDD unit VDD +0.7 interrupt side VIH(2) Ports 0, 3, 8 3.0 to 5.5 Ports B, C, E, F +0.7 VDD 3.0 to 5.5 0.9VDD VDD 3.0 to 5.5 0.75VDD VDD 4.0 to 5.5 VSS 3.0 to 4.0 VSS 4.0 to 5.5 VSS 3.0 to 4.0 VSS 3.0 to 5.5 VSS 3.0 to 5.5 VSS 3.0 to 5.5 0.222 PWM0, PWM1 VIH(3) Port70 Watchdog timer side VIH(4) XT1, XT2, RES VIL(1) Ports 1, 2 When XT1 and XT2 general purpose input Low level input voltage SI2P0 to 3 VIL(2) 0.3VDD V 0.1VDD +0.4 P71 to P73 P70 port input/ 0.2VDD interrupt side VIL(3) Ports 0, 3, 8 Ports B, C, E, F VIL(4) PWM0, PWM1 VIL(5) Port70 Watchdog timer side VIL(6) XT1, XT2, RES When XT1 and XT2 general purpose input Instruction cycle tCYC time (Note 2-1) Oscillation FmCF frequency range FmRC CF1, CF2 FmMRC CF oscillation. 3.0 to 5.5 4 Internal RC oscillation 3.0 to 5.5 0.3 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 0.25VDD μs 13.5 1.0 MHz Frequency variable RC oscillation source 2.0 3.0 to 5.5 16 3.0 to 5.5 32.768 oscillation FsX’tal XT1, XT2 32.768kHz crystal oscillation. kHz Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. No.A1795-8/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Symbol Pins/Remarks Specification Conditions VDD[V] High level input IIH(1) curre Ports 0, 1, 2 Output disable Ports 3, 7, 8 Pull-up resistor OFF Ports B, C, E, F VIN=VDD (including the off-leak current of SI2P0 to SI2P3 RES min typ max unit 3.0 to 5.5 1 3.0 to 5.5 1 the output Tr.) PWM0, PWM1 IIH(2) Low level input XT1, XT2 Using as an input port IIH(3) CF1 VIN=VDD VIN=VDD IIL(1) Ports 0, 1, 2 Output disable Ports 3, 7, 8 Pull-up resistor OFF Ports B, C, E, F VIN=VDD (including the off-leak current of current SI2P0 to SI2P3 RES 3.0 to 5.5 1 3.0 to 5.5 -1 3.0 to 5.5 -1 3.0 to 5.5 -15 4.5 to 5.5 VDD-1 IOH=-0.4mA 3.0 to 5.5 VDD-0.4 5 15 -5 -1 μA the output Tr.) PWM0, PWM1 IIL(2) High level output XT1, XT2 Using as an input port IIL(3) CF1 VIN=VSS VIN=VSS VOH(1) Ports 0, 1, 2, 3 IOH=-1.0mA voltage Ports B, C, E, F VOH(2) Ports 71, 72, 73 SI2P0 to SI2P3 VOH(3) PWM0, PWM1 IOH=-10mA 4.5 to 5.5 VDD-1.5 VOH(4) P30, P31(PWM4, IOH=-1.6mA 3.0 to 5.5 VDD-0.4 5 output mode) Low level output VOL(1) voltage Ports 0, 1, 2, 3 IOL=1.0mA 1.0 3.0 to 5.5 0.4 IOL=10mA 4.5 to 5.5 1.5 IOL=1.6mA 3.0 to 5.5 0.4 0.4 Ports B, C, E, F VOL(2) Ports 71, 72, 73 IOL=0.4mA SI2P0 to SI2P3 VOL(3) PWM0, PWM1 VOL(4) Pull-up resistation VOL(5) Ports 70, 8, XT2 IOL=1.6mA 3.0 to 5.5 Rpu(1) Ports 0, 1, 2, 3 VOH=0.9VDD 4.5 to 5.5 15 35 80 Rpu(2) Port 7 3.0 to 5.5 15 35 150 kΩ Ports B, C, E, F Hysteresis voltage V 4.5 to 5.5 VHYS RES Ports 1, 2, 7 3.0 to 5.5 0.1VDD V 3.0 to 5.5 10 pF SI2P0 to SI2P3 Pin capacitance CP All pins • For pins other than that under test: VIN=VSS • f=1MHz • Ta=25°C Power down VDET0 detection voltage VDET1 VDD1 • Excluding the HOLD mode 3.0 3.3 3.6 • HOLD mode 1.1 1.6 2.1 V No.A1795-9/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V 1. SIO0 Serial I/O Characteristics (Note 4-1-1) Parameter Symbol Frequency tSCK(1) Low level tSCKL(1) Pins/ SCK0(P12) Specification Conditions Remarks VDD[V] • See Fig. 2. max unit 1 tSCKH(1) 1 pulse width tSCKHA(1a) Input clock typ 2 pulse width High level min • Continuous data transmission/reception mode • SIO2 is not in use simultaneous. 3.0 to 5.5 4 tCYC • See Fig. 2. • (Note 4-1-2) tSCKHA(1b) • Continuous data transmission/reception mode • SIO2 is in use simultaneous. 6 Serial clock • See Fig. 2. • (Note 4-1-2) Frequency tSCK(2) SCK0(P12) • CMOS output selected. 4/3 • See Fig. 2. Low level tSCKL(2) 1/2 pulse width High level tSCK tSCKH(2) 1/2 Output clock pulse width tSCKHA(2a) • Continuous data transmission/reception mode • SIO2 is not in use simultaneous. 3.0 to 5.5 • CMOS output selected. tSCKH(2) tSCKH(2) +2tCYC +(10/3)tCYC • See Fig. 2. tSCKHA(2b) tCYC • Continuous data transmission/reception mode • SIO2 is in use simultaneous. • CMOS output selected. tSCKH(2) tSCKH(2) +2tCYC +(16/3)tCYC • See Fig. 2. Serial input Data setup time SI0(P11), SB0(P11) • Must be specified with respect to Data hold time 0.03 rising edge of SIOCLK • See fig. 2. thDI(1) 3.0 to 5.5 0.03 Input clock Output tdD0(1) delay time SI0(P11), SB0(P11) • Continuous data (1/3)tCYC transmission/reception mode +0.05 • (Note 4-1-3) tdD0(2) • Synchronous 8-bit mode. • (Note 4-1-3) Output clock Serial output tsDI(1) tdD0(3) • (Note 4-1-3) μs 1tCYC 3.0 to 5.5 +0.05 (1/3)tCYC +0.05 Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 2. No.A1795-10/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB 2. SIO1 Serial I/O Characteristics (Note 4-2-1) Input clock Symbol Frequency tSCK(3) Low level tSCKL(3) Pins/ SCK1(P15) VDD[V] min • See Fig. 2. Frequency tCYC SCK1(P15) • CMOS output selected. tSCKL(4) 2 3.0 to 5.5 pulse width High level 1/2 tSCK tSCKH(4) 1/2 pulse width Serial input Data setup time SI1(P14), SB1(P14) • Must be specified with respect to Data hold time 0.03 rising edge of SIOCLK • See fig. 2. thDI(2) 3.0 to 5.5 0.03 Output Serial output tsDI(2) unit 1 • See Fig. 2. Low level max 1 tSCKH(3) tSCK(4) typ 2 3.0 to 5.5 pulse width High level Specification Conditions Remarks pulse width Output clock Serial clock Parameter delay time tdD0(4) SO1(P13), SB1(P14) μs • Must be specified with respect to falling edge of SIOCLK • Must be specified as the time to the beginning of output state 3.0 to 5.5 change in open drain output (1/3)tCYC +0.05 mode. • See Fig. 2. Note 4-2-1: These specifications are theoretical values. Add margin depending on its use. No.A1795-11/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB 3. SIO2 Serial I/O Characteristics (Note 4-3-1) Parameter Frequency Symbol tSCK(5) Pins/ SCK2 Specification Conditions Remarks VDD[V] • See Fig. 2. tSCKL(5) tSCKH(5) unit 1 pulse width tSCKHA(5a) Input clock max 1 pulse width High level typ 2 (SI2P2) Low level min • Continuous data transmission/reception mode of SIO0 is not in use simultaneous. 3.0 to 5.5 4 tCYC • See Fig. 2. • (Note 4-3-2) tSCKHA(5b) • Continuous data transmission/reception mode of SIO0 is in use simultaneous. 7 Serial clock • See Fig. 2. • (Note 4-3-2) Frequency Low level tSCK(6) tSCKL(6) • CMOS output selected. (SI2P2) • See Fig. 2. 4/3 SCK2O 1/2 (SI2P3) pulse width High level SCK2 tSCK tSCKH(6) 1/2 Output clock pulse width tSCKHA(6a) • Continuous data transmission/reception mode of SIO0 is not in use simultaneous. 3.0 to 5.5 • CMOS output selected. tSCKH(6) tSCKH(6) +(5/3)tCYC +(10/3)tCYC • See Fig. 2. tSCKHA(6b) tCYC • Continuous data transmission/reception mode of SIO0 is in use simultaneous. • CMOS output selected. tSCKH(6) tSCKH(6) +(5/3)tCYC +(19/3)tCYC • See Fig. 2. Serial input Data setup time SI2(SI2P1), SB2(SI2P1) • Must be specified with respect to Data hold time 0.03 rising edge of SIOCLK • See fig. 2. thDI(3) 3.0 to 5.5 0.03 Output delay Serial output tsDI(3) time tdD0(5) SO2(SI2P0), SB2(SI2P1) μs • Must be specified with respect to falling edge of SIOCLK • Must be specified as the time to the beginning of output state change in open drain output 3.0 to 5.5 (1/3)tCYC +0.05 mode. • See Fig. 2. Note 4-3-1: These specifications are theoretical values. Add margin depending on its use. Note 4-3-2: To use serial-clock-input, a time from SI2RUN being set when serial clock is "H" to the first negative edge of the serial clock must be longer than tSCKHA. No.A1795-12/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Symbol Pins/Remarks Specification Conditions VDD[V] High/low level tPIH(1) INT0(P70), • Interrupt source flag can be set. pulse wid tPIL(1) INT1(P71), • Event inputs for timer 0 or 1 are min typ max unit enabled. INT2(P72), INT4(P20 to P23), 3.0 to 5.5 1 3.0 to 5.5 2 3.0 to 5.5 64 3.0 to 5.5 256 3.0 to 5.5 200 INT5(P24 to P27), INT6(P20), INT7(P24) tPIH(2) INT3(P73) when noise • Interrupt source flag can be set. tPIL(2) filter time constant is 1/1. • Event inputs for timer 0 are tPIH(3) INT3(P73) • Interrupt source flag can be set. tPIL(3) (The noise rejection clock • Event inputs for timer 0 are tCYC enabled. is selected to 1/32.) enabled. tPIH(4) INT3(P73) • Interrupt source flag can be set. tPIL(4) (The noise rejection clock • Event inputs for timer 0 are is selected to 1/128.) tPIL(5) RES enabled. • Reset acceptable * See Fig. below μs VDD RES Internal regulator stabilization time must be 10ms (max.) or more. Figure Power-on Time Reset Timing AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Symbol Pins/Remarks Specification Conditions VDD[V] Resolution N AN0(P80) Absolute precision ET to AN7(P87) Conversion time TCAD AN8(P70) AN9(P71) (Note 6-1) AD conversion time=32×tCYC (when ADCR2=0) (Note 6-2) AD conversion time=64×tCYC (when ADCR2=1) (Note 6-2) Analog input min typ 3.0 to 5.5 VAIN 3.0 to 5.5 3.0 to 5.5 voltage range Analog port IAINH VAIN=VDD 3.0 to 5.5 input current IAINL VAIN=VSS 3.0 to 5.5 unit bit ±1.5 3.0 to 5.5 3.0 to 5.5 max 8 LSB 7.104(tCYC= 0.222μs) μs 14.21(tCYC= 0.222μs) VSS VDD 1 -1 V μA Note 6-1: The quantization error (±1/2 LSB) is excluded from the absolute accuracy value. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the complete digital value corresponding to the analog input value is loaded in the required register. No.A1795-13/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Normal mode Symbol IDDOP(1) consumption current (Note 7-1) IDDOP(2) Pins/ VDD1 =VDD2 =VDD3 =VDD4 Specification Conditions Remarks VDD[V] min typ max unit • FmCF=13.5MHz oscillation mode • FmX’tal=32.768kHz by crystal oscillation 4.5 to 5.5 8.0 10.0 3.0 to 4.5 6.0 8.0 4.5 to 5.5 5.0 6.0 3.0 to 4.5 4.0 5.0 4.5 to 5.5 3.0 4.0 mode • System clock set to 13.5MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. IDDOP(3) • FmCF=8MHz oscillation mode • FmX’tal=32.768kHz by crystal oscillation mode IDDOP(4) • System clock set to 8MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. IDDOP(5) • FmCF=4MHz oscillation mode • FmX’tal=32.768kHz by crystal oscillation mode mA • System clock set to 4MHz side IDDOP(6) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped 3.0 to 4.5 2.4 3.0 4.5 to 5.5 0.8 1.2 3.0 to 4.5 0.6 1.0 4.5 to 5.5 0.8 2.0 3.0 to 4.5 0.5 1.5 4.5 to 5.5 300 500 • 1/1 frequency division ratio. IDDOP(7) • FmCF=0Hz (oscillation stopped) • FmX'al=32.768kHz by crystal oscillation mode. IDDOP(8) • System clock set to internal RC oscillation • Frequency variable RC oscillation stopped • 1/2 frequency division ratio. IDDOP(9) • FmCF=0Hz (oscillation stopped) • FmX'al=32.768kHz by crystal oscillation mode. • Internal RC oscillation stopped IDDOP(10) • System clock set to 1MHz with frequency variable RC oscillation • 1/2 frequency division ratio. IDDOP(11) • FmCF=0Hz (oscillation stopped) • FmX'al=32.768kHz by crystal oscillation mode. μA • System clock set to 32.768kHz side. IDDOP(12) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped 3.0 to 4.5 250 450 • 1/2 frequency division ratio. Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. General-purpose I/O port "L" output when the above-mentioned data is measured However, the P0 port is an input setting because of the mode setting Continued on next page. No.A1795-14/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Continued from preceding page. Parameter HALT mode Symbol IDDHALT(1) consumption current (Note 7-1) Pins/ Specification Conditions Remarks VDD[V] VDD1 =VDD2 • HALT mode =VDD3 =VDD4 • FmX’tal=32.768kHz by crystal oscillation • FmCF=13.5MHz oscillation mode min typ max 4.5 to 5.5 2.0 3.0 3.0 to 4.5 1.8 2.5 4.5 to 5.5 1.2 1.8 3.0 to 4.5 1.0 1.5 4.5 to 5.5 0.6 0.9 unit mode • System clock set to 13.5MHz side IDDHALT(2) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. • HALT mode IDDHALT(3) • FmCF=8MHz oscillation mode • FmX’tal=32.768kHz by crystal oscillation mode IDDHALT(4) • System clock set to 8MHz side • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. • HALT mode IDDHALT(5) • FmCF=4MHz oscillation mode • FmX’tal=32.768kHz by crystal oscillation mode mA • System clock set to 4MHz side IDDHALT(6) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped 3.0 to 4.5 0.5 0.7 4.5 to 5.5 0.5 1.0 3.0 to 4.5 0.3 0.8 4.5 to 5.5 1.0 2.0 3.0 to 4.5 0.8 1.5 4.5 to 5.5 250 500 3.0 to 4.5 200 400 • 1/1 frequency division ratio. • HALT mode IDDHALT(7) • FmCF=0Hz (oscillation stopped) • FmX’tal=32.768kHz by crystal oscillation mode IDDHALT(8) • System clock set to internal RC oscillation • Frequency variable RC oscillation stopped • 1/2 frequency division ratio. IDDHALT(9) • HALT mode • FmCF=0Hz (oscillation stopped) • FmX'al=32.768kHz by crystal oscillation mode. • Internal RC oscillation stopped IDDHALT(10) • System clock set to 1MHz with frequency variable RC oscillation • 1/2 frequency division ratio. • HALT mode IDDHALT(11) • FmCF=0Hz (oscillation stopped) • FmX'al=32.768kHz by crystal oscillation mode. • System clock set to 32.768kHz side. IDDHALT(12) • Internal RC oscillation stopped • Frequency variable RC oscillation stopped • 1/2 frequency division ratio. Current drain during HOLD mode Current drain IDDHOLD(1) HOLD mode • HOLD mode IDDHOLD(2) IDDHOLD(3) during timebase clock VDD1 VDD1 • Timer HOLD mode • FmX'tal=32.768kHz by crystal oscillation IDDHOLD(4) μA 4.5 to 5.5 1.5 20.0 3.0 to 4.5 1.0 18.0 4.5 to 5.5 150 300 3.0 to 4.5 100 200 mode Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. General-purpose I/O port "L" output when the above-mentioned data is measured However, the P0 port is an input setting because of the mode setting Continued on next page. No.A1795-15/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Continued from preceding page. Parameter Pins/ Symbol Current drain IDDCLOCK(1) during Intermittent for clock mode Specification Conditions Remarks VDD[V] VDD1 =VDD2 • Intermittent for clock mode =VDD3 =VDD4 and 20 steps are executed. min typ max • Each 500ms is shifted to a normal mode, 4.5 to 5.5 250 500 • FmCF=0Hz (oscillation stopped) • FmX'al=32.768kHz by crystal oscillation μA mode. IDDCLOCK(2) unit • System clock set to 32.768kHz side. • Internal RC oscillation stopped 3.0 to 4.5 200 400 • Frequency variable RC oscillation stopped • 1/1 frequency division ratio. Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors. General-purpose I/O port "L" output when the above-mentioned data is measured However, the P0 port is an input setting because of the mode setting UART(Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V Parameter Clock rate Pins/ Symbol UBR, UBR2 Remarks Specification Conditions VDD[V] min typ max unit 8192/3 tCYC UTX1(P32), RTX1(P33), 3.0 to 5.5 UTX2(P33), 16/3 RTX2(P34) Data length: 7, 8, and 9 bits ( LSB first ) Stop bits: 1 bit (2-bit in continuous data transmission) Parity bits: Non Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H) Start bit Start of transmission Stop bit End of transmission Transmit data (LSB first) UBR, UBR2 Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H) Start bit Start of reception Stop bit Received data (LSB first) End of reception UBR, UBR2 No.A1795-16/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Package Dimensions unit : mm (typ) 3151A 23.2 0.8 20.0 51 50 100 31 14.0 81 1 17.2 80 30 0.65 0.3 0.15 0.1 3.0max (2.7) (0.58) SANYO : QIP100E(14X20) No.A1795-17/29 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PC6/DBGP1 PC7/DBGP2 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN/T0LCP P73/INT3/T0IN/T0HCP RES XT1 XT2 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1 P13/SO1 P12/SCK0 P11/SI0/SB0 P10/SO0 P87/AN7 P86/AN6 P85/AN5 P84/AN4 P83/AN3 P82/AN2 P81/AN1 P80/AN0 VDD1 CF2 CF1 VSS1 1 PC5/DBGP0 SI2P2/SCK2 SI2P3/SCK2O PWM1 PWM0 VDD2 VSS2 P00 P01 P02 P03 P04 P05/CKO P06/T6O P07/T7O P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1 P21/INT4/T1IN/T0LCP/T0HCP P22/INT4/T1IN/T0LCP/T0HCP P23/INT4/T1IN/T0LCP/T0HCP P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1 P25/INT5/T1IN/T0LCP/T0HCP P26/INT5/T1IN/T0LCP/T0HCP P27/INT5/T1IN/T0LCP/T0HCP P30/PWM4 P31/PWM5 P32/UTX1 P33/URX1 P34/UTX2 P35/URX2 PB7 PB6 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Pin Assignment 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PB5 81 50 SI2P1/SI2/SB2 PB4 82 49 SI2P0/SO2 PB3 83 48 PF7 PB2 84 47 PF6 PB1 85 46 PF5 PB0 86 45 PF4 VREG 87 44 PF3 VSS3 88 43 PF2 VDD3 89 42 PF1 NC 90 41 PF0 NC 91 40 VDD4 NC 92 39 VSS4 NC 93 38 PE7 NC 94 37 PE6 NC 95 36 PE5 PC0 96 35 PE4 PC1 97 34 PE3 PC2 98 33 PE2 PC3 99 32 PE1 PC4 100 31 PE0 LC878496PB,LC8784C8PB LC8784G0PB,LC8784G1PB LC8784J2PB,LC8784J3PB LC8784M4PB,LC8784P6PB LC8784P7PB Top view SANYO: QIP100E (14×20) “Lead Free Product” No.A1795-18/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB PIN No. NAME PIN No. NAME 1 PC5/DBGP0 51 SI2P2/SCK2 2 PC6/DBGP1 52 SI2P3/SCK2O 3 PC7/DBGP2 53 PWM1 4 P70/INT0/T0LCP/AN8 54 PWM0 5 P71/INT1/T0HCP/AN9 55 VDD2 6 P72/INT2/T0IN/T0LCP 56 VSS2 7 P73/INT3/T0IN/T0HCP 57 P00 8 RES 58 P01 9 XT1 59 P02 10 XT2 60 P03 11 VSS1 61 P04 12 CF1 62 P05/CKO 13 CF2 63 P06/T6O 14 VDD1 64 P07/T7O 15 P80/AN0 65 P20/INT4/T1IN/T0LCP/T0HCP/INT6/T0LCP1 16 P81/AN1 66 P21/INT4/T1IN/T0LCP/T0HCP 17 P82/AN2 67 P22/INT4/T1IN/T0LCP/T0HCP 18 P83/AN3 68 P23/INT4/T1IN/T0LCP/T0HCP 19 P84/AN4 69 P24/INT5/T1IN/T0LCP/T0HCP/INT7/T0HCP1 20 P85/AN5 70 P25/INT5/T1IN/T0LCP/T0HCP 21 P86/AN6 71 P26/INT5/T1IN/T0LCP/T0HCP 22 P87/AN7 72 P27/INT5/T1IN/T0LCP/T0HCP 23 P10/SO0 73 P30/PWM4 24 P11/SI0/SB0 74 P31/PWM5 25 P12/SCK0 75 P32/UTX1 26 P13/SO1 76 P33/URX1 27 P14/SI1/SB1 77 P34/UTX2 28 P15/SCK1 78 P35/URX2 29 P16/T1PWML 79 PB7 30 P17/T1PWMH/BUZ 80 PB6 31 PE0 81 PB5 32 PE1 82 PB4 33 PE2 83 PB3 34 PE3 84 PB2 35 PE4 85 PB1 36 PE5 86 PB0 37 PE6 87 VREG 38 PE7 88 VSS3 39 VSS4 89 VDD3 40 VDD4 90 NC 41 PF0 91 NC 42 PF1 92 NC 43 PF2 93 NC 44 PF3 94 NC 45 PF4 95 NC 46 PF5 96 PC0 47 PF6 97 PC1 48 PF7 98 PC2 49 SI2P0/SO2 99 PC3 50 SI2P1/SI2/SB2 100 PC4 No.A1795-19/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB System Block Diagram CF1 CF2 CF Clock X'tal XT2 generator RC XT1 Interrupt control MRC Bus Interface Standby control Timer 0 IR RES PLA Timer 1 ROM Timer 4 VREG Regulator Timer 5 PC VDD Port 0 VSS Port 1 SIO0 ACC Port 3 B register Port 7 C register Port 8 ALU SIO1 ADC SIO2 INT0 to 3 noise rejection filter PSW PWM0 Port 2 INT4, 5, 6, 7 RAR PWM1 Port B RAM Base Timer Port C Stack pointer Timer 6 Port E Watchdog timer Timer 7 Port F UART1 PWM4 VREG operation UART2 PWM5 VDD operation No.A1795-20/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Pin Description Pin No. I/O VSS1 VSS2 Name 11 - VSS3 VSS4 88 VDD1 VDD2 14 VDD3 VDD4 89 Function Description Option • Power supply pin No • Connect it with GND 56 39 - • Power supply pin No • Connect it with VDD 55 40 I/O Port 0 • 8-bit I/O port Yes P00 57 • I/O specifiable in 4-bit units P01 58 • Pull-up resistor can be turned on and off in 4-bit units P02 59 • HOLD release input P03 60 • Port 0 interrupt input P04 61 • Pin functions P05 62 P05: System clock output P06 63 P06: Timer 6 toggle output P07 64 P07: Timer 7 toggle output I/O Port 1 • 8-bit I/O port Yes P10 23 • I/O specifiable in 1-bit units P11 24 • Pull-up resistor can be turned on and off in 1-bit units P12 25 • Pin functions P13 26 P10: SIO0 data output P14 27 P11: SIO0 data input, bus I/O P15 28 P12: SIO0 clock I/O P16 29 P13: SIO1 data output P17 30 P14: SIO1 data input, bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output P17: Timer 1 PWMH output, beeper output I/O Port 2 • 8-bit I/O port Yes P20 65 • I/O specifiable in 1-bit units P21 66 • Pull-up resistor can be turned on and off in 1-bit units P22 67 • Other functions P23 68 P24 69 P25 70 P26 71 P27 72 P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input/INT6 input/timer 0L capture 1 input P21 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/ timer 0H capture input/INT7 input/timer 0H capture 1 input P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer0L capture input/ timer 0H capture input Interrupt acknowledge type • Interrupt acknowledge type I/O Port 3 Rising Falling INT4 enable enable INT5 enable enable INT6 enable INT7 enable Rising/ H level L level enable disable disable enable disable disable enable enable disable disable enable enable disable disable Falling • 6-bit I/O port P30 73 • I/O specifiable in 1-bit units P31 74 • Pull-up resistor can be turned on and off in 1-bit units P32 75 • Pin functions P33 76 P30: PWM4 output P34 77 P31: PWM5 output P35 78 P32: UART1 transmit Yes P33: UART1 receive P34: UART2 transmit P35: UART2 receive Continued on next page. No.A1795-21/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Continued from preceding page. Name Pin No. I/O I/O Port 7 Function Description Option • 4-bit I/O port No P70 4 • I/O specifiable in 1-bit units P71 5 • Pull-up resistor can be turned on and off in 1-bit units P72 6 • Other functions P73 7 P70: INT0 input/HOLD release input/Timer 0L capture input/Output for watchdog timer/ AD converter input port P71: INT1 input/HOLD release input/Timer 0H capture input/ AD converter input port P72: INT2 input/HOLD release input/Timer 0 event input/timer0L capture input P73: INT3 input with noise filter/Timer 0 event input/timer 0H capture input • Interrupt acknowledge type Port 8 I/O Rising Falling INT0 enable enable INT1 enable enable INT2 enable INT3 enable H level L level disable enable enable disable enable enable enable enable disable disable enable enable disable disable Falling • 8-bit I/O port (Output: N-channel open drain) P80 15 • I/O specifiable in 1-bit units P81 16 • Other functions P82 17 P83 18 P84 19 P85 20 P86 21 P87 22 • 8-bit I/O port PB0 86 • I/O specifiable in 1-bit units PB1 85 • Pull-up resistor can be turned on and off in 1-bit units PB2 84 PB3 83 PB4 82 PB5 81 PB6 80 PB7 79 Port C I/O • 8-bit I/O port PC0 96 • I/O specifiable in 1-bit units PC1 97 • Pull-up resistor can be turned on and off in 1-bit units PC2 98 PC3 99 PC4 100 PC5 1 PC6 2 PC7 3 I/O Port E • 8-bit I/O port PE0 31 • I/O specifiable in 2-bit units PE1 32 • Pull-up resistor can be turned on and off in 1-bit units PE2 33 PE3 34 PE4 35 PE5 36 PE6 37 PE7 38 Port F No P80 to P87: AD converter input port I/O Port B Rising/ I/O • 8-bit I/O port PF0 41 • I/O specifiable in 2-bit units PF1 42 • Pull-up resistor can be turned on and off in 1-bit units PF2 43 PF3 44 PF4 45 PF5 46 PF6 47 PF7 48 Yes Yes No No Continued on next page. No.A1795-22/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Continued from preceding page. Name Pin No. I/O I/O SIO2 Function Description • 4-bit I/O port SI2P0 49 • I/O specifiable in 1-bit units SI2P1 50 • Shared functions: SI2P2 51 SI2P0: SIO2 data output SI2P3 52 SI2P1: SIO2 data input, bus input/output Option No SI2P2: SIO2 clock input/output SI2P3: SIO2 clock output PWM0 54 I/O • PWM0 output port No • General-purpose I/O available PWM1 53 I/O • PWM1 output port No • General-purpose I/O available RES 8 I • Reset pin No Must connect it with VDD1 through RC (Refer to Page27 Figure 1) XT1 9 I • Input terminal for 32.768kHz X'tal oscillation No • Shared functions: General-purpose input port Must be set for input with software and connected to VSS1 if not to be used. XT2 10 I/O • Output terminal for 32.768kHz X'tal oscillation No • Shared functions: General-purpose I/O port Must be set for general-purpose output and kept open if not to be used. Please connect suitable dumping resistance for the crystal used between the terminal when you use it as Output terminal for 32.768kHz X'tal oscillation. CF1 12 I • Input terminal for oscillation No CF2 13 O • Output terminal for oscillation No NC 90 - • Please open the terminal No NC 91 - • Please open the terminal No NC 92 - • Please open the terminal No NC 93 - • Please open the terminal No NC 94 - • Please open the terminal No NC 95 - • Please open the terminal No VREG 87 O • Internal low voltage output No • Connect a bypass capacitor to this pin. (Refer to Page27) No.A1795-23/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Port Output Types The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode. Port Options Selected in Units of Option Type P00 to P07 1 bit 1 P10 to P17 1 bit Output Type Pull-up Resistor CMOS Programmable (Note 1) 2 N-channel open drain No 1 CMOS Programmable 2 N-channel open drain Programmable 1 bit 1 CMOS Programmable 2 N-channel open drain Programmable - No CMOS Programmable P20 to P27 P30 to P35 PB0 to PB7 PC0 to PC7 PE0 to PE7 PF0 to PF7 P70 - No N-channel open drain Programmable P71 to P73 - No CMOS Programmable P80 to P87 - No N-channel open drain No SI2P0, SI2P2, - No CMOS No - No CMOS (when selected as ordinary port) No SI2P3 PWM0, PWM1 SI2P1 N-channel open drain (When SIO2 data is selected) XT1 - No XT2 - No Input only No Output for 32.768kHz quartz oscillator No N-channel open drain (when in general-purpose output mode) Note 1: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07). *1: Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time. Be sure to electrically short the VSS1, VSS2, AVSS and VSS4 pins. Example 1: When backup is active in the HOLD mode, the high level of the port outputs is supplied by the backup capacitors. Back-up capacitor LSI VDD1 Power Supply VDD2 VDD3 VDD4 VREG VSS1 VSS2 VSS3 VSS4 No.A1795-24/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB Example 2: The high level output at the ports is unstable when the HOLD mode.backup is in effect. Back-up capacitor LSI VDD1 Power supply VDD2 VDD3 VDD4 VREG VSS1 VSS2 VSS3 VSS4 No.A1795-25/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB VDD1, VSS1 Terminal condition It is necessary to place capacitors between VDD1 and VSS1 as describe below. • Place capacitors as close to VDD1 and VSS1 as possible. • Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1’, L2 = L2’). • Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel. • Capacitance of C2 must be more than 0.1μF. • Please mount a suitable capacitor about C1. • Use thicker pattern for VDD1 and VSS1. L2 L1 VSS1 C1 C2 VDD1 L1’ L2’ VREG, VSS3 Terminal condition It is necessary to place capacitors between VREG and VSS3 as describe below. • Place capacitors as close to VREG and VSS3 as possible. • Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L4 = L4’). • Capacitance of C4 must be more than 1μF to 10μF. • Use thicker pattern for VREG and VSS3. L4 VSS3 C4 VREG L4’ No.A1795-26/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB VDDx, VSSx Terminal condition x=2 to 4 • It is necessary to place capacitors between VDDx and VSSx as describe below. • Place capacitors as close to VDDx and VSSx as possible. • Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L5 = L5’). • Capacitance of C5 must be more than 0.1μF. • Use thicker pattern for VDDx and VSSx. L5 VSSx C5 VDDx L5’ VDD RRES (Note) Select CRES and RRES value to assure that reset is generated after the VDD becomes higher than the minimum operating voltage. CRES Recommended value CRES: 0.47μF RRES: 270kΩ RES Figure 1 Reset Circuit No.A1795-27/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB SIOCLK: DATAIN: DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DATAOUT: DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 Data RAM transmission period (only SIO0, 2) tSCK tSCKL tSCKH SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Data RAM transmission period (only SIO0, 2) tSCKL tSCKHA SIOCLK: tsDI thDI DATAIN: tdDO DATAOUT: Figure 2 Serial Input/Output Test Condition tPIL tPIH Figure 3 Pulse Input Timing Condition No.A1795-28/29 LC878496PB/C8PB/G0PB/G1PB/J2PB/J3PB/M4PB/P6PB/P7PB SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of February, 2011. Specifications and information herein are subject to change without notice. PS No.A1795-29/29