SANYO LE24CBK22

Ordering number : EN*A1514A
LE24CBK22
CMOS IC
Two Wire Serial Interface EEPROM
(2K+2K EEPROM)
Overview
The dual port EEPROM series consists of two independent banks, and each bank can be controlled separately using
dedicated control pins. The two banks can each be controlled separately, but share the internal power supply system. In
addition, this product uses a 2-wire serial interface, and is the optimal device for realizing substantial reductions in
system cost and mounting area, as well as low power consumption.
The dual port EEPROM series also has a combined mode that allows the two-bank configuration (2K bits + 2K bits) to
be used as a pseudo one-bank configuration (4K bits) by setting the COBM pin low. Together with the 16-byte page
write function, this enables a reduction in the number of factory write processes.
This product incorporates SANYO's high performance CMOS EEPROM technology and realizes high-speed operation
and high-level reliability. The interface of this product is compatible with the I2C bus protocol, making it ideal as a
nonvolatile memory for small-scale parameter storage.
In addition, this product also supports DDC2TM, so it can also be used as an EDID data storage memory for display
equipment.
Functions
• Capacity
• Bank structure
• Single supply voltage
• Interface
• Operating clock frequency
• Low power consumption
: 2K bits (256 × 8 bits) + 2K bits (256 × 8 bits), 4K bits in total
: 2 banks (2K bits + 2K bits)
: 2.5V to 5.5V
: Two wire serial interface (I2C Bus*), VESA DDC2TM compliant**
: 400kHz (max)
: Standby: 5μA (max)
: Active (Read): 0.5mA (max)
Continued on next page.
2
* : I C Bus is a trademark of Philips Corporation.
** : DDC and EDID are trademarks of Video Electronics Standard Association (VESA).
* This product is licensed from Silicon Storage Technology, Inc. (USA), and manufactured and sold by
SANYO Semiconductor Co., Ltd.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
10511 SY/82609 SY IM No.1514-1/20
LE24CBK22
Continued from preceding page.
• Automatic page write mode: 16 bytes
• Read mode
: Sequential read and random read
• Erase/Write cycles
: 106 cycles
• Data Retention
: 20 years
• High reliability
: Adopts SANYO’s proprietary symmetric memory array configuration (USP6947325)
Noise filters connected to SCL1, SDA2, SCL2 and SDA2 pins
Incorporates a feature to prohibit write operations under low voltage conditions.
• Package
: LE24CBK22M
MFP8 (225mil)
: LE24CBK22TT
MSOP8 (150mil)
Package Dimensions
Package Dimensions
unit:mm (typ)
3032E [LE24CBK22M]
unit:mm (typ)
3245B [LE24CBK22TT]
3.0
5.0
2
1.27
1
0.15
(0.53)
1.7 MAX
0.35
2
0.65
0.125
0.08
0.1
(0.85)
(1.5)
0.25
1.1MAX
1
(0.6)
0.5
0.63
3.0
4.4
6.4
4.9
8
8
SANYO : MFP8(225mil)
SANYO : MSOP8(150mil)
Pin Assignment
Pin Descriptions
PIN.1
SCL2
Serial clock input
PIN.2
SDA2
Serial data input/output
(For Bank2)
SCL2
1
8
VDD
PIN.3
COBM
Bank/combine mode switching
SDA2
2
7
WP
PIN.4
GND
Ground
COBM
3
6
SCL1
PIN.5
SDA1
Serial data input/output
GND
4
5
SDA1
PIN.6
SCL1
Serial clock input
PIN.7
WP
Write protect
PIN.8
VDD
Power supply
(For Bank1)
No.1514-2/20
LE24CBK22
Block Diagram
Bank1
COBM
WP
X decoder
Address generator
Serial controller
Condition detector
EEPROM Array
(2K-bit)
Serial-Parallel converter
Bank2
High voltage generator
X decoder
Address generator
Write controller
Serial controller
Bank Controller & Mode Decoder
Input Buffer
High voltage generator
Y decoder & Sense AMP
Condition detector
SDA2
I/O Buffer
SDA1
I/O Buffer
SCL2
Input Buffer
SCL1
Input Buffer
Write controller
EEPROM Array
(2K-bit)
Y decoder & Sense AMP
Serial-Parallel converter
Description of Operation
The Bank1 control signals are SCL1 and SDA1, and the Bank2 control signals are SCL2 and SDA2. The control signals
for each bank can be controlled separately, regardless of the other bank's status. This enables behavior like two separate
EEPROM mounted in a single package, enabling the Bank1 and Bank2 sides to be used simultaneously for two
independent systems.
Bank mode (2K bits + 2K bits) and combined mode (internally treated as 4K bits) can be switched using the COBM pin.
In combined mode, the Bank1 control signals (SCL1, SDA1) are used, and both Bank1 and Bank2 are accessed. This
enables the two-bank configuration (2K bits + 2K bits) to be used as a pseudo one-bank configuration (4K bits), which
allows access to both the Bank1 and Bank2 areas using a single system of control signals (SCL1, SDA1). Data
correlation is guaranteed between combined mode and bank mode, enabling operation while switching the mode, such
as performing write in combined mode and read in bank mode.
No.1514-3/20
LE24CBK22
Specifications
Absolute Maximum Ratings
Parameter
Symbol
Conditions
Ratings
Supply voltage
DC input voltage
Over-shoot voltage
Storage temperature
Below 20ns
Tstg
Unit
-0.5 to +6.5
V
-0.5 to +5.5
V
-1.0 to +6.5
V
-65 to +150
°C
Note: If an electrical stress exceeding the maximum rating is applied, the device may be damaged.
Operating Conditions
Parameter
Symbol
Conditions
Ratings
Operating supply voltage
Operating temperature
Unit
2.5 to 5.5
V
-40 to +85
°C
DC Electrical Characteristics
Parameter
Symbol
VDD=2.5V to 5.5V
Conditions
min
Supply current at reading
typ
Unit
max
ICC11
f=400kHz
0.5
mA
ICC12
f=400kHz
0.8
mA
ICC21
f=400kHz, tWC=5ms
5
mA
ICC22
f=400kHz, tWC=5ms
8
mA
Standby current
ISB
VIN=VDD or GND
5
μA
Input leakage current
ILI
VIN=GND to VDD
-2.0
+2.0
μA
Output leakage current (SDA)
ILO
VOUT=GND to VDD
-2.0
+2.0
μA
Input low voltage
VIL
VDD*0.3
V
Input high voltage
VIH
(when either Bank1 or Bank2 is read)
Supply current at reading
(when both Bank1 and Bank2 are read
simultaneously)
Supply current at writing
(when either Bank1 or Bank2 is written)
Supply current at writing
(when both Bank1 and Bank2 are
written simultaneously)
VOL
Output low voltage
0.7
VDD*0.7
V
IOL=0.7mA, VDD=2.5V
0.2
V
IOL=3.0mA, VDD=2.5V
0.4
V
IOL=3.0mA, VDD=5.5V
0.4
V
IOL=6.0mA, VDD=4.5V
0.6
V
Capacitance/Ta=25°C, f=100kHz
Parameter
Symbol
Conditions
min
typ
max
Unit
In/Output capacitance
CI/O
VI/O=0V (SDA)
2
5
pF
Input capacitance
CI
VIN=0V (other than SDA)
2
5
pF
Note: This parameter is sampled and not 100% tested.
No.1514-4/20
LE24CBK22
AC Electric Characteristics
Fast Mode
Parameter
VDD=2.5V to 5.5V
Symbol
min
typ
unit
max
Slave mode SCL clock frequency
fSCLS
SCL clock low time
tLOW
1200
ns
SCL clock high time
tHIGH
600
ns
SDA output delay time
tAA
100
SDA data output hold time
tDH
100
ns
Start condition setup time
tSU.STA
600
ns
Start condition hold time
tHD.STA
600
ns
Data in setup time
tSU.DAT
100
ns
Data in hold time
tHD.DAT
0
ns
Stop condition setup time
tSU.STO
600
SCL, SDA rise time
tR
300
ns
SCL, SDA fall time
tF
300
ns
Bus release time
tBUF
Noise suppression time
tSP
Write cycle time
tWC
0
400
kHz
900
ns
ns
1200
ns
100
ns
5
ms
Standard Mode
Parameter
VDD=2.5V to 5.5V
Symbol
min
typ
unit
max
Slave mode SCL clock frequency
fSCLS
SCL clock low time
tLOW
4700
0
100
kHz
SCL clock high time
tHIGH
4000
SDA output delay time
tAA
SDA data output hold time
tDH
100
ns
Start condition setup time
tSU.STA
4700
ns
Start condition hold time
tHD.STA
4000
ns
Data in setup time
tSU.DAT
250
ns
Data in hold time
tHD.DAT
0
ns
Stop condition setup time
tSU.STO
4000
ns
ns
ns
100
3500
ns
SCL, SDA rise time
tR
1000
ns
SCL, SDA fall time
tF
300
ns
Bus release time
tBUF
Noise suppression time
tSP
Write cycle time
tWC
4700
ns
100
ns
5
ms
Bus Timing
tF
tHIGH
tLOW
tR
tSP
SCL
tSU.STA
tHD.STA
tHD.DAT
tSU.DAT
tSU.STO
tSP
SDA/IN
tAA
tDH
tBUF
SDA/OUT
No.1514-5/20
LE24CBK22
Write Timing
tWC
SCL
D0
SDA
Write Data
Acknowledge
Stop
condition
Start
condition
Pin Functions
(For Bank1)
SCL1 (serial clock input) pin
The SCL1 pin is the serial clock input pin used to access the Bank1 area, and processes signals at the rising and falling
edges of the SCL1 clock signal.
This pin must be pulled up by a resistor to the VDD level, and wired-ORed with another open drain (or open collector)
output device for use.
In combined mode, the SCL1 pin is serial clock input pin controlled both Bank1 and Bank2.
SDA1 (serial data input/output) pin
The SDA1 pin is used to transfer serial data to the input/output of the Bank1 side area and it consists of a signal input
pin and n-channel transistor open drain output pin.
Like the SCL1 line, the SDA1 line must be pulled up by a resistor to the VDD level and wired-ORed with another
open drain (or open collector) output device for use.
In combined mode, the SDA1 pin is serial data input/output pin controlled both Bank1 and Bank2.
(For Bank2)
SCL2 (serial clock input) pin
The SCL2 pin is the serial clock input pin used to access the Bank2 area, and processes signals at the rising and falling
edges of the SCL2 clock signal.
This pin must be pulled up by a resistor to the VDD level, and wired-ORed with another open drain (or open collector)
output device for use.
In combined mode, the SCL2 pin is invalid.
SDA2 (serial data input/output) pin
The SDA2 pin is used to transfer serial data to the input/output of the Bank2 side area and it consists of a signal input
pin and n-channel transistor open drain output pin.
Like the SCL2 line, the SDA2 line must be pulled up by a resistor to the VDD level and wired-ORed with another
open drain (or open collector) output device for use.
In combined mode, the SDA2 pin is invalid.
(Shared pins)
WP (write protect) pin
When the WP pin is high, write protect is enabled, and write is prohibited to all memory areas within both Bank1 and
Bank2. Read operation can access all memory areas regardless of the WP pin status.
COBM(combined Mode) pin
The COBM pin is used to switch the EEPROM internal operation between bank mode and combined mode. The
EEPROM operates in bank mode when the COBM pin is high, and in combined mode when low.
Note that in combined mode, the SCL2 and SDA2 pins are treated as don’t care.
No.1514-6/20
LE24CBK22
Functional Description
1. Start condition
When the SCL line is at the high level, the start condition is established by changing the SDA line from high to low.
The operation of the EEPROM as a slave starts in the start condition.
2. Stop condition
When the SCL line is at the high level, the stop condition is established by changing the SDA line from low to high.
When the device is set up for the read sequence, the read operation is suspended when the stop condition is received,
and the device is set to standby mode. When it is set up for the write sequence, the capture of the write data is ended
when the stop condition is received, and the EEPROM internal write operation is started.
tSU.STA
tSU.STO
tHD.STA
SCL
SDA
Stop
condition
Start
condition
3. Data transfer
Data is transferred by changing the SDA line while the SCL line is low. When the SDA line is changed while the SCL
line is high, the resulting condition will be recognized as the start or stop condition.
tSU.DAT
tHD.DAT
SCL
SDA
No.1514-7/20
LE24CBK22
4. Acknowledge
During data transfer, 8 bits are transferred in succession, and then in the ninth clock cycle period the device on the
system bus receiving the data sets the SDA line to low, and sends the acknowledge signal indicating that the data has
been received. The acknowledge signal is not sent during an EEPROM internal write operation.
SCL
(EEPROM input)
8
1
9
SDA
(Master output)
Acknowledge
bit output
SDA
(EEPROM output)
Start
condition
tAA
tDH
5. Device addressing
For the purposes of communication, the master device in the system generates the start condition for the slave device.
Communication with a particular slave device is enabled by sending along the SDA bus the device address, which is 7
bits long, and the read/write command code, which is 1 bit long, immediately following the start condition.
The upper four bits of the device address are called the device code which, for this product, is fixed as “1010.” This
device has the upper 3-bit of the Slave Device address as the Slave address (Bank1: SA2, SA1, SA0 and Bank2: SB2,
SB1, SB0), which fixed internally. The value of Slave address are SA2=0, SA1=0, SA0=0 and SB2=0, SB1=0, B0=0
When the device code input from SDA and the slave addresses are compared with the product’s device code and slave
addresses that were set at the mounting stage and found to match, the product sends the acknowledge signal during
the ninth clock cycle period, and initiates the read or write operation in accordance with the read or write command
code. If they do not match, the EEPROM returns to standby mode. When a read operation is performed immediately
after the slave device has been switched, the random read command must be used.
Device Code
Bank1
1
0
1
Slave Address
0
SA2
SA1
MSB
SA0
or A8
R/W
LSB
Device address word
* The default internal slave address is set to SA2 = 0, SA1 = 0, SA0 = 0.
* In bank mode (2K bits), the valid address is A7 to A0, and the valid slave address is SA2, SA1 and SA0.
* In combined mode (4K bits), the valid address is A8 to A0, and the slave address SA2 and SA1 is don’t care.
A8 = 0: Selects the Bank1 area, A8 = 1: Selects the Bank2 area.
Valid Address
Slave Address
Bank mode
(COBM=’H’)
A7-A0
SA2, SA1, SA0
Combine mode
(COBM=’L’)
A8-A0
SA2, SA1
A8=0: Selects the Bank1 area
But SA2 and SA1 are don’t care.
A8=1: Selects the Bank2 area
No.1514-8/20
LE24CBK22
Slave Address
Device Code
Bank2
1
0
1
0
SB2
MSB
SB1
SB0
R/W
LSB
Device address word
* The default internal slave address is set to SB2 = 0, SB1 = 0, SB0 = 0.
* In combine mode (4K bits), communication in Bank2 side is invalid.
Valid Address
Bank mode
(COBM=’H’)
Combine mode
(COBM=’L’)
A7-A0
Slave Address
SB2, SB1, SB0
-
-
6. Internal mode
The EEPROM functions in bank mode when the COBM pin is high, or in combined mode when the COBM pin is low.
6-1. Bank mode
The EEPROM functions in bank mode when the COBM pin is high. In bank mode, each bank (Bank1, Bank2) is
controlled separately using dedicated control signals. The two banks are independent, and can be controlled separately
regardless of the other bank's status. This enables treatment like two separate EEPROM mounted in a single package,
which means that the Bank1 and Bank2 sides can be connected to the MCU of separate systems.
LE24CBK22
SCL1
00h
Bank1
(2K-bit)
SDA1
FFh
WP
SCL2
00h
Bank2
(2K-bit)
SDA2
FFh
No.1514-9/20
LE24CBK22
6-2. Combine mode
The EEPROM functions in combined mode when the COBM pin is low. In combined mode, The Bank1 control
signals SCL1 and SDA1 are used to control both Bank1 and Bank2. Combined mode uses the two-bank configuration
(2K bits + 2K bits) as a pseudo one-bank configuration (4K bits). In combined mode, the Bank2 control signals SCL2
and SDA2 are treated as don’t care.
In combined mode, the memory area is processed as a 4K-bit single bank, so the MSB address changes from A7 to A8,
and A8 becomes a valid address. Set A8 = 0 to control the Bank1 area, or A8 = 1 to control the Bank2 area.
Data correlation is guaranteed between combined mode and bank mode, enabling operation while switching the mode,
such as performing write in combined mode and read in bank mode.
Slave Address
Device Code
Bank1
1
0
1
0
x
x
A8
R/W
X: don’t care
LSB
MSB
Device address word
LE24CBK22
000h
SCL1
Bank1
(2K-bit)
SDA1
WP
0FFh
100h
Bank2
(2K-bit)
SCL2
SDA2
1FFh
7 EEPROM write operation
7-1. Byte writing
When the EEPROM receives the 7-bit device address and write command code “0” after the start condition, it
generates an acknowledge signal. After this, if it receives the 8-bit word address, generates an acknowledge signal,
receives the 8-bit write data, generates an acknowledge signal and then receives the stop condition, the internal write
operation of the EEPROM in the designated memory address will start. Rewriting is completed in the tWC period
after the stop condition. During an EEPROM internal write operation, no input is accepted and no acknowledge
signals are generated.
1
0
1
0 S2 S1
S0/
A8 W
A7 A6 A5 A4 A3 A2 A1 A0
ACK
R/W
In bank mode: S2, S1, and S0 are valid.
Data
D7 D6 D5 D4 D3 D2 D1 D0
ACK
Stop
SDA
Start
Word Address
ACK
Access from master
In combined mode: A8 is valid. S2 and S1 are don’t care.
No.1514-10/20
LE24CBK22
7-2. Page writing
This product enables pages with up to 16 bytes to be written. The basic data transfer procedure is the same as for byte
writing: Following the start condition, the 7-bit device address and write command code “0,” word address (n), and
data (n) are input in this order while confirming acknowledge “0” every 9 bits. The page write mode is established if,
after data (n) is input, the write data (n+1) is input without inputting the stop condition. After this, the write data
equivalent to the largest page size can be received by a continuous process of repeating the receiving of the 8-bit
write data and generating the acknowledge signals.
At the point when the write data (n+1) has been input, the lower 4 bits (A0-A3) of the word addresses are
automatically incremented to form the (n+1) address. In this way, the write data can be successively input, and the
word address on the page is incremented each time the write data is input. If the write data exceeds 16 bytes or the
last address of the page is exceeded, the word address on the page is rolled over. Write data will be input into the
same address two or more times, but in such cases the write data that was input last will take effect. Finally, the
EEPROM internal write operation corresponding to the page size for which the write data is received starts from the
designated memory address when the stop condition is received.
SDA
Start
Memory Address(n)
1
0
1
0 S2 S1
S0/
W
A8
Data(n)
A7 A6 A5 A4 A3 A2 A1 A0
ACK
R/W
Data(n+1)
D7 D6 D5 D4 D3 D2 D1 D0
• •
D7 D6 - D1 D0
ACK
ACK
ACK
• •
D7 D6 - D1 D0
D7 D6 - D1 D0
D7 D6 - D1 D0
ACK
D7 D6 - D1 D0
ACK
Stop
Data(n+x)
ACK
In bank mode: S2, S1, and S0 are valid.
Access from master
In combined mode: A8 is valid. S2 and S1 are don’t care.
7-3. Acknowledge polling
Acknowledge polling is used to find out when the EEPROM internal write operation is completed. When the stop
condition is received and the EEPROM starts rewriting, all operations are prohibited, and no response can be given to
the signals sent by the master device. Therefore, in order to find out when the EEPROM internal write operation is
completed, the start condition, device address and write command code are sent from the master device to the
EEPROM (slave device), and the response of the slave device is detected.
In other words, if the slave device does not send the acknowledge signal, it means that the internal write operation is
in progress; conversely, if it does send the acknowledge signal, it means that the internal write operation has been
completed.
0
1
0 S2 S1
S0/
W
A8
During Write
1
NO ACK
R/W
0
1
0 S2 S1
End of Write
Start
1
Start
SDA
Start
During Write
S0/
A8 W
1
0
1
S0/
0 S2 S1 A8 W
• •
ACK
R/W
NO ACK
R/W
In bank mode: S2, S1, and S0 are valid.
In combined mode: A8 is valid. S2 and S1 are don’t care.
Access from master
No.1514-11/20
LE24CBK22
8 EEPROM read operations
8-1. Current address reading
The address equivalent to the memory address accessed last +1 is held as the internal address of the EEPROM for
both write* and read operations. Therefore, provided that the master device has recognized the position of the
EEPROM address pointer, data can be read from the memory address with the current address pointer without
specifying the word address.
As with writing, current address reading involves receiving the 7-bit device address and read command code “1”
following the start condition, at which time the EEPROM generates an acknowledge signal. After this, the 8-bit data
of the (n+1) address is output serially starting with the highest bits. After the 8 bits have been output, by not sending
an acknowledge signal and inputting the stop condition, the EEPROM completes the read operation and is set to
standby mode.
If the previous read address is the last address, the address for the current address reading is rolled over to become
address 0.
*: If the last address (A3-A0=1111b) on the page has been designated at the write operation as the word address,
the first address (A3-A0=0000b) on the page serves as the internal address after writing.
1
0
1
0 S2 S1
Data(n+1)
S0/
R
A8
Stop
SDA
Start
Device Address
D7 D6 D5 D4 D3 D2 D1 D0
NO ACK
ACK
R/W
In bank mode: S2, S1, and S0 are valid.
Access from master
In combined mode: A8 is valid. S2 and S1 are don’t care.
8-2. Random read
Random read is a mode in which any memory address is specified and its data read. The address is specified by a
dummy write input.
First, when the EEPROM receives the 7-bit device address and write command code “0” following the start condition,
it generates an acknowledge signal. It then receives the 8-bit word address, and generates an acknowledge signal.
Through these operations, the word address is loaded into the address counter inside the EEPROM.
Next, the start condition is input again and the current read is initiated. This causes the data of the word address that
was input using the dummy write input to be output. If, after the data is output, an acknowledge signal is not sent and
the stop condition is input, reading is completed, and the EEPROM returns to standby mode.
1
0
1
0 S2 S1
S0/
W
A8
A7 A6 A5 A4 A3 A2 A1 A0
ACK
R/W
Dummy Write
Start
Start
SDA
Device Address
ACK
1
0
1
Data(n)
0 S2 S1
S0/
R
A8
D7 - D0
ACK
Stop
Word Address(n)
Device Address
NO ACK
R/W
Current Read
In bank mode: S2, S1, and S0 are valid.
In combined mode: A8 is valid. S2 and S1 are don’t care.
Access from maste
No.1514-12/20
LE24CBK22
8-3. Sequential read
In this mode, the data is read continuously, and sequential read operations can be performed with both current address
read and random read. If, after the 8-bit data has been output, acknowledge “0” is input and reading is continued
without issuing the stop condition, the address is incremented, and the data of the next address is output.
If acknowledge “0” continues to be input after the data has been output in this way, the data is successively output
while the address is incremented. When the last address is reached, it is rolled over to address 0, and the data
continues to be read. As with current address read and random read, the operation is completed by inputting the stop
condition without sending an acknowledge signal.
1
0
1
0 S2 S1
Data (n)
S0/
R
A8
Data (n+1)
D7 D6 - D1 D0
D7 D6 - D1 D0
ACK
ACK
R/W
In bank mode: S2, S1, and S0 are valid.
Data (n+x)
D7 D6 - D1 D0
Stop
SDA
Start
Device Address
ACK
NO ACK
Access from maste
In combined mode: A8 is valid. S2 and S1 are don’t care.
No.1514-13/20
LE24CBK22
Application Notes
1) Software reset function
Software reset (start condition + 9 dummy clock cycles + start condition), shown in the figure below, is executed in
order to avoid erroneous operation after power-on and to reset while the command input sequence. During the
dummy clock input period, the SDA bus must be opened (set to high by a pull-up resistor). Since it is possible for
the ACK output and read data to be output from the EEPROM during the dummy clock period, forcibly entering H
will result in an overcurrent flow.
Note that this software reset function does not work during the internal write cycle.
Dummy clock cycle × 9
1
SCL
2
8
9
SDA
Start condition
Start condition
2) Pull-up resistor of SDA pin
Due to the demands of the I2C bus protocol function, the SDA pin must be connected to a pull-up resistor (with a
resistance from several kΩ to several tens of kΩ) without fail. The appropriate value must be selected for this
resistance (RPU) on the basis of the VIL and IIL of the microcontroller and other devices controlling this product as
well as the VOL–IOL characteristics of the product. Generally, when the resistance is too high, the operating
frequency will be restricted; conversely, when it is too low, the operating current consumption will increase.
RPU maximum resistance
The maximum resistance must be set in such a way that the bus potential, which is determined by the sum total (IL)
of the input leaks of the devices connected to the SDA bus and by RPU, can completely satisfy the input high level
(VIH min) of the microcontroller and EEPROM. However, a resistance value that satisfies SDA rise time tR and fall
time tF must be set.
RPU maximum value = (VDD - VIH)/IL
Example: When VDD=3.0V and IL= 2μA
RPU maximum value = (3.0V − 3.0V × 0.8)/2μA = 300kΩ
RPU minimum value
A resistance corresponding to the low-level output
voltage (VOL max) of SANYO’s EEPROM must be set.
RPU minimum value = (VDD − VOL)/IOL
RPU
EEPROM
Master
device
IL
SDA
CBUS
IL
Example: When VDD=3.0V, VOL = 0.4V and IOL = 1mA
RPU minimum value = (3.0V − 0.4)/1mA = 2.6kΩ
Recommended RPU setting
RPU is set to strike a good balance between the operating frequency requirements and power consumption. If it is
assumed that the SDA load capacitance is 50pF and the SDA output data strobe time is 500ns, RPU will be about
RPU = 500ns/50pF = 10kΩ.
No.1514-14/20
LE24CBK22
3) Precautions when turning on the power
This product contains a power-on reset circuit for preventing the inadvertent writing of data when the power is
turned on. The following conditions must be met in order to ensure stable operation of this circuit. No data
guarantees are given in the event of an instantaneous power failure during the internal write operation.
Item
VDD=2.5 to 5.5V
Symbol
min
Power rise time
tRISE
Power off time
tOFF
Power bottom voltage
Vbot
typ
unit
max
100
ms
10
ms
0.2
V
tRISE
VDD
tOFF
Vbot
0V
Notes:
1) The SDA pin must be set to high and the SCL pin to low or high.
2) Steps must be taken to ensure that the SDA and SCL pins are not placed in a high-impedance state.
A. If it is not possible to satisfy the instruction 1 in Note above, and SDA is set to low during power rise
After the power has stabilized, the SCL and SDA pins must be controlled as shown below, with both pins set to high.
VDD
VDD
tLOW
SCL
SCL
SDA
SDA
tDH
tSU.DAT
tSU.DAT
B. If it is not possible to satisfy the instruction 2 in Note above
After the power has stabilized, software reset must be executed.
C. If it is not possible to satisfy the instructions both 1 and 2 in Note above
After the power has stabilized, the steps in A must be executed, then software reset must be executed.
4) Noise filter for the SCL and SDA pins
This product contains a filter circuit for eliminating noise at the SCL and SDA pins. Pulses of 100ns or less are not
recognized because of this function.
5) Function to inhibit writing when supply voltage is low
This product contains a supply voltage monitoring circuit that inhibits inadvertent writing below the guaranteed
operating supply voltage range. The data is protected by ensuring that write operations are not started at voltages
(typ.) of 1.3V and below.
6) Slave address settings
This product does not come with any slave address pins, but the information of the Bank1: SA2, SA1, SA0 and
Bank2: SB2, SB1, SB0 slave addresses is held internally. SA2=0, SA1=0, SA0=0 and SB2=0, SB1=0, SB0=0 were
set for the slave addresses before shipment. During device addressing, these slave address codes must be executed
following the device code.
No.1514-15/20
LE24CBK22
7) Note on Write Protect Operation
This product prohibits writing to all memory areas when the WP pin is high. To ensure full write protection, the WP
pin is set high for all periods from the start condition to the stop condition, and the condition below must be satisfied.
Item
VDD=2.5 to 5.5V
Symbol
min
typ
unit
max
WP Setup time
tSU.WP
600
ns
WP Hold time
tHD.WP
600
ns
WP
tHD.WP
tSU.WP
SCL
SDA
Start condition
Stop condition
8) Notes on Mode Switching
This product selects bank mode operation or combined mode operation according to the COBM pin status. Changing
the COBM pin status while this product is active (during access to Bank1 or Bank2, including during the write
period) is prohibited.
The following conditions must be observed to ensure reliable access functions in each mode.
Item
VDD=2.5 to 5.5V
Symbol
min
typ
unit
max
COBM Setup time
tSU.COBM
10
μs
COBM Hold time (Write cycle time)
tHD.COBM
5
ms
COBM
tSU.COBM
tHD.COBM
SCL
SDA
Start condition
Stop condition
No.1514-16/20
LE24CBK22
9) Write using a ROM writer in combined mode
This product enters combined mode by setting the COBM pin (Pin 3) low, which allows the two-bank configuration
(2K bits + 2K bits) to be used as a pseudo one-bank configuration (4K bits). This enables write using a ROM writer
in the manner of a typical 4k-bit EEPROM.
LE24C04x
(Standard 4K-bit EEPROM)
LE24CBK22
SCL2
1
8
VDD
S0
1
8
VDD
SDA2
2
7
WP
S1
2
7
WP
COBM
3
6
SCL1
S2
3
6
SCL
GND
4
5
SDA1
GND
4
5
SDA
Pin 3 of standard 4K-bit EEPROM products is assigned a slave pin (S2), but Pin 3 of the LE24CBK22 is assigned the
COBM pin. Combined mode is entered by setting the COBM pin low. In combined mode, the state of the SCL2 pin and
SDA2 pin is "don't care" (may be either high, low, or open).
ROM writer connection example
Connect to GND
level
LE24CBK22
(don’t care)
SCL2
1
8
VDD
SDA2
2
7
WP
COBM
3
6
SCL1
GND
4
5
SDA1
Slave
Address
Device Code
In combined mode:
(From SCL1/SDA1)
1
0
1
0
SA2
MSB
SA1
A8
R/W
LSB
Device address word
In combined mode, the slave address (SA2, SA1) is don't care, and any combination can be entered
(SA2 = 1, SA1 = 1 or SA2 = 1, SA1 = 0 or SA2 = 0, SA1 = 1 or SA2 = 0, SA1 = 0).
No.1514-17/20
LE24CBK22
Memory Area (4K-bit)
000h
Bank1
(2K-bit)
A8=0
The MSB address in combined mode is A8. A8 is used to select the
Bank1 or Bank2 area. Set A8 = 0 to control the Bank1 area, or A8 = 1
to control the Bank2 area.
0FFh
100h
Bank2
(2K-bit)
A8=1
1FFh
10) System Configuration Image
(HDMI System)
This product can support two HDMI ports simultaneously. Each port can be accessed (read operation, write
operation) constantly, regardless of the other port’s status.
Bank1
LE24CBK22
Image
Processor
HDMI
Connector
Bank2
2
DDC
2
IC
Level Shifter
TMDS
HDMI
Connector
IC
Level Shifter
HDMI
Receiver
DDC
TMDS
LCD-TV
No.1514-18/20
LE24CBK22
11) Peripheral Circuit Diagram
Example of connection with HDMI receiver
VDD(3V) *1
*2
DDC+5V
*2
*5
RPU
8:VDD
DDC_CLK
HDMI
Connector DDC_DAT
LE24CBK22
*4
GND
7:WP
6:SCL1
5:SDA1
*2
DDC+5V
DDC_CLK
HDMI
Connector DDC_DAT
*5
RPU
3:COBM
1:SCL2
2:SDA2
GND
4:GND
*3
Level Shifter
*3
Level Shifter
VDD(3V)
SCL1(3V)
SDA1(3V) HDMI
Receiver
SCL2(3V)
SDA2(3V)
*1: System power supply (3V) for HDMI receiver, etc.
*2: Reverse-current preventing diode
This device can be operated by supplying power from any of the connected HDMI connectors (DDC + 5V) or the
system power supply (3V). However, the supply voltage must be set so that the voltage stepped-down by the
reverse-current preventing diode is within the guaranteed operation voltage range of this device.
*3: Level shifter
When connecting the 5V HDMI connector side with a 3V system, level shifters must generally be inserted. However,
this is not necessary when the HDMI receiver supports 5V input signals.
*4: Write protect
In general after implementation, use with HDMI applications presumes that this device performs read-only operation.
The write protect function is enabled to prevent write due to mistaken access, by setting the WP pin to the same
level as the power supply (8: VDD) for this device.
Note that the WP pin is connected to the power supply via a resistor, and that when re-settings, etc., is necessary,
write operation is enabled by connecting the WP pin to GND level using jumpers, etc.
*5: Pull-up resistors for the I2C and DDC interfaces.
See item 2) in the Application Notes for the resistance value settings.
No.1514-19/20
LE24CBK22
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using
products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise
to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise,
without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
for volume production.
Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
intellectual property rights which has resulted from the use of the technical information and products mentioned
above.
This catalog provides information as of January, 2011. Specifications and information herein are subject
to change without notice.
PS No.1514-20/20