SANYO LV5223GR

Ordering number : ENA1969
Bi-CMOS IC
LV5223GR
LED Driver
Overview
The LV5223GR is 9ch LED driver IC for the cell phones with built-in charge pump circuit.
Features
• LED driver ×9 channels (3-color 1, 3-color 2, GPO (LED) ×3, 9 channels in total) and on-chip charge pump circuit.
• Each LED driver current level can be adjusted independently over the serial bus.
• Ring tone and 3-color LEDs (3-color 1, 3-color 2) synchronization function.
• Gradation function (3-color 1, 3-color 2, in total 6 channels only)
• RLED2 and GLED2 support strobe mode.
• Miniature package
Function
• Charge pump circuit ((2 times step up) Output voltage: 5V)
• LED driver 3-color LED ×2 + GPO (LED) LED driver ×3
Channel 1 LED current can be switched indecently in 5-bit units (0.5 to 16mA)
Ring tone synchronization function (forced activation with SCTL: H)
Gradation function
Channel 1 LED current can be switched indecently in 5-bit units (0.5 to 16mA)
Ring tone synchronization function (forced activation with SCTL: H)
Gradation function
Only RLED2 and GLED2 support strobe mode; LED current output (2.8mA to 44.8mA) (FCTL=high)
GPO1 (LED3), GPO2 (LED4), GPO3 (LED5) when GPO1 to GPO3 are used as the LED driver
• GPO output ×3
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to
"standard application", intended for the use as general electronics equipment (home appliances, AV equipment,
communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be
intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace
instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety
equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case
of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee
thereof. If you should intend to use our products for applications outside the standard applications of our
customer who is considering such use and/or outside the scope of our intended standard applications, please
consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our
customer shall be solely responsible for the use.
Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate
the performance, characteristics, and functions of the described products in the independent state, and are not
guarantees of the performance, characteristics, and functions of the described products as mounted in the
customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent
device, the customer should always evaluate and test devices mounted in the customer' s products or
equipment.
72011 SY 20080410-S00003 No.A1969-1/24
LV5223GR
Specifications
Maximum Ratings at Ta = 25°C
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
VCC max
Maximum voltage
V1 max
Maximum output current
IO max 1
RLED1, GLED1, BLED1 and BLED2 pins
40
mA
IO max 2
RLED2 and GLED2 pins
50
mA
Allowable power dissipation
Pd max
* Mounted on a circuit board
800
mW
Operating temperature
Topr
-30 to +80
°C
Storage temperature
Tstg
-40 to +125
°C
LED pins, charge pump pin
5
V
6
V
* Specified board: 40mm × 50mm × 0.8mm, glass epoxy board. (2S2P (4-layer board))
Operating Conditions at Ta = 25°C
Parameter
Symbol
Supply voltage 1
VBAT
Supply voltage 2
VDD
Conditions
Ratings
Unit
3.0 to 5.0
V
1.65 to VBAT
V
Electrical Characteristics at Ta = 25°C, VCC = 5.0V
Parameter
Symbol
Conditions
Ratings
min
typ
Unit
max
Consumption current
Consumption current
ICC1
VBAT+VDD consumption current RESET:L
(when reset)
ICC2
VBAT+VDD consumption current RESET:H in
serial default
ICC3
VBAT+VDD consumption current
charge pump: ON
0
5
μA
0.5
5.0
μA
4
mA
500
kHz
Oscillator block
Oscillator frequency
Fosc
Charge pump block
Output voltage
VO1
IO=30mA
4.8
5.0
5.2
V
Maximum current
IO1
TSS
VBAT=3.3V, VO1>4.3V
TSS=1/Fosc × 400 *1
200
Soft start time
3-color 1, 2 LED driver FCTL=L
0.2
0.5
1.0
mA
15
16
17
mA
1.8
2.8
3.8
mA
42.0
44.8
47.6
mA
mA
μs
800
LED driver block
Minimum output current value 1
IMIN1
Serial data=#00 VO=0.5V
Maximum output current value 1
IMAX1
3-color 1, 2 LED driver FCTL=L
Serial data=#FF VO=0.5V
Minimum output current value 2
IMIN2
RLED2, GLED2 pin LED driver FCTL=H
Serial data=#00 VO=0.5V
Maximum output current value 2
IMAX2
RLED2, GLED2 pin LED driver FCTL=H
Serial data=#FF VO=0.5V
ON resistance
RON1
GPO1(LED3), GPO2(LED4), GPO3(LED5) pins
Ω
5
When LED driver ON IL=-40mA
Non-linearity error
LE1
3-color 1, 2 LED driver VO=0.5V *2
-2
2
LSB
Differential linearity error
DLE1
3-color 1, 2 LED driver VO=0.5V *3
-2
2
LSB
Maximum output current
ΔIL1
3-color LED driver 1, 2 FCTL=L
-10
%
-10
%
Maximum current setting VO=0.35V
ΔIL2
RLED2, GLED2 pin LED driver FCTL=H
Maximum current setting VO=0.45V
Leakage current
IL1
3-color LED driver 1, 2 & GPO(LED) × 3
1
μA
0.45
V
LED driver: OFF VO=5V
Control circuit block
H level 1
VINH1
Input H level SCTL
1.3
L level 1
VINL1
Input L level SCTL
0
H level 2
VINH2
Input H level FCTL
1.3
L level 2
VINL2
Input L level FCTL
0
H level 3
VINH3
Input H level serial signal input pin
VDD × 0.8
V
V
0.45
V
V
Continued on next page.
No.A1969-2/24
LV5223GR
Continued from preceding page.
Parameter
Symbol
Conditions
L level 3
VINL3
Input L level serial signal input pin
H level 4
VINH4
Input H level RESET
L level 4
VINL4
Input L level RESET
H level 5
VHO5
Output H level GPO1 GPO2 GPO3 IL=1mA
Ratings
min
typ
0
max
VDD × 0.2
1.5
0
Unit
V
V
0.3
VDD – 0.3
V
V
When output mode is set to buffer
L level 5
VLO5
Output L level GPO1 GPO2 GPO3 IL=-1mA
0
0.3
V
When output mode is set to buffer
*1. Soft start time: Interval from the time the charge pump is started until the time the charge pump output voltage reaches 5V.
*2. Non-linearity error: The difference between the actual and ideal current values.
*3. Differential linearity error: The difference between the actual and ideal increment when one low-order bi value is added.
Note) The LED current can be charged by changing the value of RT.
(Example: When RT = 10kΩ, VO>0.945V and RGB1&2 LED current is set to 14.5mA, the RGB1&2 current can be set to flow at 14.5mA × 27kΩ /
10 kΩ = 39.15mA)
(When the value of RT has been reduced, adjust the oscillation frequency by increasing the value of CT.)
Package Dimensions
unit : mm (typ)
3357
TOP VIEW
SIDE VIEW
BOTTOM VIEW
(0.125)
(0.09)
3.5
0.4
3.5
(C0.09)
28
2 1
0.19
(0.55)
0.4
(0.035)
0.8
SIDE VIEW
Pd max -- Ta
1.0
Allowable power dissipation, Pd max -- W
SANYO : VCT28(3.5X3.5)
Specified board : 40.0 × 50.0 × 0.8mm3
4-layer glass epoxy(2S2P)
0.8
0.6
0.4
0.36
0.2
0
--30
0
20
40
60
80
100
Ambient temperature, Ta -- C
No.A1969-3/24
LV5223GR
Block Diagram & Pin arrangement drawing
VBAT
RESET
17
PGND
SVBAT
18
C1B
CT
19
PVBAT
SGND
100pF
C1A
TC
20
OUT
470pF
TEST
FCTL
21
SCTL
16
15
22
14
Charge pump
23
13
24
12
25
OSC
26
IREF
Sirial I/F
11
10
9
27
VDD
SCL
SDA
RT
GPO3(LED5)
GPO2(LED4)
LED driver
RLED1
8
28
1
2
3
4
5
6
GPO1(LED3)
7
BLED2
GLED2
LEDGND2
RLED2
BLED1
GLED1
LEDGND1
Pin Descriptions
Pin No.
Pin name
Description
1
LEDGND1
GND pin1 for LED driver
2
GLED1
GLED1 driver output pin
3
BLED1
BLED1 driver output pin
4
RLED2
RLED2 driver output pin
5
LEDGND2
GND pin2 for LED driver
6
GLED2
GLED2 driver output pin
7
BLED2
BLED2 driver output pin
8
GPO1(LED3)
GPO1 output & LED3 driver output pin
9
GPO2(LED4)
GPO2 output & LED4 driver output pin
10
GPO3(LED5)
GPO3 output & LED5 driver output pin
11
RT
Standard current setting resistance connection pin
12
SDA
Serial data signal input pin
13
SCL
Serial clock signal input pin
14
VDD
Power supply pin
15
PGND
GND pin for Charge pump
16
C1B
Flying capacitor connection pin B for charge pump
17
PVBAT
Power supply for charge pump
18
C1A
Flying capacitor connection pin A for charge pump
19
OUT
Output pin for charge pump
20
TEST
TEST pin
21
FCTL
Strobe mode pin
22
SCTL
3-color1 & 3-color2 LED driver external synchronous signal input pin
23
TC
Charge pump phase amends pin
24
SGND
GND pin for analog circuit
25
CT
Setting of frequency of oscillator capacity connection pin
26
SVBAT
Supply voltage for analog circuit
27
RESET
RESET signal input pin
28
RLED1
RLED1 driver output pin
Protection
Protection
diode vs. VBAT diode vs. GND
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
○
No.A1969-4/24
LV5223GR
Pin Functions
Pin No.
Pin Name
Pin function
1
LEDGND1
GND pin1 for LED driver
2
GLED1
LED driver pin for RGB1 and RGB2.
3
BLED1
Feedback is applied so that the current flowing to the output
4
RLED2
transistor becomes the set current level. When RT=27kΩ, the
6
GLED2
driver output current levels can be independently adjusted from
7
BLED2
approx. 0.5mA to 16mA in 0.5mA steps by serial setting. In the
28
RLED1
strobe mode, the current levels can be independently adjusted
Equivalent Circuit
from 2.8mA to 44.8mA in 2.8mA steps for the RLED2 and GLED2
pins only.
5
LEDGND2
GND pin2 for LED driver
8
GPO1(LED3)
GPO output/LED driver shared pin. Output can be set to current
9
GPO2(LED4)
sink by serial setting or VDD or GND voltage can be output.
10
GPO3(LED5)
11
RT
Reference current setting resistor connection pin. The reference
current is generated by connecting an external resistor to GND.
VDD
SVBAT
The pin voltage is approximately 0.65V. By changing this current
level, the oscillation frequency and LED driver current (3-color 1
and 3-color 2 only) can be changed.
12
SDA
Serial data signal input pin
13
SCL
Serial clock signal input pin
14
VDD
Power supply pin
15
PGND
GND pin for Charge pump
16
C1B
Charge pump flying capacitor connection pin B
This pin is connected to the clock driver side of the charge pump.
SVBAT
VDD
SVBAT
VDD
SVBAT
SVBAT
Continued on next page.
No.A1969-5/24
LV5223GR
Continued from preceding page.
Pin No.
Pin Name
17
PVBAT
18
C1A
Pin function
Equivalent Circuit
Power supply for charge pump
Charge pump flying capacitor connection pin A
This pin is connected to the charge transfer driver side of the
PVBAT
charge pump.
C1A
19
OUT
Output pin for charge pump
20
TEST
Test pin. This must always be connected to GND.
21
FCTL
FCTL: Strobe mode pin.
22
SCTL
SCTL: 3-color 1 and 3-color 2 LED driver external sync signal input
OUT
SVBAT
SVBAT
pin.
When this pin is not going to be used, it must be connected to GND
without fail.
23
TC
Charge pump phase compensation pin.
Stable operation of the charge pump is provided by connecting a
SVBAT
capacitor to this pin.
24
SGND
25
CT
GND pin for analog circuit
Oscillator frequency setting capacitor connection pin.
The oscillation frequency can be changed by changing the
SVBAT
capacitance of the capacitor.
26
SVBAT
27
RESET
Supply voltage for analog circuit
RESET signal input pin.
Reset state at L.
SVBAT
No.A1969-6/24
LV5223GR
Serial Bus Communication Specifications
1) I2C serial transfer timing conditions
twH
SCL
th1
twL
th2
tbuf
SDA
th1
ts2
ts1
ton
START condition
tof
ts3
Resend start condition
STOP condition
Input waveform condition
Standard mode
Parameter
Symbol
Conditions
Min.
Typ.
Max.
SCL clock frequency
fsc1
SCL clock frequency
0
-
100
kHz
Data setup time
ts1
SCL setup time relative to the fall of SDA
4.7
-
-
μs
ts2
SDA setup time relative to the rise of SCL
250
-
-
ns
ts3
SCL setup time relative to the rise of SDA
4.0
-
-
μs
th1
SCL hold time relative to the fall of SDA
4.0
-
-
μs
th2
SDA hold time relative to the fall of SCL
0
-
3.45
μs
μs
Data hold time
Pulse width
Input waveform
Unit
twL
SCL pulse width for the L period
4.7
-
-
twH
SCL pulse width for the H period
4.0
-
-
μs
ton
SCL and SDA (input) rise time
-
-
1000
ns
conditions
tof
SCL and SDA (input) fall time
-
-
300
ns
Bus free time
tbuf
Time between STOP condition and START
4.7
-
-
μs
condition
High-speed mode
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Unit
SCL clock frequency
fsc1
SCL clock frequency
0
-
400
kHz
Data setup time
ts1
SCL setup time relative to the fall of SDA
0.6
-
-
μs
ts2
SDA setup time relative to the rise of SCL
100
-
-
ns
ts3
SCL setup time relative to the rise of SDA
0.6
-
-
μs
th1
SCL hold time relative to the fall of SDA
0.6
-
-
μs
th2
SDA hold time relative to the fall of SCL
0
-
0.9
μs
Data hold time
Pulse width
Input waveform
twL
SCL pulse width for the L period
1.3
-
-
μs
twH
SCL pulse width for the H period
0.6
-
-
μs
ton
SCL and SDA (input) rise time
-
-
300
ns
conditions
tof
SCL and SDA (input) fall time
-
-
300
ns
Bus free time
tbuf
Time between STOP and START conditions
1.3
-
-
μs
No.A1969-7/24
LV5223GR
2) I2C bus transfer method
Start and stop conditions
During data transfer operation using the I2C bus, SDA must basically be kept in constant state while SCL is “H” as
shown below.
SCL
SDA
ts2
th2
When data is not being transferred, both SCL and SDA are set in the “H” state.
When SCL=SDA is “H,” the start condition is established when SDA is changed from “H” to “L,” and access is started.
When SCL is “H,” the stop condition is established when SDA is changed from “L” to “H,” and access is ended.
STOP condition
START condition
SCL
SDA
ts3
th1
Data transfer and acknowledgement response
After the start condition has been established, the data is transferred one byte (8 bits) at a time.
Any number of bytes of data can be transferred continuously.
Each time the 8-bit data is transferred, the ACK signal is sent from the receive side to the send side. The ACK signal is
issued when SDA on the send side is released and SDA on the receive side is set to “L” immediately after fall of the
clock pulse at the SCL eighth bit of data transfer to “L.”
When the next 1-byte transfer is left in the receive state after sending the ACK signal from the receive side, the receive
side releases SDA at the fall of the SCL ninth clock.
In the I2C bus, there is no CE signal. In its place, a 7-bit slave address is assigned to each device, and the first byte of
transfer is assigned to the command (R/W) representing the 7-bit address and subsequent transfer direction. Note that
only write is valid in this IC. The 7-bit address is transferred sequentially starting with MSB, and the eighth bit is set to
“L” which indicates a write.
In the LV5223GP the slave address is specified as "1110101"
Start
M
S
B
Slave address
L
S
B
W
A
C
K
M
S
B
Resistor address
L
S
B
A
C
K
M
S
B
Data
L
S
B
A
C
K
Stop
SCL
SDA
No.A1969-8/24
LV5223GR
Serial mode setting
ADDRESS : 00h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
B2SW
G2SW
R2SW
B1SW
G1SW
R1SW
CPSW
STBY
default
0
0
0
0
0
0
0
0
D0
STBY
0
Standby
1
Active
D1
CPSW
0
OFF
1
ON
D2
R1SW
0
OFF
1
ON
D3
G1SW
0
OFF
1
ON
D4
B1SW
0
OFF
1
ON
D5
R2SW
0
OFF
1
ON
D6
G2SW
0
OFF
1
ON
D7
B2SW
0
OFF
1
ON
STBY setting
*Default
LED operation enabled by releasing STBY (LED can be operated by another power supply
Charge pump ON/OFF setting
*Default
RLED1 output setting
*Default
GLED1 output setting
*Default
BLED1 output setting
*Default
RLED2 output setting
*Default
GLED2 output setting
*Default
BLED2 output setting
*Default
No.A1969-9/24
LV5223GR
ADDRESS : 01h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
SCTEN1
-
-
R1[4]
R1[3]
R1[2]
R1[1]
R1[0]
default
0
0
0
0
0
0
0
0
D4
D3
D2
D1
D0
current value (mA)
0
0
0
0
0
0.5
0
0
0
0
1
1.0
0
0
0
1
0
1.5
0
0
0
1
1
2.0
0
0
1
0
0
2.5
0
0
1
0
1
3.0
0
0
1
1
0
3.5
0
0
1
1
1
4.0
0
1
0
0
0
4.5
0
1
0
0
1
5.0
0
1
0
1
0
5.5
0
1
0
1
1
6.0
0
1
1
0
0
6.5
0
1
1
0
1
7.0
0
1
1
1
0
7.5
0
1
1
1
1
8.0
1
0
0
0
0
8.5
1
0
0
0
1
9.0
1
0
0
1
0
9.5
1
0
0
1
1
10.0
1
0
1
0
0
10.5
1
0
1
0
1
11.0
1
0
1
1
0
11.5
1
0
1
1
1
12.0
1
1
0
0
0
12.5
1
1
0
0
1
13.0
1
1
0
1
0
13.5
1
1
0
1
1
14.0
1
1
1
0
0
14.5
1
1
1
0
1
15.0
1
1
1
1
0
15.5
1
1
1
1
1
16.0
D7
SCTEN1
0
RGB1 SCTL valid
1
RGB1 SCTL non valid
RLED1 current value setting
*Default
RGB1 SCTL signal enable
*Default
No.A1969-10/24
LV5223GR
ADDRESS : 02h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
-
G1[4]
G1[3]
G1[2]
G1[1]
G1[0]
default
0
0
0
0
0
0
0
0
D4
D3
D2
D1
D0
current value (mA)
0
0
0
0
0
0.5
0
0
0
0
1
1.0
0
0
0
1
0
1.5
0
0
0
1
1
2.0
0
0
1
0
0
2.5
0
0
1
0
1
3.0
0
0
1
1
0
3.5
0
0
1
1
1
4.0
0
1
0
0
0
4.5
0
1
0
0
1
5.0
0
1
0
1
0
5.5
0
1
0
1
1
6.0
0
1
1
0
0
6.5
0
1
1
0
1
7.0
0
1
1
1
0
7.5
0
1
1
1
1
8.0
1
0
0
0
0
8.5
1
0
0
0
1
9.0
1
0
0
1
0
9.5
1
0
0
1
1
10.0
1
0
1
0
0
10.5
1
0
1
0
1
11.0
1
0
1
1
0
11.5
1
0
1
1
1
12.0
1
1
0
0
0
12.5
1
1
0
0
1
13.0
1
1
0
1
0
13.5
1
1
0
1
1
14.0
1
1
1
0
0
14.5
1
1
1
0
1
15.0
1
1
1
1
0
15.5
1
1
1
1
1
16.0
GLED1 current value setting
*Default
No.A1969-11/24
LV5223GR
ADDRESS : 03h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
-
B1[4]
B1[3]
B1[2]
B1[1]
B1[0]
default
0
0
0
0
0
0
0
0
D4
D3
D2
D1
D0
current value (mA)
0
0
0
0
0
0.5
0
0
0
0
1
1.0
0
0
0
1
0
1.5
0
0
0
1
1
2.0
0
0
1
0
0
2.5
0
0
1
0
1
3.0
0
0
1
1
0
3.5
0
0
1
1
1
4.0
0
1
0
0
0
4.5
0
1
0
0
1
5.0
0
1
0
1
0
5.5
0
1
0
1
1
6.0
0
1
1
0
0
6.5
0
1
1
0
1
7.0
0
1
1
1
0
7.5
0
1
1
1
1
8.0
1
0
0
0
0
8.5
1
0
0
0
1
9.0
1
0
0
1
0
9.5
1
0
0
1
1
10.0
1
0
1
0
0
10.5
1
0
1
0
1
11.0
1
0
1
1
0
11.5
1
0
1
1
1
12.0
1
1
0
0
0
12.5
1
1
0
0
1
13.0
1
1
0
1
0
13.5
1
1
0
1
1
14.0
1
1
1
0
0
14.5
1
1
1
0
1
15.0
1
1
1
1
0
15.5
1
1
1
1
1
16.0
BLED1 current value setting
*Default
No.A1969-12/24
LV5223GR
ADDRESS : 04h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
SCTEN2
-
-
R2[4]
R2[3]
R2[2]
R2[1]
R2[0]
default
0
0
0
0
0
0
0
0
D4
D3
D2
D1
D0
current value (mA)
0
0
0
0
0
0.5
0
0
0
0
1
1.0
0
0
0
1
0
1.5
0
0
0
1
1
2.0
0
0
1
0
0
2.5
0
0
1
0
1
3.0
0
0
1
1
0
3.5
0
0
1
1
1
4.0
0
1
0
0
0
4.5
0
1
0
0
1
5.0
0
1
0
1
0
5.5
0
1
0
1
1
6.0
0
1
1
0
0
6.5
0
1
1
0
1
7.0
0
1
1
1
0
7.5
0
1
1
1
1
8.0
1
0
0
0
0
8.5
1
0
0
0
1
9.0
1
0
0
1
0
9.5
1
0
0
1
1
10.0
1
0
1
0
0
10.5
1
0
1
0
1
11.0
1
0
1
1
0
11.5
1
0
1
1
1
12.0
1
1
0
0
0
12.5
1
1
0
0
1
13.0
1
1
0
1
0
13.5
1
1
0
1
1
14.0
1
1
1
0
0
14.5
1
1
1
0
1
15.0
1
1
1
1
0
15.5
1
1
1
1
1
16.0
D7
SCTEN2
0
RGB2 SCTL valid
1
RGB2 SCTL non valid
RLED2 current value setting
*Default
RGB2 SCTL signal enable
*Default
No.A1969-13/24
LV5223GR
ADDRESS : 05h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
-
G2[4]
G2[3]
G2[2]
G2[1]
G2[0]
default
0
0
0
0
0
0
0
0
D4
D3
D2
D1
D0
current value (mA)
0
0
0
0
0
0.5
0
0
0
0
1
1.0
0
0
0
1
0
1.5
0
0
0
1
1
2.0
0
0
1
0
0
2.5
0
0
1
0
1
3.0
0
0
1
1
0
3.5
0
0
1
1
1
4.0
0
1
0
0
0
4.5
0
1
0
0
1
5.0
0
1
0
1
0
5.5
0
1
0
1
1
6.0
0
1
1
0
0
6.5
0
1
1
0
1
7.0
0
1
1
1
0
7.5
0
1
1
1
1
8.0
1
0
0
0
0
8.5
1
0
0
0
1
9.0
1
0
0
1
0
9.5
1
0
0
1
1
10.0
1
0
1
0
0
10.5
1
0
1
0
1
11.0
1
0
1
1
0
11.5
1
0
1
1
1
12.0
1
1
0
0
0
12.5
1
1
0
0
1
13.0
1
1
0
1
0
13.5
1
1
0
1
1
14.0
1
1
1
0
0
14.5
1
1
1
0
1
15.0
1
1
1
1
0
15.5
1
1
1
1
1
16.0
GLED2 current value setting
*Default
No.A1969-14/24
LV5223GR
ADDRESS : 06h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
-
B2[4]
B2[3]
B2[2]
B2[1]
B2[0]
default
0
0
0
0
0
0
0
0
D4
D3
D2
D1
D0
current value (mA)
0
0
0
0
0
0.5
0
0
0
0
1
1.0
0
0
0
1
0
1.5
0
0
0
1
1
2.0
0
0
1
0
0
2.5
0
0
1
0
1
3.0
0
0
1
1
0
3.5
0
0
1
1
1
4.0
0
1
0
0
0
4.5
0
1
0
0
1
5.0
0
1
0
1
0
5.5
0
1
0
1
1
6.0
0
1
1
0
0
6.5
0
1
1
0
1
7.0
0
1
1
1
0
7.5
0
1
1
1
1
8.0
1
0
0
0
0
8.5
1
0
0
0
1
9.0
1
0
0
1
0
9.5
1
0
0
1
1
10.0
1
0
1
0
0
10.5
1
0
1
0
1
11.0
1
0
1
1
0
11.5
1
0
1
1
1
12.0
1
1
0
0
0
12.5
1
1
0
0
1
13.0
1
1
0
1
0
13.5
1
1
0
1
1
14.0
1
1
1
0
0
14.5
1
1
1
0
1
15.0
1
1
1
1
0
15.5
1
1
1
1
1
16.0
BLED2 current value setting
*Default
No.A1969-15/24
LV5223GR
ADDRESS : 07h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
FOUT1[2]
FOUT1[1]
FOUT1[0]
FIN1[2]
FIN1[1]
FIN1[0]
default
0
0
0
0
0
0
0
0
D2
D1
D0
FIN1
0
0
0
No slope
0
0
1
Slope 1/32
0
1
0
1/16
0
1
1
1/8
1
0
0
1/4
1
0
1
1/2
1
1
0
3/4
1
1
1
Max slope
D5
D4
D3
FOUT1
0
0
0
No slope
0
0
1
Slope 1/32
0
1
0
1/16
0
1
1
1/8
1
0
0
1/4
1
0
1
1/2
1
1
0
3/4
1
1
1
Max slope
RGB1 FIN slope setting
*Default
Max. slope is 1/2 of automatic ON/OFF period of RGB1
RGB1 FOUT slope setting
*Default
Max. slope is 1/2 of automatic ON/OFF period of RGB1
ADDRESS : 08h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
FOUT2[2]
FOUT2[1]
FOUT2[0]
FIN2[2]
FIN2[1]
FIN2[0]
default
0
0
0
0
0
0
0
0
D2
D1
D0
FIN2
0
0
0
No slope
0
0
1
Slope 1/32
0
1
0
1/16
0
1
1
1/8
1
0
0
1/4
1
0
1
1/2
1
1
0
3/4
1
1
1
Max slope
D5
D4
D3
FOUT2
0
0
0
No slope
0
0
1
Slope 1/32
0
1
0
1/16
0
1
1
1/8
1
0
0
1/4
1
0
1
1/2
1
1
0
3/4
1
1
1
Max slope
RGB2 FIN slope setting
*Default
Max. slope is 1/2 of automatic ON/OFF period of RGB2
RGB2 FOUT slope setting
*Default
Max. slope is 1/2 of automatic ON/OFF period of RGB2
No.A1969-16/24
LV5223GR
ADDRESS : 09h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
SYNC
GR1M1
GRON1
AT1[2]
AT1[1]
AT1[0]
default
0
0
0
0
0
0
0
0
D2
D1
D0
AT1
0
0
0
0.262sec
0
0
1
0.524sec
0
1
0
1.049sec
0
1
1
2.097sec
1
0
0
4.194sec
1
0
1
8.389sec
1
1
×
-
RGB1 automatic ON/OFF function setting
*Default
D3
GRON1
RGB1 automatic ON/OFF function setting
0
OFF
1
ON
D4
GR1M1
0
OFF
1
ON
D5
SYNC
0
OFF
execution setting of RGB2 are done as well as RGB1
1
ON
*Default
*Default
RGB1 is executed one time of the gradation.
*Default
Automatic operation ON/OFF cycle and the gradation.
ADDRESS : 0ah
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
-
GR1M2
GRON2
AT2[2]
AT2[1]
AT2[0]
default
0
0
0
0
0
0
0
0
D2
D1
D0
AT2
0
0
0
0.262sec
0
0
1
0.524sec
0
1
0
1.049sec
0
1
1
2.097sec
1
0
0
4.194sec
1
0
1
8.389sec
1
1
×
-
D3
GRON1
0
OFF
1
ON
D4
GR1M1
0
OFF
1
ON
RGB2 automatic ON/OFF function setting
*Default
RGB2 automatic ON/OFF function setting
*Default
RGB2 is executed one time of the gradation.
*Default
No.A1969-17/24
LV5223GR
ADDRESS : 0bh
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
R1Aoff[5]
R1Aoff[4]
R1Aoff[3]
R1Aoff[2]
R1Aoff[1]
R1Aoff[0]
default
0
0
0
0
0
0
0
0
D5-0 RLED1 automatic OFF position setting (default: ALL0)
ADDRESS : 0ch
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
R1Aon[5]
R1Aon[4]
R1Aon[3]
R1Aon[2]
R1Aon[1]
R1Aon[0]
default
0
0
0
0
0
0
0
0
D5-0 RLED1 automatic OFF position setting (default: ALL0)
When R1Aon=R1Aoff, all the periods off.
LED control output waveform (RLED1). Same for GLED1, BLED1, GLED2, GLED2 and BLED2
When D5 to D0 ALL0: Clock 0 rise position.
When D5 to D0 ALL1: Clock 63 rise position.
R1on R1Aon[5:0]=000000(00h)
For R1off R1Aoff[5:0]=000101(05h)
64 counts
CLK for gradation
0
3
2
1
4
5
63
0
59 counts
5 counts
RLED1
OFF period
ON period
R1off
R1on
ADDRESS : 0dh
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
G1Aoff[5]
G1Aoff[4]
G1Aoff[3]
G1Aoff[2]
G1Aoff[1]
G1Aoff[0]
default
0
0
0
0
0
0
0
0
D5-0 GLED1 automatic OFF position setting (default: ALL0)
ADDRESS : 0eh
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
G1Aon[5]
G1Aon[4]
G1Aon[3]
G1Aon[2]
G1Aon[1]
G1Aon[0]
default
0
0
0
0
0
0
0
0
D5-0 GLED1 automatic OFF position setting (default: ALL0)
When G1Aon=G1Aoff, all the periods off.
No.A1969-18/24
LV5223GR
ADDRESS : 0fh
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
B1Aoff[5]
B1Aoff[4]
B1Aoff[3]
B1Aoff[2]
B1Aoff[1]
B1Aoff[0]
default
0
0
0
0
0
0
0
0
D5-0 BLED1 automatic OFF position setting (default: ALL0)
ADDRESS : 10h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
B1Aon[5]
B1Aon[4]
B1Aon[3]
B1Aon[2]
B1Aon[1]
B1Aon[0]
default
0
0
0
0
0
0
0
0
D5-0 BLED1 automatic OFF position setting (default: ALL0)
When B1Aon=B1Aoff, all the periods off.
ADDRESS : 11h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
R2Aoff[5]
R2Aoff[4]
R2Aoff[3]
R2Aoff[2]
R2Aoff[1]
R2Aoff[0]
default
0
0
0
0
0
0
0
0
D5-0 RLED2 automatic OFF position setting (default: ALL0)
ADDRESS : 12h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
R2Aon[5]
R2Aon[4]
R2Aon[3]
R2Aon[2]
R2Aon[1]
R2Aon[0]
default
0
0
0
0
0
0
0
0
D5-0 RLED2 automatic OFF position setting (default: ALL0)
When R2Aon=R2Aoff, all the periods off.
ADDRESS : 13h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
G2Aoff[5]
G2Aoff[4]
G2Aoff[3]
G2Aoff[2]
G2Aoff[1]
G2Aoff[0]
default
0
0
0
0
0
0
0
0
D5-0 GLED2 automatic OFF position setting (default: ALL0)
ADDRESS : 14h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
G2Aon[5]
G2Aon[4]
G2Aon[3]
G2Aon[2]
G2Aon[1]
G2Aon[0]
default
0
0
0
0
0
0
0
0
D5-0 GLED2 automatic OFF position setting (default: ALL0)
When G2Aon=G2Aoff, all the periods off.
No.A1969-19/24
LV5223GR
ADDRESS : 15h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
B2Aoff[5]
B2Aoff[4]
B2Aoff[3]
B2Aoff[2]
B2Aoff[1]
B2Aoff[0]
default
0
0
0
0
0
0
0
0
D5-0 BLED2 automatic OFF position setting (default: ALL0)
ADDRESS : 16h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
-
-
B2Aon[5]
B2Aon[4]
B2Aon[3]
B2Aon[2]
B2Aon[1]
B2Aon[0]
default
0
0
0
0
0
0
0
0
D5-0 BLED2 automatic OFF position setting (default: ALL0)
When B2Aon=B2Aoff, all the periods off.
ADDRESS : 17h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
GTO3EN
GPO2EN
GPO1EN
-
-
GPO3
GPO2
GPO1
default
0
0
0
0
0
0
0
0
D0
GPO1
GPO1(LED3) output setting
0
GPO1 (LED3) output: Open when GPO1EN=0, low when GPO1EN=1
1
GPO1 (LED3) output: LED-Drv ON when GPO1EN=0, high when GPO1EN=1
D1
GPO2
GPO2(LED4) output setting
0
GPO2 (LED4) output: Open when GPO2EN=0, low when GPO2EN=1
1
GPO2 (LED4) output: LED-Drv ON when GPO2EN=0, high when GPO2EN=1
D2
GPO3
GPO3 (LED5) output: Open when GPO3EN=0, low when GPO3EN=1
1
GPO3 (LED5) output: LED-Drv ON when GPO3EN=0, high when GPO3EN=1
GPO1EN
*Default
GPO3(LED5) output setting
0
D5
*Default
*Default
GPO1(LED3) output
0
When GPO1 (LED3) output is used as LED-Drv
Setting for using GPO or LED-Drv
1
When GPO1 (LED3) output is used as GPO
*Default
D6
GPO2EN
GPO2(LED4) output
0
When GPO2 (LED4) output is used as LED-Drv
Setting for using GPO or LED-Drv
1
When GPO2 (LED4) output is used as GPO
*Default
D7
GPO3EN
GPO3(LED5) output
0
When GPO3 (LED5) output is used as LED-Drv
Setting for using GPO or LED-Drv
1
When GPO3 (LED5) output is used as GPO
*Default
*GPO1EN must be set to 1 without fail when the GPO1 (LED3) pin is to be used as GPO.
When GPO1EN is set to 1, do not apply a voltage higher than the VDD voltage to the GPO1 (LED3) pin.
The same applies to the GPO2 (LED4) and GPO3 (LED5) pins.
No.A1969-20/24
LV5223GR
ADDRESS : 18h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
FCTENR2
-
-
-
FCTR2[3]
FCTR2[2]
FCTR2[1]
FCTR2[0]
default
0
0
0
0
0
0
0
0
D3
D2
D1
D0
Current value(mA)
0
0
0
0
2.8
0
0
0
1
5.6
0
0
1
0
8.4
0
0
1
1
11.2
0
1
0
0
14.0
0
1
0
1
16.8
0
1
1
0
19.6
0
1
1
1
22.4
1
0
0
0
25.2
1
0
0
1
28.0
1
0
1
0
30.8
1
0
1
1
33.6
1
1
0
0
36.4
1
1
0
1
39.2
1
1
1
0
42.0
1
1
1
1
44.8
D7
FCTENR2
0
FCTL non valid
1
FCTL valid
Strobe mode: RLED2 current level established when FCTL is high.
*Default
RLED2 FCTL signal enable
*Default
ADDRESS : 19h
D7
D6
D5
D4
D3
D2
D1
D0
resister name
FCTENG2
-
-
-
FCTG2[3]
FCTG2[2]
FCTG2[1]
FCTG2[0]
default
0
0
0
0
0
0
0
0
D3
D2
D1
D0
Current value(mA)
0
0
0
0
2.8
0
0
0
1
5.6
0
0
1
0
8.4
0
0
1
1
11.2
0
1
0
0
14.0
0
1
0
1
16.8
0
1
1
0
19.6
0
1
1
1
22.4
1
0
0
0
25.2
1
0
0
1
28.0
1
0
1
0
30.8
1
0
1
1
33.6
1
1
0
0
36.4
1
1
0
1
39.2
1
1
1
0
42.0
1
1
1
1
44.8
D7
FCTENG2
0
FCTL non valid
1
FCTL valid
Strobe mode: GLED2 current level established when FCTL is high.
*Default
GLED2 FCTL signal enable
*Default
No.A1969-21/24
LV5223GR
Precautions for serial transmission and usage note
* ON operation of the charge pump must be performed when the LED is off.
* Do not turn ON the LED for 800µs typ. (soft start time) after the charge pump has been turned on.
* When the fade operation of LED is performed, turn off the charge pump after the fade-out has been completed.
* Gradation level must be selected without fail when gradation is OFF.
* When the charge pump is operating, use the LED driver in such a way that the total current flowing to the LEDs.
* Even in the strobe mode (FCTL=H), the gradation operation is performed for RLED2 and GLED2 when RLED2 and
GLED2 are set to gradation ON.
* Even in the strobe mode (FCTL=H), current flows to RLED2 and GLED2 in synchronization with the SCTL signal
when SCTL is valid.
* When the LED pins are not to be used
When LEDs are not connected to the LED pins, connect the LED driver pins to VBAT or GND.
* Precaution when using the SCTL pin or FCTL pin
When the SCTL pin or FCTL pin is set to high, current flows to the SCTL or FCTL input circuit.
(This is also true in the STBY or reset mode.)
When the pin is not going to be used, it must be set to low without fail.
* By default, the GP01 (LED3) pin is left open.
When the GP01 (LED3) pin is to be set high by default, connect a pull-up resistor to the pin.
Conversely, when the GP01 (LED3) pin is to be set low by default, connect a pull-down resistor to the pin.
Connect pull-up or pull-down resistors to the GP02 (LED4) and GP03 (LED5) pins as well in the same way.
No.A1969-22/24
LV5223GR
LV5223GR serial map
• Table upper row: Register name
Table the lower: Default value
Register address
A7
00h
0
A6
0
A5
0
A4
0
A3
A2
0
0
data
A1
0
A0
0
01h
0
0
0
0
0
0
0
1
02h
0
0
0
0
0
0
1
0
03h
04h
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
05h
0
0
0
0
0
1
0
1
06h
0
0
0
0
0
1
1
0
07h
08h
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
09h
0
0
0
0
1
0
0
1
0ah
0
0
0
0
1
0
1
0
0bh
0ch
0
0
0
0
0
0
0
0
1
1
0
1
1
0
1
0
0dh
0
0
0
0
1
1
0
1
0eh
0
0
0
0
1
1
1
0
0fh
10h
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
11h
0
0
0
1
0
0
0
1
12h
0
0
0
1
0
0
1
0
13h
14h
0
0
0
0
0
0
1
1
0
0
0
1
1
0
1
0
15h
0
0
0
1
0
1
0
1
16h
0
0
0
1
0
1
1
0
17h
18h
19h
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
Register address
1
0
0
1
0
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
B2SW
G2SW
R2SW
B1SW
G1SW
R1SW
CPSW
STBY
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SCTEN1
×
×
0
0
0
×
×
×
0
0
0
×
×
×
0
0
0
×
×
×
0
0
0
×
×
×
0
0
0
×
×
×
0
0
0
×
×
0
0
×
×
R1[4:0]
0
0
0
0
G1[4:0]
0
0
0
0
0
0
0
0
0
0
FIN1[2:0]
0
0
0
GRON1
0
0
0
0
0
×
×
×
GR1M2
GRON2
0
0
0
0
0
×
×
0
0
0
×
×
0
0
×
×
0
0
×
×
0
0
×
×
0
0
×
×
0
0
×
×
0
0
×
×
0
0
×
×
0
0
×
×
0
GPO3EN
0
0
FIN2[2:0]
GR1M1
×
0
FOUT2[2:0]
0
0
0
FOUT1[2:0]
SYNC
×
0
B2[4:0]
0
0
0
G2[4:0]
×
×
0
R2[4:0]
0
0
0
B1[4:0]
×
×
0
0
0
0
AT1[2:0]
0
0
0
AT2[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R1Aoff[5:0]
0
0
0
R1Aon[5:0]
0
0
0
G1Aoff[5:0]
0
0
0
0
0
G1Aon[5:0]
0
B1Aoff[5:0]
0
0
0
B1Aon[5:0]
0
0
0
R2Aoff[5:0]
0
0
0
0
0
R2Aon[5:0]
0
G2Aoff[5:0]
0
0
0
G2Aon[5:0]
0
0
0
B2Aoff[5:0]
0
0
0
0
0
0
0
0
0
0
GPO2EN
GPO1EN
×
×
GPO3
GPO2
GPO1
0
0
0
0
B2Aon[5:0]
0
0
0
0
FCTENR2
×
×
×
0
0
0
0
FCTENG2
×
×
×
0
0
0
0
FCTR2[3:0]
0
0
0
0
0
0
0
0
Data
No.A1969-23/24
LV5223GR
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products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition
ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd.
products described or contained herein.
SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all
semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or
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to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt
safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not
limited to protective circuits and error prevention circuits for safe design, redundant design, and structural
design.
In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are
controlled under any of applicable local export control laws and regulations, such products may require the
export license from the authorities concerned in accordance with the above law.
No part of this publication may be reproduced or transmitted in any form or by any means, electronic or
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without the prior written consent of SANYO Semiconductor Co.,Ltd.
Any and all information described or contained herein are subject to change without notice due to
product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the
SANYO Semiconductor Co.,Ltd. product that you intend to use.
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed
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Upon using the technical information or products described herein, neither warranty nor license shall be granted
with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third
party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's
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This catalog provides information as of July, 2011. Specifications and information herein are subject
to change without notice.
PS No.A1969-24/24