Product Brief OPTICAL TRANSPORT & DATACOM PRODUCTS SMI4028 45 to 49 Gbps 16:2 Multiplexer/CMU with DQPSK Precoder Product Description SMI4028 is a 16:2 Multiplexer with on chip Clock Multiplier Unit and DQPSK Precoder that support the data rate from 45 to 49Gbps. Product Highlights 4 User-Enabled DQPSK Precoder Function 4 SFI-5+Compliant FIFO and Deskew functions 4 Dual Ground-Referenced High-Speed Single-Ended Output Ports 0.3 to 0.7 Volt pp SE Output Level (adjustable for reduced power) 14 psec (typical) Rise/Fall Times 4.8 psec p-p total jitter (typical) 1.0 psec (rms) total jitter Data-to-Data Skew Adjustments for Each Output Data Lane; +/- 0.25UI GPPO Connection; 22.5 to 24.5 Gbaud (fBaud) 4 High-Speed Differential Clock Outputs with Highly Stable Clock-Data Skew and Low Phase Noise Full (23.5 nominal) and Half-Rate (11.75 GHz nominal) CML Clocks Skew control of +/- 0.5UI on Half-Rate Clock 0.8 Volt pp Differential Output Level SONET-compliant Clock Multiplier Unit (CMU) with VCO User Selectable Reference Clock Input Ports Reference Clock Clean-Up Loop Circuitry On-Chip PRWS Error Checker and Pattern Generator: 27-1 or 231-1 industry-standard patterns On-chip error counter for measuring BER Lane-by-lane error checking 4 SPI Control Interface Supports 1.2V or 1.8V LVCMOS 4 Temperature Sense Output Voltage 4 Dual-Power Supply Voltages: +1.2 or +1.8V and -2.8V 4 Low Power Consumption: 2.9 Watts (typical) 4 4 4 4 Applications 4 OC768/OTU3 Modules and Transponders 4 MSPP, ADM and Cross-connects 4 IP Routers and Switches W W W .SE MTE CH .COM SIERRA MONOLITHICS Product Brief SMI4028 Block Diagram — 16:2 Multiplexer/CMU with DQPSK Precoder RESP Bias Current Control Data Select PRBS Error Checker . . . 17 Channel DLL Array TXDATA[1]P/N TXDATA[0]P/N 17xN Channel FIFO Array DATA_0 WRCLK_0 DLLCLK_SEL 2:1 16: 1 ∆φ TXDATAOUT[1] TXDATA1 _EN 1, ½ HSCLK0_PH[7:0] DAC HSCLK0_ LVL [7:0] 1, ½ DAC HSCLK1_ LVL [7:0] Clock Multiplier Unit (CMU) TXMCLKP/N HSCLK0 _EN DAC HSCLK[1]P/N ∆φ HSCLK1_FSEL HSCLK1_PH[7:0] HSCLK[0]P/N ∆φ HSCLK0_FSEL X4 PLL TXDCKP/N TXDATAOUT[0] DAC TXDATA1_LVL[7:0] PRBS Block TXDSCP/N ∆φ DAC TXDATA1_PH [7:0] Fixed Data PRBS Pattern 27 /231 TXDATA0 _EN DAC TXDATA0_PH[7:0] Mux .. . TXDATA_SEL[1:0] DQPSK Precoder TXDATA[14]P/N DAC TXDATA0_LVL [7:0] Deskew DATA_15 WRCLK_15 HSCLK1 _EN DAC SFI-5 Transmit Controller DESKEW _EN TXOOA SFI-5 Block ADC TEMP SPI Subsystem TXLF_N R C2 TXCKSRCP/N 2:1 PHSERR_EN PHSERR_UPP/N PHSERR_DNP/N Phase Detect REFPLL P/N TXREFCLKP/N SPI_EN_N SPI_CLK SPI_DIN SPI_DOUT VCC Digital -1.6V Reference REFN16_OUT REFN16_IN VEE Digital VDD Digital VEE -1.6V Regulator VCC VDD_SFI5 Diode Temp. Sensor VCC_VCO GTEMP_P GTEMP_N VEE_VCO TX_TEMP PTAT Temp. Sensor REFSEL Ref Select Block RESET_N Control DACs Control logic Status FRAME_EPOCH _EN Deskew Correlator VDD Control Frame Header Acquistion FRAME_LOCK TXLF_P C1 CMU_LOCK TXMCLK_EN FRAME_EPOCH 1.0 K Mux Block PRECODER_EN CMU Block TXDATA[15]P/N Select Resistor RESN Interface Definitions SFI5 compatabile I/O LVCMOS (1.2, 1.8V) GND referenced CML AC coupled CML Sierra Monolithics Inc. is now part of Semtech Incorporated. To view the most current product specifications and datasheets, contact your local Semtech Field Applications Engineer. W W W .SE MTE CH .COM SIERRA MONOLITHICS SMI4028-PB