74LCX74 LOW VOLTAGE CMOS DUAL D-TYPE FLIP FLOP WITH 5V TOLERANT INPUTS ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 5V TOLERANT INPUTS HIGH SPEED : fMAX = 150 MHz (MAX.) at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V PCI BUS LEVELS GUARANTEED AT 24 mA BALANCED PROPAGATION DELAYS: tPLH ≅ tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 2.0V to 3.6V (1.5V Data Retention) PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 74 LATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015); MM > 200V DESCRIPTION The 74LCX74 is a low voltage CMOS DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for inputs. SOP TSSOP ORDER CODES PACKAGE TUBE T&R SOP TSSOP 74LCX74M 74LCX74MTR 74LCX74TTR A signal on the D INPUT is transferred to the Q OUTPUT during the positive going transition of the clock pulse. CLR and PR are independent of the clock and accomplished by a low setting on the appropriate input. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. PIN CONNECTION AND IEC LOGIC SYMBOLS September 2001 1/11 74LCX74 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL 1, 13 2, 12 3, 11 4, 10 5, 9 6, 8 7 14 1CLR, 2CLR 1D, 2D 1CK, 2CK 1PR, 2PR 1Q, 2Q 1Q, 2Q GND VCC NAME AND FUNCTION Asynchronous Reset - Direct Input Data Inputs Clock Input (LOW to HIGH, Edge Triggered) Asynchronous Set - Direct Input True Flip-Flop Outputs Complement Flip-Flop Outputs Ground (0V) Positive Supply Voltage TRUTH TABLE INPUTS OUTPUTS FUNCTION CLR PR D CK Q Q L H L H L L X X X X X X L H H H L H H H L L H H H H H L H H X Qn Qn X : Don’t Care 2/11 CLEAR PRESET NO CHANGE 74LCX74 LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays ABSOLUTE MAXIMUM RATINGS Symbol V CC Parameter Value Unit Supply Voltage -0.5 to +7.0 V VI DC Input Voltage -0.5 to +7.0 V VO DC Output Voltage (V CC = 0V) VO DC Output Voltage (High or Low State) (note 1) IIK DC Input Diode Current IOK DC Output Diode Current (note 2) -0.5 to +7.0 V -0.5 to VCC + 0.5 - 50 V mA - 50 mA IO DC Output Current ± 50 mA ICC DC Supply Current per Supply Pin ± 100 mA IGND DC Ground Current per Supply Pin Tstg Storage Temperature TL Lead Temperature (10 sec) ± 100 mA -65 to +150 °C 300 °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) IO absolute maximum rating must be observed 2) VO < GND RECOMMENDED OPERATING CONDITIONS Symbol V CC Parameter Supply Voltage (note 1) Value Unit 2.0 to 3.6 V VI Input Voltage 0 to 5.5 V VO Output Voltage (V CC = 0V) 0 to 5.5 V VO Output Voltage (High or Low State) 0 to VCC V ± 24 mA IOH, IOL IOH, IOL Top dt/dv High or Low Level Output Current (V CC = 3.0 to 3.6V) High or Low Level Output Current (V CC = 2.7V) Operating Temperature Input Rise and Fall Time (note 2) ± 12 mA -55 to 125 °C 0 to 10 ns/V 1) Truth Table guaranteed: 1.5V to 3.6V 2) VIN from 0.8V to 2V at VCC = 3.0V 3/11 74LCX74 DC SPECIFICATIONS Test Condition Symbol VIH VIL VOH Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Ioff ICC ∆ICC Input Leakage Current Power Off Leakage Current Quiescent Supply Current ICC incr. per Input Min. Max. 2.0 -55 to 125 °C Min. Unit Max. 2.0 V 2.7 to 3.6 0.8 0.8 2.7 to 3.6 I O=-100 µA VCC-0.2 VCC-0.2 2.7 IO=-12 mA 2.2 2.2 IO=-18 mA 2.4 2.4 IO=-24 mA 2.2 V V 2.2 2.7 to 3.6 IO=100 µA 0.2 0.2 2.7 IO=12 mA 0.4 0.4 IO=16 mA 0.4 0.4 IO=24 mA 0.55 0.55 2.7 to 3.6 VI = 0 to 5.5V ±5 ±5 µA 0 V I or VO = 5.5V 10 10 µA 2.7 to 3.6 VI = VCC or GND VI or VO= 3.6 to 5.5V 10 10 ± 10 ± 10 2.7 to 3.6 VIH = VCC - 0.6V 500 500 3.0 II -40 to 85 °C VCC (V) 3.0 VOL Value V µA µA DYNAMIC SWITCHING CHARACTERISTICS Test Condition Symbol VOLP V OLV Parameter Dynamic Low Level Quiet Output (note 1) TA = 25 °C VCC (V) 3.3 Value Min. CL = 50pF VIL = 0V, V IH = 3.3V Typ. 0.8 -0.8 Unit Max. V 1) Number of outputs defined as ”n”. Measured with ”n-1” outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. 4/11 74LCX74 AC ELECTRICAL CHARACTERISTICS Test Conditi on Symbol Parameter VCC (V) tPLH tPHL Propagation Delay Time (CK to Q or Q) tPLH tPHL Propagation Delay Time (PR or CLR to Q or Q) Setup Time, HIGH or LOW level D to CK 2.7 3.0 to 3.6 2.7 tS th Hold Time, HIGH or LOW level D to CK tW CK Pulse Width, HIGH or LOW PR or CLR Pulse Width, LOW Recovery Time PR or CLR to CK trec fMAX tOSLH tOSHL Clock Pulse Frequency Output To Output Skew Time (note1, 2) CL (pF) RL (Ω) Value ts = t r (ns) 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 50 500 2.5 2.7 3.0 to 3.6 50 500 2.7 50 3.0 to 3.6 50 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 2.7 3.0 to 3.6 -40 to 85 °C -55 to 125 °C Min. Max. Min. Max. 1.5 1.5 1.5 8.0 7.0 8.0 1.5 1.5 1.5 9.2 8.0 9.2 1.5 7.0 1.5 8.0 Unit ns ns 2.5 2.5 1.5 1.5 3.0 3.5 3.5 1.5 1.5 4.0 3.0 4.0 2.5 0 0 0 0 ns 500 2.5 150 150 MHz 500 2.5 1.0 ns ns ns 1.0 ns 1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the same direction, either HIGH or LOW (tOSLH = | tPLHm - tPLHn|, tOSHL = | tPHLm - tPHLn|) 2) Parameter guaranteed by design CAPACITIVE CHARACTERISTICS Test Condition Symbol Parameter Value TA = 25 °C VCC (V) Min. Typ. CIN Input Capacitance 3.3 VIN = 0 to VCC 6 CPD Power Dissipation Capacitance (note 1) 3.3 fIN = 10MHz V IN = 0 or VCC 40 Unit Max. pF pF 1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/2 (per Fli p-Flop) 5/11 74LCX74 TEST CIRCUIT C L = 50 pF or equivalent (includes jig and probe capacitance) R L = 500Ω or equivalent R T = ZOUT of pulse generator (typically 50Ω) WAVEFORM 1 : PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/11 74LCX74 WAVEFORM 2 : PROPAGATION DELAYS (f=1MHz; 50% duty cycle) 7/11 74LCX74 WAVEFORM 3 : RECOVERY TIMES (f=1MHz; 50% duty cycle) WAVEFORM 4 : PULSE WIDTH (f=1MHz; 50% duty cycle) 8/11 74LCX74 SO-14 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. MIN. TYP. 1.75 0.1 0.068 0.2 a2 MAX. 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45° (typ.) D 8.55 8.75 0.336 0.344 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 7.62 0.300 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M S 0.68 0.026 8° (max.) PO13G 9/11 74LCX74 TSSOP14 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. MAX. 1.2 A1 0.05 A2 0.8 b 0.047 0.15 0.002 0.004 0.006 1.05 0.031 0.039 0.041 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 D 4.9 5 5.1 0.193 0.197 0.201 E 6.2 6.4 6.6 0.244 0.252 0.260 E1 4.3 4.4 4.48 0.169 0.173 0.176 1 e 0.65 BSC K 0° L 0.45 A 0.60 0.0256 BSC 8° 0° 0.75 0.018 8° 0.024 0.030 A2 A1 b e K c L E D E1 PIN 1 IDENTIFICATION 1 0080337D 10/11 74LCX74 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringe ment of patents or other righ ts of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this pub lication are subject to change without notice. Thi s pub lication supersedes and replaces all information previously supplied. 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