INTERSIL ISL6422EVEZ

ISL6422
®
Data Sheet
April 10, 2007
Dual Output LNB Supply and Control
Voltage Regulator with I2C Interface for
Advanced Satellite Set-Top Box Designs
The ISL6422 is a highly integrated voltage regulator and
interface IC, specifically designed for supplying power and
control signals from advanced satellite set-top box (STB)
modules to the low noise blocks (LNBs) of two antenna
ports. The device is consists of two independent
current-mode boost PWMs and two low-noise linear
regulators along with the circuitry required for 22kHz tone
generation, modulation and I2C device interface. The device
makes the total LNB supply design simple, efficient and
compact with low external component count.
Two independent current-mode boost converters provide the
linear regulators with input voltages that are set to the final
output voltages, plus typically 0.8V to insure minimum power
dissipation across each linear regulator. This maintains
constant voltage drops across each linear pass element
while permitting adequate voltage range for tone injection.
The final regulated output voltages are available at two
output terminals to support simultaneous operation of two
antenna ports for dual tuners. The outputs for each PWM
can be controlled in two ways:
• Full control from I2C using the VTOP1, VTOP2, VBOT1,
and VBOT12 bits, or
FN9190.1
Features
• Single Chip Power Solution
- True Dual Operation for 2-Tuner/2-Dish Applications
- Both Outputs May be Enabled Simultaneously at
Maximum Power
- Integrated DC/DC Converter and I2C Interface
• Switch-Mode Power Converter for Lowest Dissipation
- Boost PWMs with >92% Efficiency
- Selectable 13.3V or 18.3V Outputs
- Digital Cable Length Compensation (1V)
- I2C and Pin controllable output
• Output Back Bias Capability of 28V
• I2C Compatible Interface for Remote Device Control
• Four level Slave Address 0001 00XX
• 2.5V, 3.3V, 5V Logic Compatible
• External Pins to Toggle between V and H Polarization.
• Supports DiSEqC 2.0 Protocol
• Built-In Tone Oscillator Factory Trimmed to 22kHz
- Facilitates DiSEqC (EUTELSAT) Encoding
- External Modulation Input
• Internal Over-Temperature Protection and Diagnostics
• Internal OV, UV, Overload and Overtemp Flags
(Visible on I2C)
• Set the I2C to the lower range (13V/14V) and switch to the
higher range (18V/19V) with the SELVTOP1 or
SELVTOP2 pin.
• FLT Signal
All the functions on this IC are controlled via the I2C bus by
• Pb-Free Plus Anneal Available (RoHS Compliant)
writing 8-bit words onto the System Registers (SR). The
same register can be read back, and four bits per output will
report the diagnostic status. Separate enable commands sent
on the I2C bus provide independent standby mode control for
each PWM and linear combination, disabling the output into
shutdown mode. Each output channel is capable of providing
750mA of continuous current. The overcurrent limit can be
digitally programmed.
• LNB Short-Circuit Protection and Diagnostics
• QFN, EPTSSOP Packages
Applications
• LNB Power Supply and Control for Satellite Set-Top Box
Ordering Information
PART NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
The External modulation input EXTM1/2 can accept a
modulated Diseqc command and transfer it symmetrically to
the output. Alternatively, the EXTM1 or EXTM2 pin can be
used to modulate the continuous internal tone.
ISL6422ERZ
ISL6422ERZ
-20 to +85 40 Ld 6x6 QFN
ISL6422ERZ-T
ISL6422ERZ
-20 to +85 40 Ld 6x6 QFN L40.6x6
(Tape and Reel)
ISL6422EVEZ
ISL6422EVEZ -20 to+ 85 38 Ld EPTSSOP M38.173B
The FLT pin serves as an interrupt for the processor when
an over temperature, overcurrent or backwards overcurrent
fault conditions is detected by the LNB controller or when
both channels are disabled by the I2C EN bits set low. The
nature of the fault can be read of the I2C registers.
ISL6422EVEZ-T ISL6422EVEZ -20 to +85 38 Ld EPTSSOP M38.173B
(Tape and Reel)
1
L40.6x6
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6422
Pinouts
ISL6422
(38 LD EPTSSOP)
TOP VIEW
39
37
36
35
34
33
NC
TCAP2
SELVTOP2
TXT2
CS2
VSW2
NC
38
32
VOUT2
40
GATE2
PGND2
ISL6422
(40 LD QFN)
TOP VIEW
VSW2 2
37 SELVTOP2
31
VSW2 3
36 TCAP2
38 TXT2
CS2 1
GATE2 4
35 NC
EXTM2
1
30
VOUT2
PGND2 5
34 VOUT2
SGND
2
29
TDIN2
EXTM2 6
33 TDIN2
NC
3
28
TDOUT2
FLT
4
27
CPVOUT
SDA
5
SCL
6
ADDR0
7
26
ISL6422ERZ
CPSWOUT
25
CPSWIN
24
VCC
ADDR1
8
23
TDOUT1
EXTM1
9
22
TDIN1
2
16
17
18
19
20
AGND
VOUT1
VSW1
15
TCAP1
14
SELVTOP1
13
TXT1
12
CS1
11
NC
21
GATE1
10
PGND1
BYP
VOUT1
SGND 7
32 TDOUT2
FLT 8
31 CPVOUT
30 CPSWOUT
SDA 9
SCL 10
ISL6422EVEZ
29 CPSWIN
ADDR0 11
28 VCC
ADDR1 12
27 TDOUT1
EXTM1 13
26 TDIN1
BYP 14
25 VOUT1
PGND1 15
24 AGND
GATE1 16
23 TCAP1
VSW1 17
22 SELVTOP1
VSW1 18
21 NC
CS1 19
20 TXT1
FN9190.1
April 10, 2007
Block Diagram
17
12
Q
S
7
OLF2
ADDR0
OVERCURRENT
PROTECTION
LOGIC SCHEME 2
OC1
OUVF2
DCL2
OUVF1
FLT
ADDR1
SCL
DCL1
PWM
LOGIC
GATE1
4
SELVTOP1
SDA
OLF1
OVERCURRENT
PROTECTION
LOGIC SCHEME 1
COUNTER
8
6
5
PWM
LOGIC
OC2
OUVF2
ADDR0
OUVF11
ISEL2L AND
ISEL2H
OLF1 FLT OLF2
EN2
I2C
ENT2
GATE2
Q
CLK2
CLK1
COUNTER
ENT1
CS1
OTF
-
CLK1
SLOPE
COMPENSATION
BAND GAP
REF VOLTAGE
TDOUT1
+
-
+
VREF2
SELVTOP2
TONE
INJ
CKT 2
VSW2
VSW1
VOUT1
20, 21
+
-
AGND
VOUT2
+
-
EXT TONE CKT
TONE
DECODER
ENT2
FN9190.1
April 10, 2007
10
NOTE:
1. Pinouts shown are for the QFN package.
16
18
9
1
33
TXT2
TDIN2
TCAP2
EN1/EN2
EXTM2
INT 5V
SOFT-START
EXTM1
ENT1
TCAP1
SGND
30, 31
28
UVLO
POR
SOFT-START
BYP
2
37
TDOUT2
ON CHIP
LINEAR
TXT1
24
VCC
34
TXT2
19
INT
TONE
TONE
INJ
CKT 1
MSEL1
14
REF
VOLTAGE
ADJ2
OTF
THERMAL
SHUTDOWN
CHARGE PUMP
CPVOUT
35
27
26
CPSWIN
CPSWOUT
29
25
ISL6422
22
VREF1
TDIN1
CLK2
DIV AND
WAVE SHAPING
REF
VOLTAGE
ADJ1
TXT1
36
BGV
BGV
TONE
DECODER
OSC.
1.1MHz
CS2
SLOPE
COMPENSATION
+
23
DCL
VBOT2 VTOP2
VTOP1 VBOT1
∑
CS
AMP
∑
INTERFACE
MSEL2
15
+
ILIM1
CS
AMP
ILIM2
40
-
11
ISEL1L AND
ISEL1H
EN1
PGND2
-
3
SDA SCL ADDR1
PGND1
39
S
Typical Application Schematic QFN
L1
15uH
PRELIMINARY
C5
56uF
2
0
D1
CMS06
1
4
C3
56uF
R4
0
18
2
C11
10uF
0
0
C12
10uF
0
C19
0.22uF
0
R6
18
40
39
38
37
36
35
34
33
32
31
1
2
3
0
0
2
TPC6002
Q4
L2
15uH
C4
56uF
0
FN9190.1
April 10, 2007
TDOUT1
R10
100
R11
100
PGND2
GATE2
NC
VSW2
CS2
TXT2
SELVTOP2
TCAP2
NC
VOUT2
0
0
C17
1uF
C29
1.5n
0
C24
10n
RTN
0
M7
NDS356AP
Q6
2N2222A
0
L6
220uH
2
1
C26
0.22uF
R8
15
D3
CMS06
0
VLNB1
C22
0.1UF
0
D8
1.5KE24
RTN
0
0
R13 4.7K
R22
47K
0
D5
2
R23
10K
M6
NDS356AP
Q5
2N2222A
0
CMS06
0
TDOUT2
EXTM1
SELVTOP1
C13
10uF
0
TXT1
C21
0.1uF
0
0
L3 4.7uH
CMS06
D4
CMS06
R25
10K
0
1
VLNB2
D7
1.5KE24
C20
0.22uF
0
D2
15
R24
47K
C16
1uF
C2
100PF
0
30
29
28
27
26
25
24
23
22
21
R7
R14 4.7K
C28
0.1uF
0
R2
0.1
6
5
4
1
1uF
C8
R5
470
U1
ISL6422ER
PGND1
GATE1
NC
VSW1
CS1
TXT1
SELVTOP1
TCAP1
AGND
VOUT1
0
C6
56uF
VOUT2
TDIN2
TDOUT2
CPVOUT
CPSWOUT
CPSWIN
VCC
TDOUT1
TDIN1
VOUT1
0.22uF
0
C23
10n
11
12
13
14
15
16
17
18
19
20
0
EXTM2
SGND
NC
FLT
SDA
SCL
ADDR0
ADDR1
EXTM1
BYP
C25
C14
10uF
0
C15
10uF
EXTM2
0
CONFIDENTIAL
ISL6422
1
2
3
4
5
6
7
8
9
10
C1
100PF
6
5
4
R1
0.1
0
TXT2
2
0
1
2
3
R3
470
TPC6002
Q3
220uH
1
C10
10UF
FLT BAR
SELVTOP2
L5
C27
0.1uF
SCL
RTN
0
L4 4.7uH
1
SDA
VIN
D6 CMS06
ISL6422
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0V
Logic Input Voltage Range
(SDA, SCL, ENT, DSQIN1 and DSQIN2,
SEL18V1 and SEL18V2) . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
Thermal Resistance (Typical, Notes 2, 3)
θJA (°C/W)
θJC (°C/W)
EPTSSOP Package . . . . . . . . . . . . . . .
29
4
QFN Package. . . . . . . . . . . . . . . . . . . .
34
6
Maximum Junction Temperature (Note 4) . . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . -40°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300°C
(SOIC - Lead Tips Only)
Operating Temperature Range . . . . . . . . . . . . . . . . . -20°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
+150°C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to +150°C junction may trigger the shutdown of
the device even before +150°C, since this number is specified as typical.
NOTES:
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
3. For θJC, the "case temp" location is the center of the exposed metal pad on the package underside.
4. The device junction temperature should be kept below +150°C. Thermal shut-down circuitry turns off the device if junction temperature exceeds
+150°C typically.
Electrical Specifications
VCC = 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. EN1 = EN2 = H,
VTOP1 = VTOP2 = L, ENT1 = ENT2 = L, DCL = L, DSQIN1 = DSQIN2 = L, IOUT = 12mA, unless otherwise
noted. See “ISL6422 Software Description” on page 12 for I2C access to the system.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
8
12
14
V
EN1 = EN2 = L
1.5
3.0
mA
EN1 = EN2 = VTOP1 = VTOP2 = VBOT1 =
VBOT2 = ENT1 = ENT2 = H, No Load
4.0
8.0
mA
Operating Supply Voltage Range
Standby Supply Current
Supply Current
IIN
UNDERVOLTAGE LOCKOUT
Start Threshold
7.5
7.95
V
Stop Threshold
7.0
7.55
V
Start to Stop Hysteresis
350
500
mV
400
SOFT-START
COMP Rise Time (Note 5)
(Note 5)
Output Voltage (Note 5)
Line Regulation
Load Regulation
5
8196
Cycles
VOUT1
(Refer to Table 11)
13.04
13.3
13.56
V
VOUT1
(Refer to Table 11)
14.02
14.3
14.58
V
VOUT1
(Refer to Table 11)
17.94
18.3
18.66
V
VOUT1
(Refer to Table 11)
19.00
19.3
19.68
V
VOUT2
(Refer to Table 15)
13.04
13.3
13.56
V
VOUT2
(Refer to Table 15)
14.02
14.3
14.58
V
VOUT2
(Refer to Table 15)
17.94
18.3
18.66
V
VOUT2
(Refer to Table 15)
19.00
19.3
19.68
V
DVOUT1,
DVOUT2
VIN = 8V to 14V; VOUT1, VOUT2 = 13V
4.0
40.0
mV
VIN = 8V to 14V; VOUT1, VOUT2 = 18V
4.0
60.0
mV
DVOUT1,
DVOUT2
IO = 12mA to 350mA
50
80
mV
IO = 12mA to 750mA
100
200
mV
FN9190.1
April 10, 2007
ISL6422
Electrical Specifications
VCC = 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. EN1 = EN2 = H,
VTOP1 = VTOP2 = L, ENT1 = ENT2 = L, DCL = L, DSQIN1 = DSQIN2 = L, IOUT = 12mA, unless otherwise
noted. See “ISL6422 Software Description” on page 12 for I2C access to the system. (Continued)
PARAMETER
SYMBOL
Dynamic Output Current Limiting
(Note 8)
IMAX
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DCL = 0, ISEL1H and ISEL2H = 0,
ISEL1L and ISEL2L = 0,
ISEL1R and ISEL2R = 0
270
305
345
mA
DCL = 0, ISEL1H and ISEL2H = 0,
ISEL1L and ISEL2L = 0,
ISEL1R and ISEL2R = 1
350
388
422
mA
DCL = 0, ISEL1H and ISEL2H = 0,
ISEL1L and ISEL2L = 1,
ISEL1R and ISEL2R = 1
515
570
630
mA
DCL = 0, ISEL1H and ISEL2H = 1,
ISEL1L and ISEL2L = 0,
ISEL1R and ISEL2R = 1
635
705
775
mA
DCL = 0, ISEL1H and ISEL2H = 1,
ISEL1L and ISEL2L = 1,
ISEL1R and ISEL2R = 1
800
890
980
mA
Dynamic Overload Protection Off Time
TOFF
DCL = L, Output Shorted (Note 8)
Dynamic Overload Protection On Time
TON
Static Output Current Limiting
IMAX
DCL = 1 (Note 8)
Cable Fault CABF Asserted High
ICAB
EN1 and EN2 = 1;
Tone Frequency
ftone
Tone Amplitude
900
ms
20
ms
990
mA
2
10
20
mA
ENT1 and ENT2 = H
20.0
22.0
24.0
kHz
Vtone
ENT1 and ENT2 = H, IOUT = 5mA
500
680
800
mV
Tone Duty Cycle
dctone
ENT1 and ENT2 = H
40
50
60
%
Tone Rise or Fall Time
Tr, Tf
ENT1 and ENT2 = H
5
10
14
μs
TONE OSCILLATOR
TONE DECODER
Input Amplitude
Vtdin
200
1000
mV
Frequency Capture Range
Ftdin
17.5
26.5
kHz
Input Impedance
Zdet
8.6
kΩ
Detector Output Voltage
Vtdout_L
Tone Present, Iload = 3mA
0.4
V
Detector Output Leakage
Itdout_H
Tone absent, Vo = 6V
10
μA
Tone Decoder Rx Threshold
VRXth
TXT1 and TXT2 = L
100
150
200
mV
Tone Decoder Tx Threshold
VTXth
TXT1 and TXT2 = H
400
450
500
mV
IOUT = 750mA
0.8
1.0
V
LINEAR REGULATOR
Drop-out Voltage
Output Backward Leakage Current
IOBK
EN1 and EN2 = 0; VOBK = 27V
2.0
3.0
mA
Output Backward Leakage Current
IOBK
EN1 and EN2 = 0; VOBK = 28V
15.0
17.0
mA
EN1 and EN2 = 1; VOFAULT = 19V (Note 7)
125
Output Backward Current Threshold
Output Backward Voltage
IOBKTH
IOBK
EN1 and EN2 = 0
mA
27
V
Output Under Voltage
(Asserted high during Softstart)
OUVF1/2 bit is asserted high, Measured from
the typ. output set value
-6
2
%
Output Over Voltage
(Asserted high during softstart)
OUVF1/2 bit is asserted high, Measured from
the typ. output set value
+2
+6
%
6
FN9190.1
April 10, 2007
ISL6422
Electrical Specifications
VCC = 12V, TA = -20°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C. EN1 = EN2 = H,
VTOP1 = VTOP2 = L, ENT1 = ENT2 = L, DCL = L, DSQIN1 = DSQIN2 = L, IOUT = 12mA, unless otherwise
noted. See “ISL6422 Software Description” on page 12 for I2C access to the system. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
0.8
V
TXT1 AND TXT2, EXTM1 AND EXTM2, SELVTOP1 AND SELVTOP2, ADDR0 AND ADDR1 INPUT PINs (Note 8)
Asserted LOW
Asserted HIGH
1.7
Input Current
V
25
μA
700
nA
CURRENT SENSE (CS pin)
Input Bias Current
IBIAS
Overcurrent Threshold
VCS
Static current mode, DCL = H
325
450
500
mV
ERROR AMPLIFIER
Open Loop Voltage Gain
AOL
88
dB
Gain Bandwidth Product
GBP
14
MHz
93
%
20
ns
PWM
Maximum Duty Cycle
90
Minimum Pulse Width
OSCILLATOR
Oscillator Frequency
fo
Fixed at (20) (ftone)
396
440
484
kHz
Thermal Shutdown
Temperature Shutdown Threshold
150
°C
Temperature Shutdown Hysteresis
20
°C
FLT
FLT (released)
VO = 6V
10
µA
FLT (asserted)
ISINK = 3.2mA (1.5k pull-up resistor to 5V)
0.4
V
NOTES:
5. Internal digital soft-start.
6. The EXTM1 and EXTM2, SELVTOP1 and SELVTOP2, TXT1 and TXT2, and ADDR0 and ADDR1 pins have 200k internal pull-downs.
7. On exceeding this dynamic back current limit threshold for a period of 100µs, the device enters the dynamic current limit mode, and the BCF I2C
bit is set. The dynamic back current limit duty during a BCF is ON = 100µs or OFF = 5ms.
8. In the dynamic back current limit mode, the output is ON for 20ms and OFF for 900ms, but remains continuously ON in the Static mode. When
tone is ON, the minimum current limit is 50mA lower than the values indicated in the table. While in the dynamic mode of current limit, the trip
level is momentarily increased to 990mA during the 20ms ON time to facilitate recovery from overload conditions.
7
FN9190.1
April 10, 2007
ISL6422
Tone Waveform
ENT1/2
I2C
MSEL1/2
I2C
EXTM1/2
PIN
VOUT1/2
PIN
22kHz
22kHz
Internal Tone
Tr = 10µs typ
22kHz
22kHz
22kHz
Internal Tone
Tr = 10µs typ
22kHz
Tr = 10µs typ
Internal Tone
Returns to nominal VOUT ~1 period
after the last EXTM rising edge
T > 55µs
NOTES:
9. The logic presented to the signal pins TXT1 and TXT2 changes the decoder threshold during tone Transmit and Receive. TTH1 and TTH2 allow
threshold control through the I2C provided that TXT1 and TXT2 = 0.
10. The tone rise and fall times are not shown due to resolution of graphics. It is 10µs typ for 22kHz.
11. The EXTM1 and EXTM2 pins have input thresholds of VIL(max) = 0.8V and VIH(min) = 1.7V
FIGURE 1. TONE WAVEFORM
Typical Performance Curves
0.820
0.810
IOUT IN A
IOUT IN A
0.810
0.800
0.760
0.710
0.790
0.660
0.780
0
20
40
60
80
TAMB (°C)
FIGURE 2. OUTPUT CURRENT DERATING 38 LD HTSSOP:
IOUT_max vs TAMB
0
20
40
60
80
TAMB (°C)
FIGURE 3. OUTPUT CURRENT DERATING 40 LD 6x6 QFN:
IOUT_max vs TAMB
NOTE: With both channels in simultaneous operation at rated output.
\
8
FN9190.1
April 10, 2007
ISL6422
Functional Pin Descriptions
SYMBOL
FUNCTION
SDA
Bidirectional data from/to I2C bus.
SCL
Clock from I2C bus.
VSW1 and VSW2
Input of the linear post-regulator.
PGND1 and PGND2
Dedicated ground for the output gate driver of respective PWM.
CS1 and CS2
Current sense input; connect the sense resistor Rsc at this pin for desired overcurrent value for respective PWM.
SGND
Small signal ground for the IC.
TCAP1 and TCAP2
Capacitor for setting rise and fall time of the output of LNB A and LNB B respectively. Typical value is 0.22µF.
BYP
Bypass capacitor for internal 5V.
TXT1 and TXT2
TXT1 and TXT2 are the Tone Transmit signal inputs used to change the tone decoder threshold. The threshold is 200mV
max for the Rx mode when the TXT1 and TXT2 are set low. The threshold is 400mV min in the Tx mode when TXT1
and TXT2 are set high. If Tx/Rx mode is set by I2C bit TTH(1 ,2), when TTH(1, 2) = 1, then TXT(1, 2) will be driven high
(5V) by an on-chip driver.
VCC
Main power supply to the chip.
GATE1 and GATE2
These are the device outputs of PWM A and PWM B respectively. These high current driver outputs are capable of
driving the gate of a power FET. These outputs are actively held low when VCC is below the UVLO threshold.
VOUT1 and VOUT2
Output voltage for LNB A and LNB B respectively.
ADDR0 and ADDR1
Address pins select four different device addresses per Table 19.
EXTM1 and EXTM2
These pins can be used in two ways:
1. As an input for externally modulated Diseqc tone signal that is transferred symmetrically onto VOUT.
2. Alternatively apply a Diseqc modulation envelope that modulates an internal tone and then transfers it symmetrically
onto VOUT.
FLT
This is an open drain output from the controller. When the FLT goes low, it indicates that an Over Temperature has
occurred. The processor should then look at the I2C register to get the actual cause of the error. A high on the FLT
indicates that the device is functioning normally.
CPVOUT, CPSWIN,
CPSWOUT
A 47nF charge pump cap is connected to CPVOUT. Connect a 1.5nF capacitor between CPSWIN and CPSWOUT.
SELVTOP1 and
SELVTOP2
The following description applies to both pins and both bits.
When this pin is low, the VOUT is in the 13V/14V range selected by the I2C bit VBOT1 and VBOT2.
When this pin is high, the 18V/19V range is selected by the I2C bit VTOP1 and VTOP2.
The voltage select pin voltage VSPEN1 and VSPEN2 I2C bit must be set low for the SELVTOP1 and SELVTOP2 pins
to be active. Setting VSPEN1 and VSPEN2 high disables these pins and voltage selection will be done using the I2C
bits VBOT1 and VBOT2 and VTOP1 and VTOP2 only.
TDIN1 and TDIN2
TDOUT1 and TDOUT2
TDIN1 and TDIN2 are the tone decoder inputs for channels 1 and 2.
TDOUT1 and TDOUT2 are the tone detector outputs for channels 1 and 2. TDOUT1 and TDOUT2 are open drain
outputs.
AGND
Analog ground for the IC.
9
FN9190.1
April 10, 2007
ISL6422
Functional Description
The ISL6422 dual output voltage regulator makes an ideal
choice for advanced satellite set-top box and personal video
recorder applications. Both supply and control voltage
outputs for two low-noise blocks (LNBs) are available
simultaneously in any output configuration. The device
utilizes built-in DC/DC step up converters that, from a single
supply source ranging from 8V to 14V, generate the voltages
that enable the linear post-regulators to work with a
minimum of dissipated power. An undervoltage lockout
circuit disables the device when VCC drops below a fixed
threshold (7.5V typical).
DiSEqC Encoding
The internal oscillator is factory-trimmed to provide a tone of
22kHz in accordance with DiSEqC (EUTELSAT) standards.
No further adjustment is required. The tone oscillator can be
controlled either by the I2C interface (ENT1 or ENT2 bit) or by
a dedicated pin (EXTM1 or EXTM2) that allows immediate
DiSEqC data encoding separately for each LNB. All the
functions of this IC are controlled via the I2C bus by writing to
the system registers. The same registers can be read back,
and four bits will report the diagnostic status. The internal
oscillator operates the converters at twenty times the 22k tone
frequency. The device offers full I2C compatibility and
supports 2.5V, 3.3V or 5V logic, and up to 400kHz operation.
If the Tone Enable bits (ENT1 and ENT2) are set LOW and
the MSEL1 and MSEL2 bits set LOW through I2C, then the
EXTM1 and EXTM2 terminal activates the internal tone
signal, modulating the DC output with a 680mVpp typ
symmetrical tone waveform. The presence of this signal
usually provides the LNB with information about the band to
be received.
Burst coding of the tone can be accomplished due to the fast
response of the EXTM1 and EXTM2 input and rapid tone
response. This allows implementation of the DiSEqC
(EUTELSAT) protocols.
When the ENT1 or ENT2 bit is set HIGH, a continuous
22kHz tone is generated regardless of the EXTM1 and
EXTM2 pin logic status for the corresponding regulator
channel (LNB-A or LNB-B). The ENT1 or ENT2 bit must be
set LOW when the EXTM1 and/or EXTM2 pin is used for
DiSEqC encoding.
The EXTM1 and EXTM2 pins also accept an externally
modulated tone command when the MSEL1 or MSEL2 I2C
bit is set high.
DiSEqC Decoder
TDIN1 and TDIN2 are the inputs to the tone decoders of
channels 1 and 2 respectively. They accept the tone signal
derived from the VOUT through the 10nF decoupling
capacitor. The detector threshold can be set to 200mV
maximum in the Receive mode and to 400mV minimum in
the Transmit mode by means of the logic presented to the
10
TXT1 or TXT2 pin. If tone is detected, the open drain pin
TDOUT1 or TDOUT2 is asserted low. This also enables the
tone diagnostics to be performed, apart from the normal tone
detection function.
Linear Regulator
The output linear regulator will sink and source current. This
feature allows full modulation capability into capacitive loads
as high as 0.75µF. In order to minimize the power
dissipation, the output voltage of the internal step-up
converter is adjusted to allow the linear regulator to work at
minimum dropout.
When the device is put in the shutdown mode (EN1 and
EN2 = LOW), both PWM power blocks are disabled (that is,
when EN1 = 0, PWM1 is disabled, and when EN2 = 0,
PWM2 is disabled).
When the regulator blocks are active (EN1 and EN2 = HIGH,
and VSPEN1 and VSPEN2 = LOW), the output can be
controlled via I2C logic to be between 13V and 14V or
between 18V and 19V (typical) by means of the Voltage
Select bits (VTOP1, VTOP2, VBOT1, and VBOT2) for
remote controlling of non-DiSEqC LNBs.
When the regulator blocks are active (EN1 and EN2 = HIGH,
and VSPEN1 and VSPEN2 = HIGH), the VBOT1 and
VBOT2 bits and the SELVTOP1 and SELVTOP2 pins will
control the output between 13V and 14V and the VTOP1 and
VTOP2 and the SELVTOP1 and SELVTOP2 pins will control
the output between 18V and 19V.
Output Timing
The output voltage rise and fall times can be set by an the
external capacitor on the TCAP1 and TCAP2 pins. The
output rise and fall times is given by Equation 1:
( 270 )T
C = ------------------ΔV
(EQ. 1)
where:
• C is the TCAP value in nF
• T is the required slew rate in ms, and
• ΔV is the differential transition voltage from low output
voltage range to the high output range in Volts.
Rise and fall time will typically be the same.
The maximum recommended value for TCAP1 and TCAP2
would be the base on the maximum transition time allowed
in the system application. Too small a value of TCAP1 and
TCAP2 can cause high peak currents in the boost circuit. For
example, a 10V/mS slew on a 80µF VSW capacitor with an
inductor of 15µH can cause a peak inductor current of
approximately 2.3A
FN9190.1
April 10, 2007
ISL6422
Current Limiting
The dynamic back current limit block has five thresholds that
can be selected by the following bits of the SR.
• ISEL1H and ISEL2H
• ISEL1L and ISEL2L
• ISEL1R and ISEL2R
See Table 8 and Table 9 for threshold selection using these
bits. The DCL1 and DCL2 bits have to be set to low for this
mode of operation. In this mode, the overcurrent protection
circuit works dynamically 23µs after an overload is detected,
and the output is shutdown for a time tOFF, typically 900ms.
Simultaneously, the OLF1 or OLF2 bit of the System
Register is set to HIGH. After this time has elapsed, the
output is resumed for a time tON = 20ms. During tON, the
device output will be current limited to a 990mA typ level. If
the overload is still detected, the protection circuit will cycle
again through tOFF and tON. At the end of a full tON, in which
no overload is detected, normal operation is resumed and
the OLF1 or OLF2 bit is reset to LOW. Typical tON + tOFF
time is 920ms as determined by an internal timer. This
dynamic operation can greatly reduce the power dissipation
in a short circuit condition, still ensuring excellent power-on
start-up in most conditions.
However, there could be some cases in which a highly
capacitive load on the output may cause a difficult start-up
when the dynamic protection is chosen. This can be solved
by initiating any power start-up in static mode (DCL = HIGH)
and then switching to the dynamic mode (DCL = LOW) after
a chosen amount of time. When in static mode, the OLF1 or
OLF2 bit goes HIGH when the peak current sense threshold
is reached and returns LOW when the overload condition is
cleared. The OLF1, OLF2, BCF1, and BCF2 bits will be LOW
at the end of initial power-on soft-start. In the static mode the
output current through the linears is limited to 990mA typ.
When a 19.3V line is connected onto a VOUT1 or VOUT2
pin that has been set to 13.3V, the linear will then enter a
dynamic back current limit state. When a dynamic back
current limit of greater that 125mA typ is sensed at the lower
FET of the linear for a period greater that 100µs, the output
is disabled for a period of 5ms and the BCF1 and BCF2 bits
are set. If the 19.3V remains connected, the output will cycle
through the ON = 100µs/OFF = 5ms. The output will recover
when the fault is removed.
Thermal Protection
This IC is protected against overheating. When the junction
temperature exceeds +150°C (typical), the step-up converter
and the linear regulator are shut off and the OTF bit of the
SR is set HIGH. Normal operation is resumed and the OTF
bit is reset LOW when the junction is cooled down to +130°C
(typical).
11
The FLT pin serves as an interrupt for the processor when
an over temperature, overcurrent or backwards overcurrent
fault is detected by the LNB controller or when both channels
are disabled by the I2C EN1 and EN2 bits being set low.
Should the I2C lose power (for example by shorting BYP pin
to ground), it is designed to power up with all control bits set
to 0 (particularly the EN1 and EN2 bits). This prevents the
device from coming back up in a state not desired by the
host controller. If the host controller sees a FLT low, it
should read the I2C bits and find both EN1 and EN2 bits low.
When it desires one or both to be high, it should re-write the
I2C to the desired state.
External Output Voltage Selection
The output voltage can be selected by the I2C bus.
Additionally, the package offers two pins (SELVTOP1 and
SELVTOP2) for independent 13 through 19V output voltage
selection.
TABLE 1.
VSPEN1,
VSPEN2
VTOP1,
VTOP2
VBOT1,
VBOT2
SELVTOP1,
SELVTOP2
VOUT1,
VOUT12
0
X
0
0
13.3V
0
X
1
0
14.3V
0
0
X
1
18.3V
0
1
X
1
19.3V
1
0
0
X
13.3V
1
0
1
X
14.3V
1
1
0
X
18.3V
1
1
1
X
19.3V
I2C Bus Interface for ISL6422
(Refer to Phillips I2C Specification, Rev. 2.1)
Data transmission from the main microprocessor to the
ISL6422 and vice versa takes place through the two-wire I2C
bus interface, consisting of the two lines SDA and SCL. Both
SDA and SCL are bidirectional lines. They are connected to a
positive supply voltage via a pull-up resistor. (Pull-up resistors
to positive supply voltage must be externally connected.) When
the bus is free, both lines are HIGH. The output stages of
ISL6422 will have an open drain/open collector in order to
perform the wired-AND function. Data on the I2C bus can be
transferred up to 100Kbps in the standard mode or up to
400Kbps in the fast mode. The level of logic “0” and logic “1”
depends on the value of VDD as per the Electrical Specification
table on page 5. One clock pulse is generated for each data bit
transferred.
FN9190.1
April 10, 2007
ISL6422
Data Validity
The data on the SDA line must be stable during the HIGH
period of the clock. The HIGH or LOW state of the data line
can change only when the clock signal on the SCL line is
LOW. Refer to Figure 4.
The ISL6422 will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
SCL
8
2
1
9
SDA
MSB
SDA
START
ACKNOWLEDGE
FROM SLAVE
FIGURE 6. ACKNOWLEDGE ON THE I2C BUS
SCL
DATA LINE CHANGE
STABLE
OF DATA
DATA VALID ALLOWED
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock pulse without checking the slave acknowledging and
sends the new data.
FIGURE 4. DATA VALIDITY
START and STOP Conditions
As shown in Figure 5, the START condition is a HIGH to
LOW transition of the SDA line while SCL is HIGH.
This approach, though, is less protected from error and
decreases the noise immunity.
The STOP condition is a LOW to HIGH transition on the SDA
line while SCL is HIGH. A STOP condition must be sent
before each START condition.
ISL6422 Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown in Table 2:
SDA
• Start condition (S)
SCL
• Chip address byte (MSB on left; the LSB bit determines
read (1) or write (0) transmission) (the assigned I2C slave
address for the ISL6422 is 0001 00XX)
S
P
START
CONDITION
STOP
CONDITION
• Sequence of data (1 byte + Acknowledge)
• Stop condition (P)
FIGURE 5. START AND STOP WAVEFORMS
TABLE 2. INTERFACE PROTOCOL
S 0
0
0
1
0
0
0 R/W ACK
Data (8 bits)
ACK P
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
System Register Format
• R, W = Read and Write bit
• R = Read-only bit
• X = Unused
All bits reset to 0 at Power-On
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (see
Figure 6). The peripheral that acknowledges has to pull
down (LOW) the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during this clock
pulse. (Set-up and hold times must also be taken into
account.)
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
12
TABLE 3. STATUS REGISTER 1 (SR1)
R, W
R, W
R, W
R
SR1H
SR1M
SR1L
OTF
R
R
R
R
CABF1 OUVF1 OLF1
BCF1
TABLE 4. TONE REGISTER 2 (SR2)
R, W
R, W
R, W
R, W
SR2H
SR2M
SR2L
ENT1
R, W
R, W
MSEL1 TTH1
R, W
R, W
X
X
TABLE 5. COMMAND REGISTER 3 (SR3)
R, W
R, W
R, W
SR3H SR3M SR3L
R, W
R, W
R, W
R, W
R, W
DCL1 VSPEN1 ISEL1R ISEL1H ISEL1L
X
FN9190.1
April 10, 2007
ISL6422
TABLE 6. CONTROL REGISTER 4 (SR4)
R, W
R, W
R, W
R, W
R, W
R, W
SR4H
SR4M
SR4L
EN1
X
X
R, W
TABLE 9. COMMAND REGISTER 7 (SR7)
R, W
R, W
VTOP1 VBOT1
R, W
R, W
X
SR5H
SR5M
SR5L
X
R
R
R
R, W
R, W
R, W
SR6H
SR6M
SR6L
ENT2
R, W
MSEL2 TTH2
R, W
R, W
R, W
R, W
DCL2 VSPEN2 ISEL2R ISEL2H ISEL2L
R
R, W
R, W
R, W
R, W
R, W
R, W
BCF2
SR8H
SR8M
SR8L
EN2
X
X
R, W
R, W
VTOP2 VBOT2
Transmitted Data (I2C bus WRITE mode)
TABLE 8. TONE REGISTER 6 (SR6)
R, W
R, W
TABLE 10. CONTROL REGISTER 8 (SR8)
CABF2 OUVF2 OLF2
R, W
R, W
SR7H SR7M SR7L
TABLE 7. STATUS REGISTER 5 (SR5)
R, W
R, W
R, W
R, W
X
X
When the R/W bit in the chip is set to 0, the main
microprocessor can write on the system registers (SR1
through SR8) of the ISL6422 via I2C bus. These will be
written by the microprocessor as shown below. The spare
bits of registers can be used for other functions.
TABLE 11. STATUS REGISTER SR1 CONFIGURATION
SR1H
SR1M
SR1L
OTF
CABF1
OUVF1
OLF1
BCF1
FUNCTION
0
0
0
X
X
X
X
X
SR1 is selected
0
0
0
X
X
X
0
X
IOUT ≤set limit, Normal Operation
0
0
0
X
X
X
1
X
IOUT >Static / Dynamic Limiting Mode/Power blocks disabled
0
0
0
X
X
X
X
0
IOBCK ≤set limit, Normal Operation
0
0
0
X
X
X
X
1
IOBCK >Dynamic Limiting Mode/Power blocks disabled
0
0
0
X
X
0
X
X
VIN/VOUT within specified range
0
0
0
X
X
1
X
X
VIN/VOUT is not within specified range
0
0
0
X
0
X
X
X
Cable is connected, Io is >20mA
0
0
0
X
1
X
X
X
Cable is open, Io <2mA
0
0
0
0
X
X
X
X
TJ ≤130°C, Normal operation
0
0
0
1
X
X
X
X
TJ >150°C, Power blocks disabled
NOTE: X indicates “Read Only” and is a “Don’t Care” for the Write mode.
TABLE 12. TONE REGISTER SR2 CONFIGURATION
SR2H
SR2M
SR2L
ENT1
MSEL1
TTH1
X
X
FUNCTION
0
0
1
X
X
X
X
X
SR2 is selected
0
0
1
0
0
X
X
X
Internal Tone = 22kHz, modulated by EXTM1, Tr, Tf = 10µs typ
0
0
1
0
1
X
X
X
Ext 22K modulated input, Tr, Tf = 10µs typ
0
0
1
1
0
X
X
X
Internal Tone = 22kHz, modulated by the ENT1 bit, Tr, Tf = 10µs typ
0
0
1
X
X
0
X
X
TXT = 0; Decoder Rx threshold is set at 200mV max
0
0
1
X
X
1
X
X
TXT = 0; Decoder Tx threshold is set at 400mV min
NOTE: X is a “Don’t Care” for the Write mode.
13
FN9190.1
April 10, 2007
ISL6422
TABLE 13. COMMAND REGISTER SR3 CONFIGURATION
SR3H
SR3M
SR3L
DCL1
VSPEN1 ISEL1R ISEL1H ISEL1L
FUNCTION
0
1
0
X
X
X
X
X
SR3 is selected
0
1
0
0
X
0
X
X
IOUT1 = 275mA maximum
0
1
0
0
X
1
0
0
IOUT1 = 350mA maximum
0
1
0
0
X
1
0
1
IOUT1 = 515mA maximum
0
1
0
0
X
1
1
0
IOUT1 = 635mA maximum
0
1
0
0
X
1
1
1
IOUT1 = 800mA maximum
0
1
0
1
X
X
X
X
Dynamic current limit NOT selected
0
1
0
0
X
X
X
0
1
0
X
0
X
X
X
SELVTOP H/W pin Enabled
0
1
0
X
1
X
X
X
SELVTOP H/W pin Disabled
Dynamic current limit selected
NOTE: X is a “Don’t Care” for the Write mode.
TABLE 14. CONTROL REGISTER SR4 CONFIGURATION
SR4H
SR4M
SR4L
EN1
X
X
VTOP1
VBOT1
FUNCTION
0
1
1
1
X
X
0
0
SR4 is selected
0
1
1
1
X
X
0
0
VSPEN1 = SELVTOP1 = 0, VOUT1 = 13V,
VBOOST1 = 13V + VDROP
0
1
1
1
X
X
0
1
VSPEN1 = SELVTOP1 = 0, VOUT1 = 14V,
VBOOST1 = 14V + VDROP
0
1
1
1
X
X
1
0
VSPEN1 = SELVTOP1 = 0, VOUT1 = 13V,
VBOOST1 = 13V + VDROP
0
1
1
1
X
X
1
1
VSPEN1 = SELVTOP1 = 0, VOUT1 = 14V,
VBOOST1 = 14V + VDROP
0
1
1
1
X
X
0
0
VSPEN1 = 0, SELVTOP1 = 1, VOUT1 = 18V,
VBOOST1 = 18V + VDROP
0
1
1
1
X
X
0
1
VSPEN1 = 0, SELVTOP1 = 1, VOUT1 = 18V,
VBOOST1 = 18V + VDROP
0
1
1
1
X
X
1
0
VSPEN1 = 0, SELVTOP1 = 1, VOUT1 = 19V,
VBOOST1 = 19V + VDROP
0
1
1
1
X
X
1
1
VSPEN1 = 0, SELVTOP1 = 1, VOUT1 = 19V,
VBOOST1 = 19V + VDROP
0
1
1
1
X
X
0
0
VSPEN1 = 1, SELVTOP1 = X, VOUT1 = 13V,
VBOOST1 = 13V + VDROP
0
1
1
1
X
X
0
1
VSPEN1 = 1, SELVTOP1 = X, VOUT1 = 14V,
VBOOST1 = 14V + VDROP
0
1
1
1
X
X
1
0
VSPEN1 = 1, SELVTOP1 = X, VOUT1 = 18V,
VBOOST1 = 18V + VDROP
0
1
1
1
X
X
1
1
VSPEN1 = 1, SELVTOP1 = X, VOUT1 = 19V,
VBOOST1 = 19V + VDROP
0
1
1
0
X
X
X
X
PWM and Linear for channel 1 disabled
NOTE: X is a “Don’t Care” for the Write mode.
14
FN9190.1
April 10, 2007
ISL6422
TABLE 15. STATUS REGISTER SR5 CONFIGURATION
SR5H
SR5M
SR5L
CABF2 OUVF2
OLF2
BCF2
1
0
0
X
X
1
0
0
X
1
0
0
1
0
1
FUNCTION
X
X
X
SR5 is selected
X
X
0
X
IOUT ≤ set limit, Normal Operation
X
X
X
1
X
IOUT > Static/Dynamic Limiting Mode/Power blocks disabled
0
X
X
X
X
0
IOBCK ≤ set limit, Normal Operation
0
0
X
X
X
X
1
IOBCK > Dynamic Limiting Mode/Power blocks disabled
1
0
0
X
X
0
X
X
VIN/VOUT within specified range
1
0
0
X
X
1
X
X
VIN/VOUT is not within specified range
1
0
0
X
0
X
X
X
Cable is connected, Io is >20mA
1
0
0
X
1
X
X
X
Cable is open, Io <2mA
NOTE: X indicates “Read Only” state.
TABLE 16. TONE REGISTER SR6 CONFIGURATION
SR6H
SR6M
SR6L
ENT2
MSEL2
TTH2
X
X
FUNCTION
1
0
1
X
X
X
X
X
SR2 is selected
1
0
1
0
0
X
X
X
Int Tone = 22kHz, modulated by EXTM2, Tr, Tf = 10µs typ
1
0
1
0
1
X
X
X
Ext 22k modulated input, Tr, Tf = 10µs typ
1
0
1
1
0
X
X
X
Int Tone = 22kHz, modulated by ENT2 bit, Tr, Tf = 10µs typ
1
0
1
X
X
0
X
X
TXT2 = 0; Decoder Rx threshold is set at 200mV max
1
0
1
X
X
1
X
X
TXT2 = 0; Decoder Tx threshold is set at 400mV min
NOTE: X is a “Don’t Care” for the Write mode.
TABLE 17. COMMAND REGISTER SR7 CONFIGURATION
SR7H
SR7M
SR7L
DCL2
VSPEN2 ISEL2R ISEL2H ISEL2L
FUNCTION
1
1
0
X
X
X
X
X
SR7 is selected
1
1
0
0
X
0
X
X
IOUT1 = 275mA max.
1
1
0
0
X
1
0
0
IOUT1 = 350mA max.
1
1
0
0
X
1
0
1
IOUT1 = 515mA max.
1
1
0
0
X
1
1
0
IOUT1 = 635mA max.
1
1
0
0
X
1
1
1
IOUT1 = 800mA max.
1
1
0
1
X
X
X
X
Dynamic current limit NOT selected
1
1
0
0
X
X
X
X
Dynamic current limit selected
1
1
0
X
0
X
X
X
SELVTOP H/W pin Enabled
1
1
0
X
1
X
X
X
SELVTOP H/W pin Disabled
NOTE: X is a “Don’t Care” for the Write mode.
15
FN9190.1
April 10, 2007
ISL6422
TABLE 18. CONTROL REGISTER SR8 CONFIGURATION
SR8H
SR8M
SR8L
EN2
X
X
VTOP2
VBOT2
FUNCTION
1
1
1
1
X
X
0
0
SR4 is selected
1
1
1
1
X
X
0
0
VSPEN2 = SELVTOP2 = 0, VOUT1 = 13V,
VBOOST1 = 13V + VDROP
1
1
1
1
X
X
0
1
VSPEN2 = SELVTOP2 = 0, VOUT1 = 14V,
VBOOST1 = 14V + VDROP
1
1
1
1
X
X
1
0
VSPEN2 = SELVTOP2 = 0, VOUT1 = 13V,
VBOOST1 = 13V + VDROP
1
1
1
1
X
X
1
1
VSPEN2 = SELVTOP2 = 0, VOUT1 = 14V,
VBOOST1 = 14V + VDROP
1
1
1
1
X
X
0
0
VSPEN2 = 0,SELVTOP2 = 1, VOUT1 = 18V,
VBOOST1 = 18V + VDROP
1
1
1
1
X
X
0
1
VSPEN2 = 0, SELVTOP2 = 1, VOUT1 = 18V,
VBOOST1 = 18V + VDROP
1
1
1
1
X
X
1
0
VSPEN2 = 0, SELVTOP2 = 1, VOUT1 = 19V,
VBOOST1 = 19V + VDROP
1
1
1
1
X
X
1
1
VSPEN2 = 0, SELVTOP2 = 1, VOUT1 = 19V,
VBOOST1 = 19V + VDROP
1
1
1
1
X
X
0
0
VSPEN2 = 1, SELVTOP2 = X, VOUT1 = 13V,
VBOOST1 = 13V + VDROP
1
1
1
1
X
X
0
1
VSPEN2 = 1, SELVTOP2 = X, VOUT1 = 14V,
VBOOST1 = 14V + VDROP
1
1
1
1
X
X
1
0
VSPEN2 = 1, SELVTOP2 = X, VOUT1 = 18V,
VBOOST1 = 18V + VDROP
1
1
1
1
X
X
1
1
VSPEN2 = 1, SELVTOP2 = X, VOUT1 = 19V,
VBOOST1 = 19V + VDROP
1
1
1
0
X
X
X
X
PWM and Linear for channel 1 disabled
NOTE: X is a “Don’t Care” for the Write mode.
Received Data (I2C bus READ MODE)
Power–On I2C Interface Reset
The ISL6422 can provide to the master a copy of the system
register information via the I2C bus in read mode. The read
mode is master-activated by sending the chip address with
the R/W bit set to 1. At the following master-generated clock
bits, the ISL6422 issues a byte on the SDA data bus line
(MSB transmitted first).
The I2C interface built into the ISL6422 is automatically reset
at power-on. The I2C interface block will receive a Power OK
logic signal from the UVLO circuit. This signal will go HIGH
when chip power is OK. As long as this signal is LOW, the
interface will not respond to any I2C commands and the
system register SR1 and SR2 are initialized to all zeros, thus
keeping the power blocks disabled. Once the VCC rises
above UVLO, the POWER OK signal given to the I2C
interface block will be HIGH, the I2C interface becomes
operative and the SRs can be configured by the main
microprocessor. About 400mV of hysteresis is provided in
the UVLO threshold to avoid false triggering of the power-on
reset circuit. (I2C comes up with EN = 0; EN goes HIGH at
the same time as (or later than) all other I2C data for that
PWM becomes valid).
At the ninth clock bit, the MCU master can:
• Acknowledge the reception, thus starting the transmission
of another byte from the ISL6422.
• Not acknowledge, thus stopping the read mode
communication.
While the whole register is read back by the microprocessor,
the following read-only bits convey diagnostic information
about the ISL6422.
•
•
•
•
OUC1 and OUC2 (Over or Undercurrent bits)
UV1 and UV2 (Over or Undervoltage bits)
TPR1 and TPR2 (Tone present bits)
OTF (Over-temperature fault bit).
16
FN9190.1
April 10, 2007
ISL6422
ADDR0 and ADDR1 Pins
Connecting either ADDR0 or ADDR1 to GND, the chip I2C
interface address is 0001000, but it is possible to choose
between four different addresses simply by setting the logic
as indicated in Table 19.
TABLE 19. ADDRESS PIN CHARACTERISTICS
VADDR
ADDR1
ADDR0
VADDR-1
“0001000”
0
0
VADDR-2
“0001001”
0
1
VADDR-3
“0001010”
1
0
VADDR-4
“0001011”
1
1
I2C Electrical Characteristics
TABLE 20. I2C SPECIFICATIONS
PARAMETER
TEST CONDITION
MIN
TYP
MAX
Input Logic High, VIH
SDA, SCL
2.0V
Input Logic Low, VIL
SDA, SCL
0.8V
Input Logic Current, IIL
SDA, SCL;
0.4V < VDD < 3.3V
10μA
Input Hysterisis
SDA, SCL
SCL Clock Frequency
165mV
200mV
235mV
0
100kHz
400kHz
I2C Bit Description
TABLE 21.
BIT NAME
DESCRIPTION
EN1 and EN2
ENable Output for channels 1 and 2
VTOP1 and VTOP2
Voltage TOP Select (that is, 18V/19V for channels 1 and 2)
VBOT1 and VTOP2
Voltage BOTtom Select (that is, 13V/14V for channels 1 and 2)
ENT1 and ENT2
ENable Tone for channels 1 and 2
MSEL1 and MSEL2
Modulation SELect for channels 1 and 2
TFR1 and TFR2
Tone Frequency and Rise time select for channels 1 and 2
DCL1 and DCL2
Dynamic Current Limit select for channels 1 and 2
VSPEN1 and VSPEN2
Voltage Select Pin ENable for channels 1 and 2
ISEL1H and ISEL2H,
ISEL1L and ISEL2L,
ISEL1R and ISEL2R
Current limit “I” SELect high and low bits for channels 1 and 2
OTF
Over Temperature Fault bit
CABF1/2
CABle Fault or open status bit for channels 1 and 2
OUVF1/2
Over and Under Voltage Fault status bit for channels 1 and 2
OLF1/2
Over Load Fault status bit for channels 1 and 2
BCF1/2
Backward Current Fault Bit for channels 1 and 2
TTH1/2
Tone THreshold is the OR of the signal pin TXT1 or TXT2
17
FN9190.1
April 10, 2007
ISL6422
Package Outline Drawing
L40.6x6
40 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 3, 10/06
4X 4.5
6.00
36X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
40
31
30
1
6.00
4 . 10 ± 0 . 15
21
10
0.15
(4X)
11
20
0.10 M C A B
TOP VIEW
40X 0 . 4 ± 0 . 1
4 0 . 23 +0 . 07 / -0 . 05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0 . 1
(
C
BASE PLANE
( 5 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
4 . 10 )
( 36X 0 . 5 )
C
0 . 2 REF
5
( 40X 0 . 23 )
0 . 00 MIN.
0 . 05 MAX.
( 40X 0 . 6 )
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
18
FN9190.1
April 10, 2007
ISL6422
Thin Shrink Small Outline Exposed Pad Plastic Packages (EPTSSOP)
N
M38.173B
INDEX
AREA
E
0.25(0.010) M
E1
2
38 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES
GAUGE
PLANE
-B1
B M
SYMBOL
A
3
TOP VIEW
0.25
0.010
0.05(0.002)
-A-
L
SEATING PLANE
A
D
α
-C-
A2
c
e
A1
b
0.10(0.004)
0.10(0.004) M
C A M
B S
2
3
MILLIMETERS
MAX
-
MIN
MAX
NOTES
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.051
0.80
1.05
-
b
0.0075
0.0106
0.17
0.27
9
c
0.0035
0.0079
0.09
0.20
-
D
0.378
0.386
9.60
9.80
3
E1
0.169
0.177
4.30
4.50
4
e
0.0197 BSC
0.500 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
α
1
MIN
38
0o
38
7
8o
-
P
-
0.256
-
6.5
11
P1
-
0.126
-
3.2
11
Rev. 0 9/06
P1
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-BD-1, Issue F.
N
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
BOTTOM VIEW
4. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.15mm (0.006
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum
space between protrusion and adjacent lead is 0.07mm (0.0027
inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
19
FN9190.1
April 10, 2007