SPV1020 Interleaved DC-DC boost converter with built-in MPPT algorithm Features ■ PWM mode DC-DC boost converter ■ Duty cycle controlled by MPPT algorithm with 0.2% accuracy ■ Operating voltage range 6.5 - 40 V ■ Overvoltage, overcurrent, overtemperature protection ■ Interleaved 4-phase topology ■ Built-in soft-start ■ Up to 98% efficiency ■ Power capability 320 W at 40 V output ■ Automatic transition to burst mode for improved efficiency at low solar radiation ■ SPI interface Applications ■ Photovoltaic panels ■ Battery charging with a CVCC controller Description The SPV1020 is a monolithic 4-phase interleaved DC-DC boost converter designed to maximize the power generated by photovoltaic panels independent of temperature and amount of solar radiation. Optimization of the power conversion is obtained with embedded logic which performs the MPPT (max. power point tracking) algorithm on the PV cells connected to the converter. One or more converters can be housed in the connection box of the PV panels, replacing the bypass diodes. As the maximum power point is locally computed, the efficiency at system level is higher than that of conventional topologies, where the MPP is computed in the main centralized inverter. January 2012 PowerSSO-36 For a cost effective application solution and to minimize size, the SPV1020 embeds Power MOSFETs for active switches and synchronous rectifiers, minimizing the number of external devices. In addition, the 4-phase interleaved topology of the DC-DC converter obviates the need to use electrolytic capacitors, which may severely limit system lifetime. The SPV1020 operates at fixed frequency in PWM mode, where the duty cycle is controlled by the embedded logic running a Perturb&Observe MPPT algorithm. The switching frequency, internally generated and set by default at 100 kHz, is externally adjustable from 50 kHz to 200 kHz, while the duty cycle can range from 5% to 90% with a step of 0.2%. The safety of the application is guaranteed by stopping the drivers in the case of output overvoltage or overtemperature. Multiple SPV1020s can be used in a panel array with one SPV1020 per panel. Panels can be connected in series, in parallel, or series/parallel combinations. Table 1. Device summary Order codes Package Packaging SPV1020 PowerSSO-36 Tube Doc ID 17588 Rev 3 1/19 www.st.com 19 Contents SPV1020 Contents 1 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 Initialization and startup mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 Input voltage sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.4 Output voltage sensing and overvoltage protection (OVP) . . . . . . . . . . . . 10 5.5 Overcurrent protection (OCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.6 Overtemperature protection (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.7 Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.8 Undervoltage lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.9 MPPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.10 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.11 SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 Doc ID 17588 Rev 3 SPV1020 1 Application circuit Application circuit Figure 1. Application circuit 9LQ ' 9287 3LQ 3LQ 9287 & / 39&HOOV / & 9287 &% &% /; /; 3*1' 3*1' 3*1' 3*1' /; /; &% &% & / / & & ' & 9287 ;&6 63,B'$7$B,1 63,B&/. 9287 63,B'$7$B287 95(* 26&B,1 ' 5 9,1 5 9,1B616 5 9,1B616B0,186 & & 9287B616 3=B287 6*1' & 5 & 5 & 9287 9LQ Doc ID 17588 Rev 3 3/19 Pin connection 2 SPV1020 Pin connection Figure 2. Pin connection (top view) 4/19 6/54 6/54 6/54 6/54 #" #" ,8 ,8 ,8 ,8 0'.$ 0'.$ 0'.$ 0'.$ ,8 ,8 ,8 ,8 #" #" 6/54 6/54 6/54 6/54 8#3 30)?$!4!?/54 62%' 30)?$!4!?). /3#?). 30)?#,+ 6). 6/54?3.3 6).?3.3 6).?3.3?- Doc ID 17588 Rev 3 0:?/54 3'.$ SPV1020 Pin connection Table 2. Pin description Pin Name Type Description 34 VIN Supply DC input power supply unit. 7,8,17,18,19,20,29,30 VOUT Supply Booster output voltage 12,13,24,25 PGND Ground Power ground 1 SGND Ground Signal ground reference. The exposed pad is connected to PGND. 22,23,26,27,15,14,11,1 0 LX1…4 I 9,16,21,28 CB1…4 I/O External bootstrap capacitors must be connected between these pins and LXi 5 VREG I/O Power supply for internal low voltage circuitry; an external capacitor must be connected to this pin referenced to SGND 35 VIN_SNS I Sense pin of input voltage. To be biased with a resistor divider between VIN and SGND 3 VOUT_SNS I Sense pin of output voltage. To be biased with a resistor divider between VOUT and SGND 31 XCS I Activates the SPI 36 VIN_SNS_M I Dedicated ground for VIN_SNS 2 PZ_OUT I/O Compensates the output voltage feedback loop. A series resistor and capacitor are connected between PZ_OUT and SGND. 6 SPI_DATA_OUT O Data OUT for SPI interface 33 SPI_CLK I Clock for SPI interface. 32 SPI_DATA_IN I Data IN for SPI interface. 4 OSC_IN I Pin for adjusting the switching frequency; to set the default value of 100 kHz, connect OSC_IN to VREG. Otherwise connect OSC_IN through a resistor to SGND. PowerSSO-36 Booster inductor connection. Doc ID 17588 Rev 3 5/19 Maximum ratings SPV1020 3 Maximum ratings 3.1 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Unit VIN Power supply [-0.3, 40] V VOUT Power supply [-0.3, 40] V PGND Power ground 0 V SGND Signal ground [-0.3, 0.3] V VOUT_SNS Analog input [-0.3, VOUT + 0.3] V LX1….4 Analog input [-0.3, VOUT + 0.3] V CB1…4 Analog input/output [Lxi – 0.3, Lxi + 5] V VREG Analog input/output [-0.3, 6] V VIN_SNS Analog input [-0.3, 3.3 + 0.3] V XCS Analog input [-0.3, 3.3 + 0.3] V OSC_IN Analog input [-0.3, 3.3 + 0.3] V PZ_OUT Analog input/output [-0.3, VIN + 0.3] V [-0.3, 3.3 + 0.3] V SPI_DATA_OUT Analog output SPI_CLK Digital input [-0.3, 3.3 + 0.3] V SPI_DATA_IN Digital input [-0.3, 3.3 + 0.3] V VIN_SNS_M Dedicated ground [-0.3, 0.3] V Table 4. Thermal data Symbol 6/19 Range [min., max.] Parameter Min. Typ. Max. Unit RthJA Thermal resistance, junction to ambient - Tjop Junction temperature operating range - Tstg Storage temperature 24 °C/W °C Doc ID 17588 Rev 3 -50 - 125 SPV1020 4 Electrical characteristics Electrical characteristics VIN = 36 V, TA = 25 °C and TJ<125 °C, unless otherwise specified. Table 5. Electrical characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Input source section VIN Operating input voltage 6.5 40 V Quiescent current ILOAD=0 mA, VOUT=36 V, Tj=Tamb, PWM=5% 5 mA Shutdown mode current consumption ILOAD=0 mA, VOUT=VIN= 36 V, Tj=Tamb 1 mA Undervoltage lockout threshold for turn-on VIN increasing 6.5 V -0.5 V RDSON-LS Power switch ON-resistance 70 mΩ RDSON-HS Synchronous rectifier ON-resistance 70 mΩ Iq ISD VUVLO Undervoltage lockout hysteresis Power section Control section VOUT Operating output voltage IOUT Operating output current Ilim Vin 40 V 9 A LX switch current limit 4 4.5 5 A FPWM PWM frequency (default value) 70 100 150 kHz VREF Constant voltage control loop internal reference voltage 1.18 1.23 1.27 V 140 150 °C Thermal shutdown Overtemperature threshold for turn-off Tshutdown Temperature increasing Overtemperature hysteresis -20 Doc ID 17588 Rev 3 160 °C 7/19 Detailed description 5 SPV1020 Detailed description The SPV1020 is a fully integrated high efficiency DC-DC boost converter with 4-phase interleaved topology operating in the voltage range from 6.5 VDC to 40 VDC. A simplified block diagram showing only one of the four phases is shown in Figure 3 below. Figure 3. Simplified block diagram &% /; 39FHOO VWULQJ 9287 9,1B616 9287B616 3*1' 3*1' 9,1B616B0 9,1 9% 9,1 95(* $' FRQY HUW HU $' FRQY HUW HU 0337 &WUO 63,B'$7$B287 $' FRQYHUW HU ;&6 ',$* 63, '$7$ ,1 63,B&/. P9 3=B287 )DXOW &WUO 9 9 26& ,1 6*1' 2VF 5.1 Initialization and startup mode In order to guarantee a correct power-up sequence, the converter initially operates in burst mode. When the input voltage is greater than 6.5 V, the converter sequentially activates each of the four phases. Initially, only phase 1 starts to work in burst mode, charging the inductor only for one cycle over 15 cycles. Then the duty cycle is progressively increased until phase 1 is switched on at every cycle and at the default switching frequency of 100 kHz. After phase 1 has reached its steady-state condition, all the other phases are progressively switched on in the following sequence: phase 3, phase 2 and, lastly, phase 4. All the sequences are running when the power generated by the PV cells is increasing. Otherwise the sequence may go back and then forward again. 8/19 Doc ID 17588 Rev 3 SPV1020 5.2 Detailed description Oscillator The switching frequency Fswitch is internally fixed at 100 kHz and each phase operates at the frequency fixed by the oscillator. To set the default value of 100 kHz, connect OSC_IN to VREG. The switching frequency can be adjusted from 50 kHz to 200 kHz by connecting an external resistor R6 between OSC and SGND. The relationship between R6 and Fswitch is: 5.3 Input voltage sensing The device monitors the input voltage generated by the PV cells through VIN_SNS. This value is used to calculate the power generated by the PV cell string and then to adjust the PWM duty cycle to provide the maximum power point. The input voltage must be scaled to a reference voltage level of 1.25 V at the input of the ADC integrated in the SPV1020. Referring to the schematic shown in the application circuit of Figure 1, R1 and R2 are the resistors used for partitioning the input voltage. If Vin_max is the maximum input voltage of the supply source (e.g. the PV panel or the PV string), R1 and R2 must be selected according to the following formula: V inmax R1 -–1 -------- = ----------------1.25 R2 Also, in order to optimize the efficiency of the whole system, when selecting R1 and R2, their power dissipation must be taken into account. Assuming negligible the current flowing through pin VIN_SNS, maximum power dissipation in the series R1+R2 is: Pvin _ sns = (Vin _ max)2 R1 + R2 As an empirical rule, R1 and R2 should be selected according to: Pvin _ sns Note: << .01x(Vin _ max Iin _ max) In order to guarantee the proper functionality of pin VIN_SNS, current flowing in the series R1+R2 should be in the range between 20 µA and 200 µA. Doc ID 17588 Rev 3 9/19 Detailed description 5.4 SPV1020 Output voltage sensing and overvoltage protection (OVP) Another monitoring is carried out on VOUT with the VOUT_SNS pin. This pin is used to monitor the output voltage in order to regulate it’s maximum value (which cannot exceed 40 V), preventing damage due to overvoltage. VOUT_SNS (the partitioned VOUT) is checked against a threshold of 1.0 V, generated by an internal regulated voltage. When VOUT_SNS reaches 1 V, the output feedback loop begins to regulate and limits the output voltage. The stability of the loop can be externally regulated by connecting a resistor and a capacitor (pole-zero compensation) between the PZ_OUT and SGND. If VOUT_SNS exceeds 1.04 V a fault signal is generated and transmitted to the fault controller. This stops the drivers and produces a fault signal to an external chip (DIAG = 0). When VOUT_SNS decreases down to 1.04 V, the boost converter begins to regulate again and the MPPT restarts from the minimum duty cycle of 5%. Referring to the schematic shown in Figure 1, R3 and R4 are the two resistors used to partition the output voltage. If VOUT_MAX is the maximum output voltage at the load, R3 and R4 must be selected according to the following rule: V outmax R3 -------- = --------------------–1 R4 1.02 Also, in order to optimize the efficiency of the whole system, when selecting R3 and R4, their power dissipation must be taken into account. Assuming negligible the current flowing through pin VOUT_SNS, maximum power dissipation in the series R3+R4 is: Pvout _ sns = (Vout _ max)2 R3 + R4 As an empirical rule, R3 and R4 should be selected according to: Pvout _ sns << .01x(Vout _ max Iout _ max) Note: In order to guarantee the proper functionality of pin Vout_sns, current flowing in the series R3+R4 should be in the range between 20 µA and 100 µA. 5.5 Overcurrent protection (OCP) To guarantee safe operation the low-side power switches have overcurrent protection. If LX is accidentally shorted to VIN or VOUT or when the current flowing through the inductor exceeds the current limit (~4.5 A), the related low-side power switch is immediately turned off and the linked synchronous rectifier is turned on. The low-side power switch is turned on again at the next PWM cycle. 10/19 Doc ID 17588 Rev 3 SPV1020 5.6 Detailed description Overtemperature protection (OTP) When the temperature sensed at silicon level reaches 150 °C, all low-side power switches are immediately turned off. The device becomes operative again as soon as the silicon temperature drops to 130 °C. 5.7 Shutdown In shutdown mode, the SHUT command sent to the converter switches the converter off to minimize power consumption. The synchronous rectifier intrinsic body diode causes a parasitic path between the power supply input and output, that cannot be avoided in shutdown. 5.8 Undervoltage lockout (UVLO) When solar radiation is too low or the PV cells are shaded, the energy generated may be too small to drive the converter. In this case, when the input voltage is lower than the UVLO threshold, all circuitry is in the OFF state, avoiding undesired power consumption. Hysteresis has been implemented to limit undesired switching of the internal reset circuits. 5.9 MPPT In order to maximize the energy transferred from the PV cell string to the DC bus (connected to the output of the converter) the converter embeds a logic running a Perturb&Observe MPPT algorithm based on monitoring the voltage and current supplied by the PV cells. If the operating voltage of the PV array is perturbed in a given direction and the power drawn from the PV array increases, this means that the operating point has moved towards the MPP and, therefore, the operating voltage must be further perturbed in the same direction. Otherwise, if the power drawn from the PV array decreases, the operating point has moved away from the MPP and, therefore, the direction of the operating voltage perturbation must be reversed 5.10 SPI The SPV1020 embeds a 4-pin compatible SPI interface. The SPI allows full duplex, synchronous, serial communication between a host controller (the master) and the SPV1020 peripheral device (the slave). The SPI master provides the synchronizing clock and starts the communication. The idle state of the serial clock for the SPV1020 is high. Data pins are driven on the falling edges of the serial clock and they are sampled on its rising edges. These features correspond to a clock polarity set to 1 (typical host SPI control bit CPOL=1) and to a clock phase set to 1 (typical host SPI control bit CPHA=1), respectively. The bit order of each byte is MSB first. When the master initiates a transmission, a data byte is shifted out through the MOSI pin to the slave, while another data byte is shifted out through the MISO pin to the master. The master controls the serial clock on the SCLK pin. The SS (active low) pin must be driven low by the master during each transmission. The bit order of each byte is MSB first. The SPV1020 register file is accessible by the host through the SPI bus. Therefore the host can read the SPV1020 control parameter register data. Each data frame includes at least Doc ID 17588 Rev 3 11/19 Detailed description SPV1020 one command byte followed by data bytes whose direction depends on the type of command. If the command byte requires data to be read from the register file, those data are transmitted from the slave to the master through the MISO pin. Therefore the master appends a number of NOPs (0x00) to the command so that the entire data can be transmitted, see Figure 4. The master must transmit a byte to receive a byte. If the SS wire goes high before the completion of a command byte in the data frame, the SPV1020 rejects that byte and the frame is closed. Then the next data frame is considered as a new one, starting with a command byte. Figure 4. Frame structure: register read operation The host can insert a short pause between each frame byte, or it can work in burst mode (no pause between frame bytes). Some data words can be longer than 8 bits, such as ADC results (10 bits). In such cases, data is first extended to the nearest multiple of one byte (right justified). Then it is split into bytes, e.g. the ADC result R is formatted as follows: Table 6. Data format for words longer than 8 bits Bit 0 Bit 7 MSB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Byte 1 0 0 0 0 0 0 R9 MSB R8 Byte 2 R7 R6 R5 R4 R3 R2 R1 R0 LSB LSB Table 7 shows a list of commands. Each command addresses a memory location of a certain width and sets the direction of the related data. 12/19 Doc ID 17588 Rev 3 SPV1020 Detailed description Table 7. 5.11 Commands list Code(Hex) Name R/W Comment 00 Not used RESERVED 01 NOP No operation 02 SHUT Shutdown 03 Turn ON Required only after SHUT command 04 Read current Read 10-bit 05 Read vin Read 10-bit 06 Read pwm Read 9-bit 07 Read status Read Read OVC (4-bit) OVV - OVT and CR 7-bit SPI timing diagram Figure 5 shows the SPI timing diagram. Figure 5. SPI timing diagram T scl k XCS Tlead Tpw SCLK Tl ag T td Tdh Tds MOSI Bit7 Bit6 Tdv Bit0 Tho MISO Bit7 Bit6 Bit0 Typical timing requirements are listed in Table 8 and are based on characterization; these parameters are not tested in production. Doc ID 17588 Rev 3 13/19 Detailed description Table 8. SPV1020 Typical timing requirements @ 25 °C, VDD=3.3 V Parameter 14/19 Description Min. Max. Units 6 MHz 167 ns Fsclk SCLK frequency Tsck SCLK period Tpw SCLK pulse width 80 ns Tlead SS lead time 80 ns Tlag SS lag time 80 ns Ttd Sequential transfer delay 80 ns Tds MOSI data setup time 8 ns Tdh MOSI data hold time 8 ns Tdv MISO data valid time Tho MISO data hold time Doc ID 17588 Rev 3 20 8 ns ns SPV1020 Typical curves 6 Typical curves Figure 6. Efficiency and power loss vs. input Figure 7. voltage ϵϴ͘ϱϬй ϲ ϵϵ͘ϬϬй ϵϴ͘ϬϬй ϱ ϵϴ͘ϬϬй ϵϳ͘ϱϬй ϯ ĨĨŝĐŝĞŶĐLJ WŽǁĞƌůŽƐƐ sŽƵƚс ϯϰs /ŽƵƚсϴ Ϯ ϭ ϵϳ͘ϬϬй ϵϳ͘ϬϬй ĨĨŝĐŝĞŶĐLJ й ϰ ĨĨŝĐŝĞŶĐLJ й WŽǁǁĞƌ>ŽƐƐt Efficiency vs. output current ϵϲ͘ϱϬй ϵϲ͘ϬϬй ϵϱ͘ϬϬй sŝŶсϭϮs ϵϰ͘ϬϬй sŝŶсϮϰs ϵϯ͘ϬϬй sŝŶсϯϬs ϵϮ͘ϬϬй ϵϭ͘ϬϬй Ϭ ϵϲ͘ϬϬй Ϭ ϱ ϭϬ ϭϱ ϮϬ Ϯϱ ϯϬ sŽƵƚс ϯϰs ϵϬ͘ϬϬй ϯϱ Ϭ ϭ Ϯ sŽůƚĂŐĞ/ŶƉƵƚs Figure 8. ϰ ϱ ϲ ϳ >ŽĂĚƵƌƌĞŶƚ Quiescent current vs. output voltage Figure 9. Quiescent current vs. temperature ϭϰ ϭϮ dсͲϰϬΣ ϭϬ dсϬΣ ϴ dсϯϱΣ ϲ dсϱϱΣ ϰ dсϳϱΣ WсϭϭϮt Ϯ Ϭ YƵŝĞƐĐĞŶƚƵƌƌĞŶƚŵ ϭϰ YƵŝĞƐĐĞŶƚƵƌƌĞŶƚŵ ϯ ϭϮ ϭϬ sŽƵƚсϰϬs ϴ sŽƵƚсϯϲs sŽƵƚсϮϴs ϰ dсϵϱΣ Ϯ dсϭϭϱΣ Ϭ ϭϴ ϮϬ ϮϮ Ϯϰ Ϯϲ Ϯϴ ϯϬ ϯϮ ϯϰ ϯϲ ϯϴ ϰϬ sŽƵƚсϯϮs ϲ sŽƵƚсϮϰs W сϭϭϮt sŽƵƚсϮϬs sŽƵƚсϭϴs ͲϰϬ ͲϮϱ ͲϭϬ KƵƚƉƵƚsŽůƚĂŐĞs ϱ ϮϬ ϯϱ ϱϬ ϲϱ ϴϬ ϵϱ ϭϭϬ dĞŵƉĞƌĂƚƵƌĞΣ Figure 10. Power efficiency mesured on the board ISV009v1 at TA=25 ° C ϭ Ϭ͘ϵϵ Ϭ͘ϵϴ WсϮϰϬt WŽƵƚͬWŝŶй Ϭ͘ϵϳ WсϮϭϬt Ϭ͘ϵϲ WсϭϴϬt Ϭ͘ϵϱ WсϭϱϬt Ϭ͘ϵϰ WсϭϮϬt Ϭ͘ϵϯ Ϭ͘ϵϮ WсϵϬt Ϭ͘ϵϭ WсϲϬt WсϯϬt Ϭ͘ϵ ϲ͘ϰ ϲ͘ϲ ϲ͘ϴ ϳ ϳ͘Ϯ ϳ͘ϰ ϳ͘ϲ /ŽƵƚ Doc ID 17588 Rev 3 15/19 Package mechanical data 7 SPV1020 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. Table 9. PowerSSO-36™ mechanical data mm Symbol Min. Typ. A 2.15 2.47 A2 2.15 2.40 a1 0 0.075 b 0.18 0.36 c 0.23 0.32 D 10.10 10.50 E 7.4 7.6 e 0.5 e3 8.5 F 2.3 G 0.075 G1 0.06 H 10.1 10.5 h L 0.4 0.55 M 0.85 4.3 N 16/19 Max. 10deg O 1.2 Q 0.8 S 2.9 T 3.65 U 1.0 X 4.1 4.7 Y 4.9 5.5 Doc ID 17588 Rev 3 SPV1020 Package mechanical data Figure 11. PowerSSO-36™ package dimensions Doc ID 17588 Rev 3 17/19 Revision history 8 SPV1020 Revision history Table 10. 18/19 Document revision history Date Revision Changes 07-Jun-2010 1 Initial release 15-Nov-2010 2 Updated Coverpage, Figure 1, Table 5 and Chapter 5 16-Jan-2012 3 Added Chapter 6, updated Figure 7 Minor text changes Doc ID 17588 Rev 3 SPV1020 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2012 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 17588 Rev 3 19/19