VNI8200XP Octal high-side smart power solid state relay with serial/parallel selectable interface on chip Datasheet − preliminary data Features Type Vdemag(1) RDS(on)(1) VNI8200XP VCC-45 V 0.11 Ω Iout(1) VCC 0.7 A 45 V 1. Per channel ■ Output current: 0.7 A per channel ■ Serial/parallel selectable interface ■ Short-circuit protection ■ 8-bit and 16-bit SPI Interface for IC command and control diagnostic ■ Channel overtemperature detection and protection ■ Thermal independence of separate channels ■ Drives all type of loads (resistive, capacitive, inductive load) ■ Loss of GND protection ■ Power Good diagnostic ■ Undervoltage shutdown with hysteresis ■ Overvoltage protection (VCC clamping) ■ Very low supply current ■ Common fault open drain output ■ IC warning temperature detection ■ Channels output enable ■ 100 mA high efficiency step-down switching regulator with integrated boot diode ■ Adjustable regulator output ■ Switching regulator disable ■ 5 V and 3.3 V compatible I/Os ■ Channel outputs status LED driving 4 x 2 multiplexed array ■ Fast demagnetization of inductive loads ■ ESD protection ■ Designed to meet IEC 61131-2, IEC61000-4-4, and IEC61000-4-5 June 2012 PowerSSO-36 Applications ■ Programmable logic control ■ Industrial PC peripheral input/output ■ Numerical control machines Table 1. Device summary Part number Package VNI8200XP Packing Tube PowerSSO-36 VNI8200XPTR Doc ID 15234 Rev 4 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Tape and reel 1/34 www.st.com 34 Contents VNI8200XP Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1 5 6 7 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.5 Protection and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.6 Step-down switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.7 LED driving array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Functional pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 SPI/parallel selection mode (SEL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 Serial data in (SDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.3 Serial data out (SDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.4 Serial data clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.5 Slave select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.6 8/16-bit selection (SEL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.7 Output enable (OUT_EN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.8 IC warning case temperature detection (TWARN) . . . . . . . . . . . . . . . . . . 16 6.9 Fault indication (FAULT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.10 Power Good (PG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.11 Programmable watchdog counter reset (WD) . . . . . . . . . . . . . . . . . . . . . 18 SPI operation (SEL2 = H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.1 2/34 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8-bit SPI mode (SEL1 = L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Doc ID 15234 Rev 4 VNI8200XP Contents 7.2 16-bit SPI mode (SEL1 = H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8 LED driving array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 Step-down switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 11.1 Thermal behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 12 Interface timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13 Switching parameters test conditions . . . . . . . . . . . . . . . . . . . . . . . . . 27 14 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Doc ID 15234 Rev 4 3/34 Description 1 VNI8200XP Description The VNI8200XP is a monolithic 8-channel driver featuring a very low supply current, with integrated SPI interface and high efficiency 100 mA micropower step-down switching regulator peak current control loop mode. The IC, realized in STMicroelectronics™ VIPower™ technology, is intended for driving any kind of load with one side connected to ground. Active channel current limitation combined with thermal shutdown, independent for each channel, and automatic restart, protect the device against overload. Additional embedded functions are: loss of GND protection that automatically turns off the device outputs in case of ground disconnection, undervoltage shutdown with hysteresis, Power Good diagnostic for valid supply voltage range recognition, output enable function for immediate power outputs ON/OFF, and programmable watchdog function for microcontroller safe operation; case overtemperature protection to control the IC case temperature. The device embeds a four-wire SPI serial peripheral with selectable 8 or 16-bit operations; through a select pin the device can also operate with a parallel interface. Both the 8-bit and 16-bit SPI operations are compatible with daisy chain connection. The SPI interface allows command of the output driver by enabling or disabling each channel featuring, in 16-bit format, a parity check control for communication robustness. It also allows the monitoring of the status of the IC signaling Power Good, overtemperature condition for each channel, IC pre-warning temperature detection. Built-in thermal shutdown protects the chip from overtemperature and short-circuit. In overload condition, the channel turns OFF and ON again automatically after the IC temperature decreases below a threshold fixed by a temperature hysteresis so that junction temperature is controlled. If this condition makes case temperature reaching case temperature limit, TCSD, overloaded channels are turned OFF and restart, nonsimultaneously, when case and junction temperature decrease below their own reset threshold. If the case of thermal reset, the channels loaded are not switched on until the junction temperature reset event. Non-overloaded channels continue to operate normally. Case temperature above TCSD is reported through the TWARN open drain pin. An internal circuit provides a not latched common FAULT indicator reporting if one of the following events occurs: channel OVT (overtemperature), parity check fail. The Power Good diagnostic warns the controller that the supply voltage is below a fixed threshold. The watchdog function is used to detect the occurrence of a software fault of the host controller. The watchdog circuitry generates an internal reset on expiry of the internal watchdog timer. The watchdog timer reset can be achieved by applying a negative pulse on the WD pin. The watchdog function can be disabled by the WD_EN dedicated pin. This pin also allows the programming of a wide range of watchdog timings. An internal LED matrix driver circuitry (4 rows, 2 columns) allows the detection of the status of the single outputs. An integrated step-down voltage regulator provides supply voltage to the internal LED matrix driver and logic output buffers and can be used to supply the external optocouplers if the application requires isolation. The regulator is protected against short-circuit or overload conditions by means of pulse-by-pulse current limit with a peak current control loop. 4/34 Doc ID 15234 Rev 4 VNI8200XP Block diagram &" $#$# #ONVERTER 5NDERVOLTAGEAND 0OWER'OOD 3%,). 7$?%.). /54?%.). 7$). 3$)). 6CC #LAMP #LAMP0OWER 30) ,OGIC #,+). 33). 3$/). #URRENT,IMITER *UNCTION4EM P $ETECTION 3%, 62%' 2/7 2/7 2/7 6## 0' $#6$$ 62%& 0(!3% Block diagram "//4 #ASE4EM P $ETECTION ,%$ $RIVNG 0ULL DOWN RESISTOR /54 /54 /54 /54 /54 /54 /54 /54 '.$ &!5,4 #/, 2/7 47!2. Figure 1. #/, 2 Block diagram !-V Doc ID 15234 Rev 4 5/34 Pin connection 3 VNI8200XP Pin connection Figure 2. Pin connection (top view) 3%, .# 3%,). .# 7$?%.). /54 /54?%.). /54 7$). /54 3$)). /54 #,+). /54 33). 4!"6CC /54 3$/). /54 62%' /54 #/, .# #/, "//4 $# 6$$ 0(!3% '.$ 62%& 2/7 &" 2/7 47!2. 2/7 &!5,4 2/7 0' ".W Table 2. 6/34 Pin description Pin Name Type Description 1 SEL2 Logic input SPI/parallel selection mode 2 SEL1/IN1 Logic input 8/16-bit SPI selection mode/channel 1 input 3 WD_EN/ IN2 Logic/analog input 4 OUT_EN /IN3 Logic input Output enable/channel 3 input 5 WD/IN4 Logic input Watchdog input. The internal watchdog counter is cleared on the falling edges/channel 4 input. 6 SDI/IN5 Logic input Serial data input/channel 5 input 7 CLK/IN6 Logic input Serial clock/channel 6 input 8 SS/IN7 Logic input Slave select/channel 7 input 9 SDO/IN8 Logic input/output 10 VREG Power supply 11 COL0 Open source output LED source output 12 COL1 Open source output LED source output 13 DCVDD Analog output Internally generated DC-DC low voltage supply. (To be connected to external 10 nF capacitor). 14 VREF Analog output Internally generated DC-DC voltage reference. (To be connected to external 10 nF capacitor). Watchdog enable_setting/channel 2 input Serial data output/channel 8 input SPI/inputs/LED supply voltage Doc ID 15234 Rev 4 VNI8200XP Pin connection Table 2. Pin description (continued) Pin Name Type 15 ROW0 Open drain output Status channel 1-2 16 ROW1 Open drain output Status channel 3-4 17 ROW2 Open drain output Status channel 5-6 18 ROW3 Open drain output Status channel 7-8 19 PG Open drain output Power Good diagnostic - active low 20 FAULT Open drain output Fault indication - active low 21 TWARN Open drain output IC case warning temperature detection - active low Analog input Description Step-down feedback input. Connecting the output voltage directly to this pin results in an output voltage of 3.3 V. An external resistor divider is required for higher output voltages. 22 FB 23 GND 24 PHASE Power output Step-down output 25 BOOT Power output Step-down bootstrap voltage. Used to provide a drive voltage, higher than the supply voltage, to power the switch of the step-down regulator. 26 NC 27 OUT8 Power output Channel 8 power output 28 OUT7 Power output Channel 7 power output 29 OUT6 Power output Channel 6 power output 30 OUT5 Power output Channel 5 power output 31 OUT4 Power output Channel 4 power output 32 OUT3 Power output Channel 3 power output 33 OUT2 Power output Channel 2 power output 34 OUT1 Power output Channel 1 power output 35 NC Not connected 36 NC Not connected TAB TAB Ground Not connected Power supply Exposed tab internally connected to VCC Doc ID 15234 Rev 4 7/34 Maximum ratings 4 VNI8200XP Maximum ratings Table 3. Absolute maximum ratings Symbol Parameter Value Unit 45 V -0.3 V VCC Power supply voltage -VCC Reverse supply voltage VREG Logic supply voltage -0.3 to +6 V Voltage range at pins TWARN, FAULT, PG -0.3 to +6 V VCC+6 V VFAULT VTWARN VPG VBOOT Bootstrap peak voltage VPHASE = Vcc VROW Voltage range at ROW pins -0.3 to +6 V VCOL Voltage range at COL pins -0.3 to +6 V Vdig Voltage level range at logic input pins -0.3 to +6 IOUT IR Output current (continuous) Reverse output current (per channel) Internally limited V (1) -5 A IGND DC ground reverse current -250 mA IREG VREG input current -1/10 mA Current range at pins TWARN, FAULT, PG -1 to +10 mA Input current range -1 to +10 mA Current range at ROW pins (ROW in ON state) +20 mA Current range at ROW pins (ROW in OFF state) -1 to +10 mA Current range at COL pins (COL in ON state) -10 mA Current range at COL pins (COL in OFF state) -1 to +10 mA IFAULT ITWARN, IPG IIN IROW ICOL VESD Electrostatic discharge (R = 1.5 kΩ; C = 100 pF) 2000 V EAS Single pulse avalanche energy per channel not simultaneously 300 mJ PTOT Power dissipation at Tc = 25 °C Internally limited(1) W TJ Junction operating temperature Internally limited °C -55 to 150 °C TSTG Storage temperature 1. Protection functions are intended to avoid IC damage in fault conditions and are not intended for continuous operation. Continuous and repetitive operation of protection functions may reduce the IC lifetime. 8/34 A Doc ID 15234 Rev 4 VNI8200XP 4.1 Electrical characteristics Thermal data Table 4. Thermal data Symbol Rth(JC) Rth(JA) Parameter Thermal resistance junction-case (1) Thermal resistance junction-ambient (2) Value Unit Max. 2 °C/W Max. 52 °C/W 1. Per channel. 2. When mounted using minimum recommended pad size on FR-4 board (for details refer to Section 11). 5 Electrical characteristics 5.1 Power section 10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified. Table 5. Symbol Vcc Power section Parameter Test conditions Supply voltage IS IDS 45 IOUT = 0.5 A at TJ = 25 °C IOUT = 0.5 A On state resistance Vcc supply current VREG supply current Unit 36 V 52 V 0.11 0.2 Ω 1 All channels in ON state, DCDC in ON state VREG=5 V, SPI ON (2) TBD DC-DC OFF VREG= 5 V SPI OFF WD_EN=0 TBD mA DC-DC ON VREG=5 V SPI ON WD_EN=VREG TBD mA All pins at 24 V except VOUT = 0V VOUT(OFF) OFF state output voltage VIN = 0 V, IOUT = 0 A IOUT(OFF) OFF state output current VIN = VOUT = 0 V Charge pump frequency Channel in ON state (3) FCP 50 Max. All channels in OFF state, DCDC in OFF state, VREG=5 V, SPI OFF(1) Output current at GND disconnection ILGND Typ. 10.5 VccClamp Clamp on Vcc RDS(ON) Min. 0 1.45 mA TBD mA 0.5 mA 3 V 5 µA MHz 1. SS signal high, NO communication. 2. SS signal low, communication ON. 3. To cover EN55022 class A and class B normatives. Doc ID 15234 Rev 4 9/34 Electrical characteristics 5.2 VNI8200XP SPI characteristics 10.5 V < VCC < 36 V; 2.7 V < VREG < 5 V; -40 <Tj <125; unless otherwise specified. Table 6. SPI characteristics Symbol Typ. Max. Unit SPI clock frequency - 5 MHz tr(CLK), tf(CLK) SPI clock rise/fall time - 20 ns tsu(SS) SS setup time 120 - ns th(SS) SS hold time 120 - ns tw(CLK) CLK high time 80 - ns tsu(SDI) Data input setup time 100 - ns th(SDI) Data input hold time 100 - ns ta(SDO) Data output access time - 100 ns tdis(SDO) Data output disable time - 200 ns tv(SDO) Data output valid time - 100 ns th(SDO) Data output hold time fCLK VSDO 5.3 Parameter Test conditions Voltage on serial data output ISDO = 15 mA Min. 0 - ns VREG-0.8 - V ISDO = -4 mA - 0.8 V Min. Typ. Max. Unit Switching VCC = 24 V; -40 °C < TJ < 125 °C. Table 7. Symbol td(ON) tr td(OFF) tf Switching Parameter Test condition Turn-ON delay time IOUT = 0.5 A, resistive load, input rise time < 0.1 µs - 5 - µs Rise time IOUT = 0.5 A, resistive load, input rise time < 0.1 µs - 5 - µs Turn-OFF delay time IOUT = 0.5 A, resistive load, input rise time < 0.1 µs - 10 - µs Fall time IOUT = 0.5 A, resistive load, input rise time < 0.1 µs - 5 - µs IOUT = 0.5 A, resistive load, input rise time < 0.1 µs - 3 - V/µs IOUT = 0.5 A, resistive load, input rise time < 0.1 µs - 4 - V/µs dV/dt(ON) Turn-ON voltage slope dV/dt(off) 10/34 Turn-OFF voltage slope Doc ID 15234 Rev 4 VNI8200XP 5.4 Electrical characteristics Logic inputs 10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified. Table 8. Logic inputs Symbol Parameter VIL Input low level voltage VIH Input high level voltage VI(HYST) IIN 5.5 Test conditions Min. Typ. Max. Unit 0.8 V 2.20 Input hysteresis voltage V 0.15 Input current VIN = 5 V V µA 8 Protection and diagnostic 10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified. Table 9. Protection and diagnostic Symbol Parameter VPGH1 Min. Typ. Max. Power Good diagnostic ON threshold 16.6 17.5 18.4 VPGH2 Power Good diagnostic OFF threshold 15.6 16.5 17.4 V VPGHYS Power Good diagnostic hysteresis 10.5 V VUSD VUSDHYS Test conditions Unit 1 Undervoltage ON protection 9.5 Undervoltage OFF protection 9 V 0.5 V VCC-52 VCC-50 VCC-45 V Undervoltage hysteresis 0.4 Vdemag Output voltage at turnOFF IOUT = 0.5 A; LLOAD ≥ 1 mH VTWARN TWARN pin low-state output voltage ITWARN = 3 mA (active condition) 0.6 V VFAULT FAULT pin low-state output voltage IFAULT = 3 mA (fault condition) 0.6 V 0.7 V VPG PG pin low-state output IPG = 3 mA (active condition) voltage VREG=3.3 V VCC=0 IPEAK Maximum DC output current ILIM Short-circuit current limitation per channel RLOAD = 0 Hyst ILIM tracking limits RLOAD = 0 1.4 Doc ID 15234 Rev 4 0.7 1.1 0.3 A 1.7 A A 11/34 Electrical characteristics Table 9. VNI8200XP Protection and diagnostic (continued) Symbol Parameter Test conditions ILFAULT FAULT leakage current ITWARN TWARN leakage current Min. Typ. Max. Unit 2 µA 170 °C Junction reset temperature 150 °C THIST Junction thermal hysteresis 20 °C TCSD Case shutdown temperature TCR Case reset temperature TCHYST Case thermal hysteresis IPG PG leakage current TTSD Junction shutdown temperature TR Vpin = 5 V 150 115 tWD Watchdog hold time See Figure 6 tWM Watchdog time See Table 13 and Figure 6 tOUT_EN OUT_EN pin propagation delay(1) tres OUT_EN hold time tWO Watchdog timeout(2) 130 145 °C 110 °C 20 °C 50 ns td(off) ms 50 ns tWM + td(off) ms 1. Time from reset active low and power out disable. 2. The time from tWM elapsed to power out disable. 5.6 Step-down switching regulator 10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified. Table 10. Symbol VDC_out VFB 12/34 Step-down switching regulator Parameter Test conditions Min. Typ. Max. Ireg from 0 to 100 mA VREG 3.3 V, Figure 8. 3.135 3.3 3.465 Regulated output voltage V Ireg from 0 to 100 mA VREG 5 V, Figure 10. Voltage feedback 5 3.135 RDSON MOSFET on-resistance IDC_out Regulator output current IPEAK Maximum peak current Unit Doc ID 15234 Rev 4 3.3 3.465 Ω 1.5 100 0.5 V mA A VNI8200XP Electrical characteristics Table 10. Step-down switching regulator (continued) Symbol Parameter Min. Total operating quiescent current Iqop Total standby quiescent current Iqst-by IBOOTleak Regulator standby Typ. Max. Unit TBD mA TBD µA Bootstrap reverse leakage current TBD µA fs Switching frequency 400 kHz Dmax Maximum duty cycle 80% % Minimum on-time TBD ns Tonmin 5.7 Test conditions LED driving array 10.5 V < VCC < 36 V; -40 °C < TJ < 125 °C; unless otherwise specified. Table 11. LED driving array Symbol Parameter VCOL Output source voltage at COL pins Output current 0 to VREG-0.3 VREG-0.2 7 mA VROW Open drain voltage at ROW pins Output current 0 to 15 mA Fsw Test conditions Row refresh frequency with duty=25% Doc ID 15234 Rev 4 Min. Typ. 0.2 780 Max. Unit V 0.3 V Hz 13/34 Functional pin description VNI8200XP 6 Functional pin description 6.1 SPI/parallel selection mode (SEL2) This pin allows the selection of the IC interfacing mode. The SPI interface is selected if SEL2 = H, while the parallel interface is selected if SEL2 = L, according to Table 12: Table 12. Pin description Function Pin SDO/IN8 SDO SS/IN7 SEL2(1) = H SEL2 = L SPI operation Parallel operation Serial data output IN8 Input to channel 8 SS Slave select IN7 Input to channel 7 CLK/IN6 CLK Serial clock IN6 Input to channel 6 SDI/IN5 SDI Serial data input IN5 Input to channel 5 WD/IN4 WD Watchdog input IN4 Input to channel 4 OUT_EN/IN3 OUT_EN IC OUTPUT enable / disable IN3 Input to channel 3 WD_EN/IN2 WD_EN Watchdog enable / disable and timing preset IN2 Input to channel 2 SEL1/IN1 SEL1 8/16-bit SPI selection mode IN1 Input to channel 1 1. SEL2 has an internal weak pull-down. 6.2 Serial data in (SDI) If SEL2 = H, this pin is the input of the serial control frame. SDI is read on CLK rising edges and, therefore, the microcontroller must change SDI state during the CLK falling edges. After the SS falling edge, the SDI is equal to the most significant bit of the control frame (Figure 3). 6.3 Serial data out (SDO) If SEL2 = H, this pin is the output of the serial fault frame. SDO is updated on CLK falling edges and, therefore, the microcontroller must read SDO state during the CLK rising edges. The SDO pin is tri-stated when SS signal is high and it is equal to the most significant bit of the fault frame after the SS falling edge (Figure 3). 14/34 Doc ID 15234 Rev 4 VNI8200XP 6.4 Functional pin description Serial data clock (CLK) If SEL2 = H, the CLK line is the input clock for serial data sampling. On CLK rising edge the SDI input is sampled by the IC and the SDO output is sampled by the host microcontroller. On CLK falling edge, both SDI and SDO lines are updated to the next bit of the frame, from the most to the less significant one (see Figure 3). When the SS signal is high, slave not selected, the microcontroller should drive the CLK low (the settings for the MCU SPI port are CPHA = 0 and CPOL = 0). 6.5 Slave select (SS) If SEL2 = H, the slave select (SS) signal is used to enable the VNI8200XP serial communication shift register; data is flushed-in through the SDI pin and flushed-out from the SDO pin only when the SS pin is low. On the SS pin falling edge the shift register (containing the fault conditions) is frozen, so any change on the power switches status is latched until the next SS falling edge event and the SDO output is enabled. On the SS pin rising edge event the 8/16 bits present on the SPI shift register are evaluated and the outputs are driven according to this frame. If more than 8/16 bits (depending on the SPI settings) are flushed inside only the last 8/16 are evaluated; the others are flushed out from the SDO pin after fault condition bits; in this way a proper communication is possible also in a daisy chain configuration. Figure 3. 6.6 SPI mode diagram 8/16-bit selection (SEL1) If SEL2 = H, SEL1 is used to select between two possible SPI configurations: the 8-bit SPI mode (SEL1 = L) and the 16-bit SPI mode (SEL1 = H). 8/16-bit SPI operation is described below. Doc ID 15234 Rev 4 15/34 Functional pin description 6.7 VNI8200XP Output enable (OUT_EN) If SEL2 = H, the OUT_EN pin provides a fast way to disable all the outputs simultaneously. When the OUT_EN pin is driven low for at least TRES, the outputs are disabled while fault conditions in the SPI register are latched. To enable the outputs it is then necessary to raise the OUT_EN pin and re-program the IC through the SPI interface. As fault conditions are latched inside the IC and SPI interface is working also while the OUT_EN pin is driven low, it’s possible to use SPI to detect if a fault condition occurred before the reset event. The device is ready to operate normally after a TSU period. The OUT_EN pin is the fastest way to disable all the outputs when a fault occurs. Figure 4. Output channel enable/disable behavior OUT_EN t Vin( i) t OUT(i) t tOUT_EN AM12824v1 6.8 IC warning case temperature detection (TWARN) The TWARN pin is an active low open drain output. This pin is activated if the IC case temperature exceeds TCSD. According to the PCB thermal design and RthJC value, this function allows a warning about a PCB overheating condition to be given. The TWARN bit is also available through SPI. This bit is not latched: the TWARN pin is low only while the case overtemperature condition is active (TC > TCSD) and is released when this condition is removed (TC < TCR). 16/34 Doc ID 15234 Rev 4 VNI8200XP 6.9 Functional pin description Fault indication (FAULT) The FAULT pin is an open drain active low fault indication pin. This pin is activated by one or more of the following conditions: ● Channel overtemperature (OVT) This pin is activated when at least one of the channels is in junction overtemperature. Unlike the SPI fault detection bits, this signal is not latched: the FAULT pin is low only when the fault condition is active and is released if the input driving signal is off or after the OVT protection condition has been removed. This last event occurs if the channel temperature decreases below the threshold level and the case temperature has not exceeded TCSD or is below TCR. This means that the FAULT pin is low only while the junction overtemperature is active (TJ >TTSD) and is released after this condition has been removed (TJ < TR and TC < TCR). ● Parity check fail When SPI mode is used (SEL2 = H), if a parity check fault of the incoming SPI frame is detected or counted, CLK rising edges are different by a multiple of 8, the FAULT pin is kept low. When counted CLK rising edges are a multiple of 8 and parity check is valid, the FAULT pin is kept high. 6.10 Power Good (PG) The PG terminal is an open drain, that indicates the status of the supply voltage. When VCC supply voltage reaches the Vsth1 threshold, PG goes into a high impedance state. It goes into a low impedance state when VCC falls below the Vsth2 threshold. In 16-bit SPI mode, a PG bit is also available. This bit is set high when the Power Good diagnostic is active, it is otherwise cleared. Figure 5. Power Good diagnostic 0' 60'( 60'( 6CC !-V Doc ID 15234 Rev 4 17/34 Functional pin description 6.11 VNI8200XP Programmable watchdog counter reset (WD) If SEL2 = H, the VNI8200XP embeds a watchdog counter that must be erased, with a negative pulse on the WD pin, before it expires. If the WD counter elapses, the VNI8200XP goes into an internal RESET state where all the outputs are disabled; to restart normal operation a negative pulse must be applied at the WD pin. The watchdog enable/disable pin should be connected through an external divider to VREG. The watchdog time is fixed following Table 13: Table 13. Programmable watchdog time VWD_EN tWM 0.25 VREG > VWD_EN Disable 0.25 VREG ≤VWD_EN < 0.5 VREG 40 ± 10% ms 0.5 VREG ≤VWD_EN < 0.75 VREG 80 ± 10% ms 0.75 VREG ≤VWD_EN = VREG 160 ± 10% ms Figure 6. Watchdog reset WD tWM tWD t AM11802v1 18/34 Doc ID 15234 Rev 4 VNI8200XP SPI operation (SEL2 = H) 7 SPI operation (SEL2 = H) 7.1 8-bit SPI mode (SEL1 = L) If SEL2 = H, the 8-bit SPI mode is based on an 8-bit command frame sent from the microcontroller to the IC; each bit directly drives the corresponding output where LSB drives output 0 and MSB drives output 7. Each bit, set to ‘1’, activates (closes) the corresponding output. At the same time, the IC transfers the channel fault conditions (OVT) to the microcontroller. These fault conditions are latched at the occurrence and cleared after each communication (each time the SS signal has a positive transition). Each bit, set to ‘1’, indicates an OVT condition for the corresponding channel. Table 14. Command 8-bit frame (master to slave) MSB LSB IN7 IN6 Table 15. IN5 IN4 IN3 IN2 IN1 IN0 Fault 8-bit frame (slave to master) MSB LSB F7 7.2 F6 F5 F4 F3 F2 F1 F0 16-bit SPI mode (SEL1 = H) The 16-bit SPI mode is based on a 16-bit command frame sent from the microcontroller to the IC; the first 8 bits directly drive the output channels (each bit, set to ‘1’, activates the corresponding output), the other 8 bits contain a 4-bit parity check code where the last bit (the inversion of the previous one) is used to detect a communication error condition (providing at least a transition in each frame): P0 = IN0 ⊕ IN1 ⊕ IN2 ⊕ IN3 ⊕ IN4 ⊕ IN5 ⊕ IN6 ⊕ IN7 P1 = IN1 ⊕ IN3 ⊕ IN5 ⊕ IN7 P2 = IN0 ⊕ IN2 ⊕ IN4 ⊕ IN6 nP0 = NOT P0 Table 16. Command 16-bit frame (master to slave) MSB IN7 LSB IN6 IN5 IN4 IN3 IN2 IN1 IN0 - - - - P2 P1 P0 nP0 At the same time, the IC transfers to the microcontroller a 16-bit fault frame where the first 8 bits indicate a channel fault (OVT) condition (each bit, set to ‘1’, indicates an OVT event), the following 4 bits provide general fault condition information. FB_OK: this bit is related to the DC-DC regulation: at the DC-DC turn-on, this bit is low and becomes high after FB rises above 90% of the nominal VFB voltage and a correct SPI communication occurred. If the FB voltage falls below 80% of the nominal VFB voltage, this bit is zero; TWARN (IC warning Doc ID 15234 Rev 4 19/34 SPI operation (SEL2 = H) VNI8200XP case temperature, see Section 6.8), PC (parity check fail, the bit, set to ‘1’, indicates a PC fail or the length is not a multiple of 8) and PG (Power Good, see Section 6.10). The last 4 bits are used as parity check bits and communication error condition (see command 16 bit frame): P0 = F0 ⊕ F1 ⊕ F2 ⊕ F3 ⊕ F4 ⊕ F5 ⊕ F6 ⊕ F7 P1 = PC ⊕ FB_OK ⊕ F1 ⊕ F3 ⊕ F5 ⊕ F7 P2 = PG ⊕ TWARN ⊕ F0 ⊕ F2 ⊕ F4 ⊕ F6 nP0 = NOT P0 Table 17. Fault 16-bit frame slave to master MSB F7 LSB F6 F5 F4 F3 F2 F1 F0 FB_OK TWARN PC PG P2 Channel indications are latched and cleared only after a communication. 20/34 Doc ID 15234 Rev 4 P1 P0 nP0 VNI8200XP 8 LED driving array LED driving array Figure 7. LED driving array 2/7 2/7 2/7 #/, #/, 62%' 34!453 34!453 34!453 34!453 34!453 34!453 34!453 2/7 34!453 !-V The following is an indication of how to choose the Rext resistors value. Equation 1 ( VCOLmin ) – ( V ROWmax ) – VF ( LED ) R ext = ------------------------------------------------------------------------------------------IF ( LED ) Note: IF(LED) ≤7 mA. Where (VCOL min.) and (VROW max.) can be found in Table 11 and VF(LED) and IF(LED) depend on the electrical characteristics of the LEDs. Doc ID 15234 Rev 4 21/34 Step-down switching regulator 9 VNI8200XP Step-down switching regulator The IC embeds a high efficiency 100 mA micropower step-down switching regulator. The regulator is protected against short-circuit or overload conditions. Pulse-by-pulse current limit regulation is obtained in normal operation through a current loop control. A low ESR output capacitor connected to the VREG pin helps to limit the regulated voltage ripple; a low ESR (less than 10 mΩ) capacitor is preferable. The control loop pin FB allows 3.3 V to be regulated, connecting it directly to VREG, or 5 V connecting it through a voltage divider Rl/Rfbl. The DC-DC converter can be turned off by connecting the feedback pin to the DCVDD pin. In some applications it is possible to supply a 5 V or 3.3 V voltage externally or, in the case of two or more VNI8200XPs inside the same board, it's possible to configure the DC-DC converter on only one device and supply also the other ICs. 22/34 Doc ID 15234 Rev 4 VNI8200XP 10 Conventions Conventions Figure 8. Typical circuit for switching regulation VDC-out = 3.3 V 3%, .# 3%,). .# 7$?%.). /54 /54?%.). /54 7$). /54 3$)). /54 #,+). /54 33). /54 3$/). /54 #/, #/, $#6$$ # N& # N& /54 62%' 4AB6CC .# "//4 0(!3% 62%& &" 2/7 '.$ 2/7 47!2. 2/7 &!5,4 2/7 0' # N& , )REG U(2)SM! 2 K 2 K 6REG # N& 6.) # U& LOW%32MOHM-,# # !-V Doc ID 15234 Rev 4 23/34 Conventions VNI8200XP Figure 9. Typical circuit for switching regulation VDC-out = 5 V # N& # N& .# 3%, .# 3%,). 7$?%.). /54 /54?%.). /54 7$). /54 3$)). /54 #,+). /54 33). /54 3$/). /54 /54 62%' #/, 4AB6CC .# #/, "//4 $#6$$ 0(!3% 62%& &" 2/7 '.$ 2/7 47!2. 2/7 &!5,4 2/7 0' # N& , )REG U(2)SM! 2 K 2 K # N& 6REG 6.) 2 K # U& LOW%32MOHM -,## !-V Figure 10. SPI directional logic convention 3$) 6REG 33 #,+ /54 3$/ /54 7$ /54 /54?%. 7$?%. 4!"6CC /54 /54 /54 3%, /54 3%, /54 0' &!5,4 47!2. '.$ !-V 24/34 Doc ID 15234 Rev 4 VNI8200XP 11 Thermal management Thermal management The power dissipation in the IC is the main factor that sets the safe operating condition of the device in the application. Therefore, it must be taken into account very carefully. Heatsinking can be achieved using copper on the PCB with proper area and thickness. The following image (Figure 11) shows the junction-to-ambient thermal impedance values for the PSSO36 package. Figure 11. PSSO36 thermal impedance vs. time For instance, three cases have been considered using a PSSO36 packaged with copper slug soldered on a 1.6 mm thickness FR4 board with dissipating footprint (copper thickness of 70 µm): ● single layer PCB with just IC footprint dissipating area ● double layer PCB with footprint dissipating area on the top side and a 2 cm2 dissipating layer on the bottom side through 15 via holes ● double layer PCB with footprint dissipating area on the top side and an 8 cm2 dissipating layer on the bottom side through 15 via holes. Doc ID 15234 Rev 4 25/34 Thermal management 11.1 VNI8200XP Thermal behavior Figure 12. Thermal behavior 6INI( /54I/N 34!4I/FF( 1 ./ 4JI4TSD 9%3 /54I/FF 34!4I/N, 4 9%3 4C4CSD ./ 2 9%3 ./ 4C4CR ./ 4JI4JR 9%3 3 !-V Note: 26/34 1 Thermal shutdown. 2 Junction hysteresis. 3 Restore to idle condition. 4 Case hysteresis. Doc ID 15234 Rev 4 VNI8200XP 12 Interface timing diagram Interface timing diagram Figure 13. Serial timing Switching parameters test conditions Figure 14. dV/dt(ON) and dV/dt(OFF) time diagram test conditions 6OUT D6/&& D6/. 13 TR TF T !-V Doc ID 15234 Rev 4 27/34 Switching parameters test conditions VNI8200XP Figure 15. td(ON) and td(OFF) time diagram test conditions ^^ ϱϬй ƚĚ;K&&Ϳ ƚ sŽƵƚ ϵϬй ϭϬй ƚ ƚĚ;KEͿ !-V 28/34 Doc ID 15234 Rev 4 VNI8200XP 14 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 18. PowerSSO-36 mechanical data mm Symbol Min. Typ. Max. A 2.15 2.47 A2 2.15 2.40 a1 0 0.075 b 0.18 0.36 c 0.23 0.32 D 10.10 10.50 E 7.4 7.6 e 0.5 e3 8.5 F 2.3 G 0.075 G1 0.06 H 10.1 10.5 h L 0.4 0.55 M 0.85 4.3 N 10deg O 1.2 Q 0.8 S 2.9 T 3.65 U 1.0 X 4.1 4.7 Y 4.9 5.5 Doc ID 15234 Rev 4 29/34 Package mechanical data VNI8200XP Figure 16. PowerSSO-36 package dimensions Figure 17. PowerSSO-36 tube shipment (no suffix) Table 19. Note: 30/34 PowerSSO-36 tube shipment Base Q.ty 49 Bulk Q.ty 1225 Tube length (± 0.5) 532 A 3.5 B 13.8 C (± 0.1) 0.6 All dimensions are in mm. Doc ID 15234 Rev 4 VNI8200XP Package mechanical data Figure 18. PowerSSO-36 reel shipment (suffix “TR”) Table 20. PowerSSO-36 reel dimensions Base Q.ty 1000 Bulk Q.ty 1000 A (max.) 330 B (min.) 1.5 C (± 0.2) 13 F 20.2 G (2 ± 0) 24.4 N (min.) 100 T (max.) 30.4 Doc ID 15234 Rev 4 31/34 Package mechanical data VNI8200XP Figure 19. PowerSSO-36 tape dimensions Table 21. Note: 32/34 PowerSSO-36 tape dimensions Tape width W 24 Tape hole spacing P0 (± 0.1) 4 Component spacing P 12 Hole diameter D (± 0.05) 1.55 Hole diameter D1 (min.) 1.5 Hole position F (± 0.1) 11.5 Compartment depth K (max.) 2.85 Hole spacing P1 (± 0.1) 2 According to the Electronic Industries Association (EIA) standard 481 rev. A, Feb 1986. Doc ID 15234 Rev 4 VNI8200XP 15 Revision history Revision history Table 22. Document revision history Date Revision Changes 04-Dec-2008 1 Initial release 29-Apr-2009 2 Updated Table 5 on page 9 19-Jun-2012 3 Updated: Features,Section 6.4,Section 6.7,Section 6.9,Section 6.10, Section 9,Table 2,Table 3,Table 5,Table 7,Table 8,Table 9, Table 10,Table 11,Table 13,Figure 1,Figure 2. Changed: Figure 4,Figure 5,Figure 6,Figure 14,Figure 15. Content reworked to improve the readability. 27-Jun-2012 4 Changed: Symbols in 16-bit frame Section 7.2 . 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