VN820-E / VN820B5-E VN820PT-E / VN820SO-E / VN820SP-E HIGH SIDE DRIVER Table 1. General Features Type VN820-E VN820B5-E VN820PT-E VN820SO-E VN820SP-E Figure 1. Package RDS(on) IOUT VCC 40 mΩ 9A 36 V 10 1 PowerSO-10™ CMOS COMPATIBLE INPUT ON STATE OPEN LOAD DETECTION ■ OFF STATE OPEN LOAD DETECTION ■ SHORTED LOAD PROTECTION ■ UNDERVOLTAGE AND OVERVOLTAGE SHUTDOWN ■ PROTECTION AGAINST LOSS OF GROUND ■ VERY LOW STAND-BY CURRENT P2PAK PPAK ■ ■ ■ ■ PENTAWATT SO-16L Active current limitation combined with thermal shutdown and automatic restart protect the device against overload. The device detects open load condition both is on and off state. Output shorted to V CC is detected in the off state. Device automatically turns off in case of ground pin disconnection. REVERSE BATTERY PROTECTION (*) IN COMPLIANCE WITH THE 2002/95/EC EUROPEAN DIRECTIVE DESCRIPTION The VN820-E, VN820SP-E, VN820B5-E, VN820SO-E, VN820PT-E are monolithic devices made by using STMicroelectronics VIPower M0-3 Technology, intended for driving any kind of load with one side connected to ground. Active V CC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). Table 2. Order Codes Package Tube Tape and Reel PENTAWATT VN820-E - PowerSO-10™ VN820SP-E VN820SPTR-E P2PAK VN820B5-E VN820-B5TR-E SO-16L VN820SO-E VN820SOTR-E PPAK VN820PT-E VN820PTTR-E Note: (*) See application schematic at page 9. Rev. 3 February 2005 1/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 2. Block Diagram VCC OVERVOLTAGE DETECTION VCC CLAMP UNDERVOLTAGE DETECTION GND Power CLAMP DRIVER INPUT OUTPUT LOGIC CURRENT LIMITER ON STATE OPENLOAD DETECTION STATUS OVERTEMPERATURE DETECTION OFF STATE OPENLOAD AND OUTPUT SHORTED TO VCC DETECTION Table 3. Absolute Maximum Ratings Symbol VCC - VCC - IGND IOUT - IOUT IIN ISTAT Parameter DC Supply Voltage Reverse DC Supply Voltage DC Reverse Ground Pin Current DC Output Current Reverse DC Output Current DC Input Current DC Status Current Electrostatic Discharge Value PowerSO-10 PENTAWATT P2PAK SO-16L PPAK 41 - 0.3 - 200 Internally Limited -9 +/- 10 +/- 10 Unit V V mA A A mA mA (Human Body Model: R=1.5KΩ; C=100pF) VESD EMAX EMAX EMAX Ptot Tj Tc Tstg 2/38 - INPUT 4000 V - STATUS 4000 V - OUTPUT 5000 V - VCC Maximum Switching Energy (L=4mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=13A) Maximum Switching Energy (L=3.7mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=13A) Maximum Switching Energy (L=4.48mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=13A) Power Dissipation TC=25°C Junction Operating Temperature Case Operating Temperature Storage Temperature 5000 V 481 481 mJ 438 65.8 65.8 65.8 Internally Limited - 40 to 150 - 55 to 150 8.3 mJ 526 mJ 65.8 W °C °C °C VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins 1 VCC 16 GROUND INPUT 6 5 OUTPUT 7 4 STATUS N.C. N.C. 8 3 OUTPUT OUTPUT 9 2 OUTPUT 10 1 OUTPUT GND OUTPUT INPUT OUTPUT STATUS OUTPUT N.C. OUTPUT OUTPUT N.C. 11 VCC 8 VCC PPAK / P2PAK / PENTAWATT PowerSO-10 Connection / Pin Status Floating X To Ground N.C. X X Output X VCC OUTPUT N.C. 9 VCC SO-16L Input X Through 10KΩ resistor Figure 4. Current and Voltage Conventions IS VF IIN VCC INPUT ISTAT IOUT STATUS VCC OUTPUT GND VIN VSTAT IGND VOUT Table 4. Thermal Data Symbol Rthj-case Rthj-lead Rthj-amb Rthj-amb Parameter Thermal Resistance Junction-case Thermal Resistance Junction-lead Thermal Resistance Junction-ambient Thermal Resistance Junction-ambient Max Max Max Max Value PowerSO-10 PENTAWATT P2PAK SO-16L PPAK 1.9 1.9 1.9 1.9 15 (1) (1) (1) (2) 51.9 61.9 51.9 65 76.9 (1) (3) (3) (4) 37 37 48 45 (3) Unit °C/W °C/W °C/W °C/W (1) When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35µm thick). When mounted on FR4 printed circuit board with 0.5cm2 of Cu (at least 35µ thick) connected to all VCC pins. (3) When mounted on a standard single-sided FR-4 board with 6cm2 of Cu (at least 35µm thick). (4) When mounted on FR4 printed circuit board with 6cm2 of Cu (at least 35µ thick) connected to all VCC pins. (2) 3/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E ELECTRICAL CHARACTERISTICS (8V<VCC<36V; -40°C<Tj<150°C unless otherwise specified) Table 5. Power Symbol Parameter VCC Min. Typ. Max. Unit Operating Supply Voltage 5.5 13 36 V VUSD Undervoltage Shut-down 3 4 5.5 V VUSDhyst Undervoltage Shut-down hysteresis VOV Overvoltage Shut-down RON On State Resistance IS Supply Current Test Conditions 0.5 V 36 V IOUT=3A; Tj=25°C; VCC>8V 40 mΩ IOUT=3A; VCC>8V 80 mΩ 25 µA Off State; VCC=13V; VIN=VOUT=0V Off State; VCC=13V; VIN=VOUT=0V; Tj=25°C 10 10 20 µA On State; VCC=13V; VIN=5V; IOUT=0A 2 3.5 mA 0 50 µA -75 0 µA IL(off1) Off State Output Current VIN=VOUT=0V IL(off2) Off State Output Current VIN=0V; VOUT =3.5V IL(off3) Off State Output Current VIN=VOUT=0V; Vcc=13V; Tj =125°C 5 µA IL(off4) Off State Output Current VIN=VOUT=0V; Vcc=13V; Tj =25°C 3 µA Max. Unit Table 6. Switching (VCC =13V) Symbol Parameter Test Conditions Min. Typ. td(on) Turn-on Delay Time RL=4.3Ω from VIN rising edge to VOUT =1.3V 30 µs td(off) Turn-off Delay Time RL=4.3Ω from VIN falling edge to VOUT =11.7V 30 µs dVOUT / dt(on) Turn-on Voltage Slope RL=4.3Ω from VOUT=1.3 to VOUT =10.4V See relative diagram V/µs dVOUT / dt(off) Turn-off Voltage Slope RL=4.3Ω from VOUT=11.7 to VOUT =1.3V See relative diagram V/µs Table 7. Input Pin Symbol Parameter VIL Input Low Level IIL Low Level Input Current VIH Input High Level IIH High Level Input Current VI(hyst) Input Hysteresis Voltage VICL 4/38 Input Clamp Voltage Test Conditions VIN=1.25V Min. Typ. Max. Unit 1.25 V 1 µA 3.25 V VIN=3.25V 10 0.5 IIN=1mA IIN=-1mA 6 µA V 6.8 -0.7 8 V V VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E ELECTRICAL CHARACTERISTICS (continued) Table 8. VCC - Output Diode Symbol VF Parameter Test Conditions Forward on Voltage Min. Typ. -IOUT=2A; Tj=150°C Max. Unit 0.6 V Max 0.5 10 Unit V µA 100 pF 8 V Table 9. Status Pin Symbol VSTAT ILSTAT CSTAT VSCL Parameter Test Conditions Status Low Output Voltage ISTAT =1.6mA Status Leakage Current Normal Operation VSTAT=5V Status Pin Input Normal Operation VSTAT=5V Capacitance ISTAT =1mA Status Clamp Voltage ISTAT =-1mA Min 6 Typ 6.8 -0.7 V Table 10. Protections (see note 1) Symbol TTSD TR Thyst tSDL Parameter Shut-down Temperature Reset Temperature Thermal Hysteresis Status delay in overload condition Ilim Current limitation Vdemag Turn-off Output Clamp Voltage Test Conditions Min 150 135 7 Typ 175 13 5.5V<VCC<36V IOUT=3A; VIN=0V; L=6mH VCC-41 Unit °C °C °C 20 µs 20 A 20 A VCC-55 V 15 Tj>TTSD 9 Max 200 VCC-48 Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles. Table 11. Openload Detection Symbol IOL tDOL(on) VOL tDOL(off) Parameter Openload ON State Detection Threshold Openload ON State Detection Delay Openload OFF State Voltage Detection Threshold Openload Detection Delay at Turn Off Test Conditions VIN=5V Min Typ Max Unit 70 150 300 mA 200 µs 3.5 V 1000 µs IOUT =0A VIN=0V 1.5 2.5 5/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 5. OPEN LOAD STATUS TIMING (with external pull-up) IOUT < IOL VOUT > VOL OVERTEMP STATUS TIMING Tj > Tjsh VIN VIN VSTAT VSTAT tDOL(off) tDOL(on) tSDL tSDL Table 12. Truth Table CONDITIONS INPUT OUTPUT STATUS Normal Operation L H L H H H Current Limitation L H H L X X H (Tj < TTSD) H (Tj > TTSD) L Overtemperature L H L L H L Undervoltage L H L L X X Overvoltage L H L L H H Output Voltage > VOL L H H H L H Output Current < IOL L H L H H L Figure 6. Switching time Waveforms VOUTn 90% 80% dVOUT/dt(off) dVOUT/dt(on) 10% t VINn td(on) td(off) t 6/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Table 13. Electrical Transient Requirements On V CC Pin TEST LEVELS ISO T/R 7637/1 Test Pulse I II III IV 1 2 3a 3b 4 5 -25 V +25 V -25 V +25 V -4 V +26.5 V -50 V +50 V -50 V +50 V -5 V +46.5 V -75 V +75 V -100 V +75 V -6 V +66.5 V -100 V +100 V -150 V +100 V -7 V +86.5 V ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E Delays and Impedance 2 ms 10 Ω 0.2 ms 10 Ω 0.1 µs 50 Ω 0.1 µs 50 Ω 100 ms, 0.01 Ω 400 ms, 2 Ω I TEST LEVELS RESULTS II III IV C C C C C C C C C C C E C C C C C E C C C C C E CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 7/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 7. Waveforms NORMAL OPERATION INPUT LOAD VOLTAGE STATUS UNDERVOLTAGE VUSDhyst VCC VUSD INPUT LOAD VOLTAGE STATUS undefined OVERVOLTAGE VCC<VOV VCC>VOV VCC INPUT LOAD VOLTAGE STATUS OPEN LOAD with external pull-up INPUT VOUT >VOL LOAD VOLTAGE VOL STATUS OPEN LOAD without external pull-up INPUT LOAD VOLTAGE STATUS Tj INPUT LOAD CURRENT STATUS 8/38 TTSD TR OVERTEMPERATURE VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 8. Application Schematic +5V +5V VCC Rprot STATUS Dld µC Rprot INPUT OUTPUT GND RGND VGND GND PROTECTION REVERSE BATTERY NETWORK AGAINST Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND ≤ 600mV / (IS(on)max). 2) RGND ≥ (−VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device’s datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSD. Also in this case, the presence of DGND the ground network will produce a shift (j600mV) in the input threshold and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. Series resistor in INPUT and STATUS lines are also required to prevent that, during battery voltage transient, the current exceeds the Absolute Maximum Rating. Safest configuration for unused INPUT and STATUS pin is to leave them unconnected. LOAD DUMP PROTECTION Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table. µC I/Os PROTECTION: If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the µC I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of µC and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC I/Os. -VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V 5kΩ ≤ Rprot ≤ 65kΩ. Recommended Rprot value is 10kΩ. 9/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E VOUT=(VPU/(RL+RPU))RL<VOlmin. 2) no misdetection when load is disconnected: in this case the VOUT has to be higher than VOLmax; this results in the following condition RPU<(VPU–VOLmax)/ IL(off2). Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pull-up resistor RPU should be connected to a supply that is switched OFF when the module is in standby. The values of VOLmin, VOLmax and IL(off2) are available in the Electrical Characteristics section. OPEN LOAD DETECTION IN OFF STATE Off state open load detection requires an external pull-up resistor (RPU) connected between OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the microprocessor. The external resistor has to be selected according to the following requirements: 1) no false open load indication when load is connected: in this case we have to avoid VOUT to be higher than VOlmin; this results in the following condition Figure 9. Open Load detection in off state V batt. VPU VCC RPU INPUT DRIVER + LOGIC IL(off2) OUT + R STATUS VOL GROUND 10/38 RL VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 10. Off State Output Current Figure 11. High Level Input Current Iih (uA) IL(off1) (µA) 5 5 4.5 4.5 Off state Vcc=36V Vin=Vout=0V 4 3.5 Vin=3.25V 4 3.5 3 3 2.5 2.5 2 2 1.5 1.5 1 1 0.5 0.5 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 125 150 175 125 150 175 Tc (°C) Tc (ºC) Figure 12. Input Clamp Voltage Figure 14. Status Leakage Current Ilstat (uA) Vicl (V) 8 0.05 7.8 Iin=1mA 0.04 7.6 7.4 Vstat=5V 0.03 7.2 7 0.02 6.8 6.6 0.01 6.4 6.2 0 6 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 Tc (°C) Tc (°C) Figure 13. Status Low Output Voltage Figure 15. Status Clamp Voltage Vscl (V) Vstat (V) 8 0.8 7.8 0.7 Istat=1mA Istat=1.6mA 7.6 0.6 7.4 0.5 7.2 7 0.4 6.8 0.3 6.6 0.2 6.4 0.1 6.2 6 0 -50 -25 0 25 50 75 Tc (°C) 100 125 150 175 -50 -25 0 25 50 75 100 Tc (°C) 11/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 16. On State Resistance Vs Tcase Figure 17. On State Resistance Vs VCC Ron (mOhm) Ron (mOhm) 100 100 90 90 Iout=3A Vcc=8V; 13V; 36V 80 80 Tc= 150ºC 70 70 60 60 50 50 40 40 30 30 20 20 10 10 Tc= 25ºC Tc= - 40ºC 0 0 -50 -25 0 25 50 75 100 125 150 5 175 10 15 20 Figure 18. Openload On State Detection Threshold 30 35 40 Figure 20. Openload Off State Voltage Detection Threshold Vol (V) Iol (mA) 5 150 4.5 140 Vin=0V Vcc=13V Vin=5V 130 4 3.5 120 110 3 100 2.5 90 2 80 1.5 70 1 60 0.5 0 50 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 Tc (°C) Tc (°C) Figure 19. Input High Level Figure 21. Input Low Level Vih (V) Vil (V) 3.6 2.6 3.4 2.4 3.2 2.2 3 2 2.8 1.8 2.6 1.6 2.4 1.4 2.2 1.2 2 1 -50 -25 0 25 50 75 Tc (°C) 12/38 25 Vcc (V) Tc (ºC) 100 125 150 175 -50 -25 0 25 50 75 Tc (°C) 100 125 150 175 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 22. Turn-on Voltage Slope Figure 25. Turn-off Voltage Slope dVout/dt(on) (V/ms) dVout/dt(off) (V/ms) 1000 1000 900 900 Vcc=13V Rl=4.3Ohm 800 Vcc=13V Rl=4.3Ohm 800 700 700 600 600 500 500 400 400 300 300 200 200 100 100 0 0 -50 -25 0 25 50 75 100 125 150 -50 175 -25 0 25 50 75 100 125 150 175 125 150 175 Tc (ºC) Tc (ºC) Figure 23. Overvoltage Shutdown Figure 26. ILIM Vs Tcase Vov (V) Ilim (A) 50 20 48 18 46 16 44 14 42 12 40 10 38 8 36 6 34 4 32 2 Vcc=13V 30 0 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) -50 -25 0 25 50 75 100 Tc (°C) Figure 24. Input Hysteresis Voltage Vhyst (V) 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 -50 -25 0 25 50 75 100 125 150 175 Tc (°C) 13/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 27. PowerSO-10, P2PAK, PENTAWATT Maximum turn off current versus load inductance ILMAX (A) 100 A 10 B C 1 0.1 1 10 100 L(mH ) A = Single Pulse at TJstart=150ºC B= Repetitive pulse at T Jstart=100ºC C= Repetitive Pulse at T Jstart=125ºC Conditions: VCC=13.5V Values are generated with R L=0Ω In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization t 14/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 28. PPAK Maximum turn off current versus load inductance ILMAX (A) 100 A B 10 C 1 0.1 1 10 100 L(mH) A = Single Pulse at TJstart=150ºC B= Repetitive pulse at T Jstart=100ºC C= Repetitive Pulse at T Jstart=125ºC Conditions: VCC=13.5V Values are generated with R L=0Ω In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization t 15/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 29. SO-16L Maximum turn off current versus load inductance ILM AX (A) 100 A B 10 C 1 0.1 1 10 100 L(mH) A = Single Pulse at TJstart=150ºC B= Repetitive pulse at T Jstart=100ºC C= Repetitive Pulse at T Jstart=125ºC Conditions: VCC=13.5V Values are generated with R L=0Ω In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization t 16/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E SO-8 Thermal Data Figure 30. SO-8 PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: 0.14cm2, 0.8cm2, 2cm2). Figure 31. Rthj-amb Vs PCB copper area in open box free air condition RTHj_amb (ºC/W) SO-8 at 2 pins connected to TAB 110 105 100 95 90 85 80 75 70 0 0.5 1 1.5 2 2.5 PCB Cu heatsink area (cm^2) 17/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E SO-16L Thermal Data Figure 32. SO-16L PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 41mm x 48mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: 0.5cm2, 6cm2). Figure 33. SO-16L Rthj-amb Vs PCB copper area in open box free air condition 70 RTH j-amb (°C/W) 65 60 55 50 45 40 0 1 2 3 4 5 PCB Cu heatsink area (cm^2) 18/38 6 7 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E P2PAK Thermal Data Figure 34. P2PAK PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 60mm x 60mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: 0.97cm2, 8cm2). Figure 35. P2PAK Rthj-amb Vs PCB copper area in open box free air condition RTHj_amb (°C/W) 55 Tj-Tamb=50°C 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) 19/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E PPAK Thermal Data Figure 36. PPAK PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 60mm x 60mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: 0.44cm2, 8cm2). Figure 37. Rthj-amb Vs PCB copper area in open box free air condition RTHj_amb (ºC/W) 90 80 70 60 50 40 30 20 10 0 0 2 4 6 PCB Cu heatsink area (cm^2) 20/38 8 10 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E PowerSO-10™ Thermal Data Figure 38. PowerSO-10™ PC Board Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35µm, Copper areas: from minimum pad lay-out to 8cm2). Figure 39. Rthj-amb Vs PCB copper area in open box free air condition RTHj_amb (°C/W) 55 Tj-Tamb=50°C 50 45 40 35 30 0 2 4 6 8 10 PCB Cu heatsink area (cm^2) 21/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 40. PowerSO-10 Thermal Impedance Junction Ambient Single Pulse ZTH (°C/W) 100 0.5 cm2 6 cm2 10 1 0.1 0.01 0.0001 0.001 0.01 0.1 1 10 100 1000 Time (s) Figure 41. Thermal fitting model of a single channel HSD in PowerSO-10 Pulse calculation formula Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ ) where δ = tp ⁄ T Table 14. Thermal Parameter Tj C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd T_amb 22/38 Area/island (cm2) R1 (°C/W) R2 (°C/W) R3( °C/W) R4 (°C/W) R5 (°C/W) R6 (°C/W) C1 (W.s/°C) C2 (W.s/°C) C3 (W.s/°C) C4 (W.s/°C) C5 (W.s/°C) C6 (W.s/°C) 0.5 0.04 0.25 0.25 0.8 12 37 0.0008 7.00E-03 0.015 0.3 0.75 3 6 22 5 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 42. SO-8 Thermal Impedance Junction Ambient Single Pulse ZTH (°C/W) 1000 0.5 cm2 100 2 cm2 10 1 0.1 0.01 0.0001 0.001 0.01 0.1 1 Time (s) Figure 43. Thermal fitting model of a single channel HSD in SO-8 10 100 1000 Pulse calculation formula Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ ) where δ = tp ⁄ T Table 15. Thermal Parameter Tj C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd T_amb R1 R2 R3 R4 R5 R6 C1 C2 C3 C4 C5 C6 Area/island (cm2) (°C/W) (°C/W) ( °C/W) (°C/W) (°C/W) (°C/W) (W.s/°C) (W.s/°C) (W.s/°C) (W.s/°C) (W.s/°C) (W.s/°C) 0.5 0.05 0.8 3.5 21 16 58 0.006 2.60E-03 0.0075 0.045 0.35 1.05 2 28 2 23/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 44. PPAK Thermal Impedance Junction Ambient Single Pulse ZT H (°C/W) 1000 100 0.44 cm2 6 cm2 10 1 0.1 0.01 0.0001 0.001 0.01 0.1 1 Time (s) Figure 45. Thermal fitting model of a single channel HSD in PPAK 10 100 1000 Pulse calculation formula Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ ) where δ = tp ⁄ T Table 16. Thermal Parameter Tj C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd T_amb 24/38 Area/island (cm2) R1 (°C/W) R2 (°C/W) R3( °C/W) R4 (°C/W) R5 (°C/W) R6 (°C/W) C1 (W.s/°C) C2 (W.s/°C) C3 (W.s/°C) C4 (W.s/°C) C5 (W.s/°C) C6 (W.s/°C) 0.44 0.04 0.25 0.3 2 15 61 0.0008 0.007 0.02 0.3 0.45 0.8 6 24 5 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 46. P2PAK Thermal Impedance Junction Ambient Single Pulse ZTH (°C/W) 1000 100 0.97 cm2 6 cm 2 10 1 0.1 0.01 0.0001 0.001 0.01 0.1 1 T ime (s) Figure 47. Thermal fitting model of a single channel HSD in P2PAK 10 100 1000 Pulse calculation formula Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ ) where δ = tp ⁄ T Table 17. Thermal Parameter Tj C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd T_amb Area/island (cm2) R1 (°C/W) R2 (°C/W) R3( °C/W) R4 (°C/W) R5 (°C/W) R6 (°C/W) C1 (W.s/°C) C2 (W.s/°C) C3 (W.s/°C) C4 (W.s/°C) C5 (W.s/°C) C6 (W.s/°C) 0.97 0.04 0.25 0.3 4 9 37 0.0008 0.007 0.015 0.4 2 3 6 22 5 25/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 48. SO-16L Thermal Impedance Junction Ambient Single Pulse ZT H (°C/W) 1000 100 0.5 cm2 6 cm 2 10 1 0.1 0.01 0.0001 0.001 0.01 0.1 1 T ime (s) Figure 49. Thermal fitting model of a single channel HSD in SO-16L 10 100 1000 Pulse calculation formula Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ ) where δ = tp ⁄ T Table 18. Thermal Parameter Tj C1 C2 C3 C4 C5 C6 R1 R2 R3 R4 R5 R6 Pd T_amb 26/38 Area/island (cm2) R1 (°C/W) R2 (°C/W) R3( °C/W) R4 (°C/W) R5 (°C/W) R6 (°C/W) C1 (W.s/°C) C2 (W.s/°C) C3 (W.s/°C) C4 (W.s/°C) C5 (W.s/°C) C6 (W.s/°C) 0.5 0.04 0.25 2.2 12 15 37 0.0008 7.00E-03 1.50E-02 0.14 1 3 6 22 5 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E PACKAGE MECHANICAL Table 19. PowerSO-10™ Mechanical Data millimeters Symbol Min A A (*) A1 B B (*) C C (*) D D1 E E2 E2 (*) E4 E4 (*) e F F (*) H H (*) h L L (*) a α (*) Typ Max 3.35 3.4 0.00 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30 1.27 1.25 1.20 13.80 13.85 1.35 1.40 14.40 14.35 0.50 1.20 0.80 0º 2º 1.80 1.10 8º 8º Note: (*) Muar only POA P013P Figure 50. PowerSO-10™ Package Dimensions B 0.10 A B 10 H E E2 E4 1 SEATING PLANE e B DETAIL "A" h A C 0.25 D = D1 = = = SEATING PLANE A F A1 A1 L DETAIL "A" α P095A 27/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E PACKAGE MECHANICAL Table 20. SO-8 Mechanical Data Symbol millimeters Min Typ A a1 1.75 0.1 0.25 a2 1.65 a3 0.65 0.85 b 0.35 0.48 b1 0.19 0.25 C 0.25 c1 0.5 45 (typ.) D 4.8 5 E 5.8 6.2 e 1.27 e3 3.81 F 3.8 4 L 0.4 1.27 M 0.6 S L1 8 (max.) 0.8 Figure 51. SO-8 Package Dimensions 28/38 Max 1.2 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E PACKAGE MECHANICAL Table 21. PENTAWATT (VERTICAL) Mechanical Data Symbol millimeters Min Typ A 4.8 C D Max 1.37 2.4 2.8 D1 1.2 1.35 E 0.35 0.55 F 0.8 1.05 F1 1 1.4 G 3.2 3.4 3.6 G1 6.6 6.8 7 H2 H3 10.4 10.05 10.4 L 17.85 L1 15.75 L2 21.4 L3 22.5 L5 2.6 3 L6 15.1 15.8 L7 6 6.6 M 4.5 M1 4 Diam. 3.65 3.85 Figure 52. PENTAWATT (VERTICAL) Package Dimensions 29/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E PACKAGE MECHANICAL Table 22. P2PAK Mechanical Data Symbol millimeters Min Typ Max A 4.30 4.80 A1 2.40 2.80 A2 0.03 0.23 b 0.80 1.05 c 0.45 0.60 c2 1.17 1.37 D 8.95 9.35 D2 E 8.00 10.00 E1 10.40 8.50 e 3.20 3.60 e1 6.60 7.00 L 13.70 14.50 L2 1.25 1.40 L3 0.90 1.70 L5 1.55 2.40 R V2 0.40 0º Package Weight 8º 1.40 Gr (typ) Figure 53. P2PAK Package Dimensions P010R 30/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E PACKAGE MECHANICAL Table 23. PPAK Mechanical Data Symbol millimeters Min Typ Max A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 B 0.40 0.60 B2 5.20 5.40 C 0.45 0.60 C2 0.48 0.60 D1 5.1 D 6.00 E 6.40 6.20 6.60 E1 4.7 e 1.27 G 4.90 5.25 G1 2.38 2.70 H 9.35 L2 L4 1.00 0.60 R V2 10.10 0.8 1.00 0.2 0º Package Weight 8º Gr. 0.3 Figure 54. PPAK Package Dimensions P032T1 31/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 55. PowerSO-10™ SUGGESTED PAD LAYOUT and TUBE SHIPMENT (no suffix) CASABLANCA 14.6 - 14.9 MUAR B 10.8 - 11 C 6.30 C A A B 0.67 - 0.73 1 9.5 2 3 4 5 10 9 8 7 0.54 - 0.6 All dimensions are in mm. 1.27 6 Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) Casablanca 50 1000 532 10.4 16.4 0.8 Muar 50 1000 532 4.9 17.2 0.8 Figure 56. PowerSO-10™ TAPE AND REEL SHIPMENT (suffix “TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) 24 4 24 1.5 1.5 11.5 6.5 2 End All dimensions are in mm. Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 32/38 500mm min VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 57. SO-8 TUBE SHIPMENT (no suffix) B Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) C A 100 2000 532 3.2 6 0.6 All dimensions are in mm. Figure 58. SO-8 TAPE AND REEL SHIPMENT (suffix “TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) All dimensions are in mm. 12 4 8 1.5 1.5 5.5 4.5 2 End Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed 33/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 59. PENTAWAT TUBE SHIPMENT (no suffix) B C Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) All dimensions are in mm. A 34/38 50 1000 532 18 33.1 1 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 60. P2PAK TUBE SHIPMENT (no suffix) Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) B C 50 1000 532 18 33.1 1 All dimensions are in mm. A Figure 61. P2PAK TAPE AND REEL SHIPMENT (suffix “TR”) REEL DIMENSIONS Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 1000 330 1.5 13 20.2 24.4 60 30.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) All dimensions are in mm. 24 4 16 1.5 1.5 11.5 6.5 2 End Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. 500mm min User direction of feed 35/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Figure 62. PPAK SUGGESTED PAD LAYOUT and TUBE SHIPMENT (no suffix) A C Base Q.ty Bulk Q.ty Tube length (± 0.5) A B C (± 0.1) B 3 1.8 75 3000 532 6 21.3 0.6 6.7 All dimensions are in mm. Figure 63. PPAK TAPE AND REEL SHIPMENT (suffix “TR”) REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C (± 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 16.4 60 22.4 All dimensions are in mm. TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 (± 0.1) P D (± 0.1/-0) D1 (min) F (± 0.05) K (max) P1 (± 0.1) All dimensions are in mm. 16 4 8 1.5 1.5 7.5 2.75 2 End Start Top No components Components No components cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 36/38 500mm min VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E REVISION HISTORY Table 24. Revision History Date Revision Description of Changes Oct. 2004 1 - First Issue. Dec. 2004 2 - Minor changes. Feb. 2005 3 - Configuration Diagram (PowerSO-10) modification. 37/38 VN820-E / VN820SO-E / VN820SP-E / VN820B5-E / VN820PT-E Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. 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