STMICROELECTRONICS VND5050J-E

VND5050J-E
VND5050K-E
Double channel high side driver with analog current sense
for automotive applications
Features
General
Max supply voltage
VCC
41V
Operating voltage range
VCC
4.5 to 36V
Max On-State resistance (per ch.)
RON
50 mΩ
Current limitation (typ)
ILIMH
19 A
Off state supply current
IS
2 µA(*)
(*) Typical value with all loads connected
Application
■
All types of resistive, inductive and capacitive
loads
Main
■
■
■
■
■
■
Inrush current active management by power
limitation
Very low stand-by current
3.0V CMOS compatible input
Optimized electromagnetic emission
Very low electromagnetic susceptibility
In compliance with the 2002/95/ec european
directive
Diagnostic Functions
■
Open drain status output
On state open load detection
■ Off state open load detection
■ Thermal shutdown indication
■
Protections
■
Undervoltage shut-down
■ Overvoltage clamp
■ Output stuck to VCC detection
■ Load current limitation
PowerSSO-12
PowerSSO-24
■
Self limiting of fast thermal transients
Protection against loss of ground and loss of
VCC
■ Thermal shut down
■
■
Reverse battery protection (see Figure 28)
■
Electrostatic discharge protection
Description
The VND5050K-E and VND5050J-E is a
monolithic device made using STMicroelectronics
VIPower M0-5 technology. It is intended for driving
resistive or inductive loads with one side
connected to ground. Active VCC pin voltage
clamp protects the device against low energy
spikes (see ISO7637 transient compatibility
table). The device detects open load condition
both in on and off state, when STAT_DIS is left
open or driven low. Output shorted to VCC is
detected in the off state.
When STAT_DIS is driven high, STATUS pin is in
high impedance state.
Output current limitation protects the device in
overload condition. In case of long overload
duration, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
Thermal shut-down with automatic restart allows
the device to recover normal operation as soon as
fault condition disappears..
Order codes
March 2006
Package
Part number (Tube)
Part number (Tape & Reel)
PowerSSO-12
VND5050J-E
VND5050J-E13TR
PowerSSO-24
VND5050K-E
VND5050K-E13TR
Rev 1
1/28
www.st.com
28
Contents
VND5050J-E / VND5050K-E
Contents
1
Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
2.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.4
Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
4
5
6
2/28
GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 16
3.1.1
Solution 1: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.2
Solution 2: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3
µC I/Os protection: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
Open load detection in off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1
PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2
PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1
Package Mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.2
Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
VND5050J-E / VND5050K-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1.
Block Diagram
VCC
VCC
CLAMP
GND
UNDERVOLTAGE
INPUT1
CLAMP 1
STATUS1
DRIVER 1
STAT_DIS
OUTPUT1
LOGIC
OVERTEMP. 1
INPUT2
CURRENT LIMITER 1
STATUS2
OPENLOAD ON 1
OPENLOAD OFF 1
CONTROL & PROTECTION
STATUS2 EQUIVALENT TO
CHANNEL1
PWRLIM 1
Table 1.
VCC
INPUT2
OUTPUT2
Pin Function
Name
Function
VCC
Battery connection
OUTPUTn
Power output
GND
Ground connection. Must be reverse battery protected by an external diode/resistor network
INPUTn
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state
STATUSn
Open drain digital diagnostic pin
STAT_DIS
Active high CMOS compatible pin, to disable the STATUS pin
Figure 2.
Configuration diagram (top view) & suggested connections for unused and n.c. pins
TAB = Vcc
GND
STAT_DIS
INPUT 1
STATUS 1
STATUS 2
INPUT 2
12
11
10
9
8
7
1
2
3
4
5
6
Vcc
OUTPUT 1
OUTPUT 1
OUTPUT 2
OUTPUT 2
Vcc
VCC
GND.
N.C.
STAT_DIS
INPUT1
STATUS1
N.C.
STATUS2
N.C.
INPUT2
N.C.
VCC
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT1
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
OUTPUT2
TAB = VCC
PowerSSO-12
Connection / Pin
Floating
To Ground
PowerSSO-24
Status
N.C.
Output
Input
STAT_DIS
X
X
X
X
X
N.R.
X
N.R.
10KΩ resistor
10KΩ resistor
N.R. = Not recommended
3/28
Electrical specifications
2
VND5050J-E / VND5050K-E
Electrical specifications
Figure 3.
Current and Voltage Conventions
IS
VCC
ISD
VCC
IOUTn
STAT_DIS
OUTPUTn
VSD
VOUTn
IINn
ISTATn
INPUTn
STATUSn
VINn
VSTATn
GND
IGND
VFn = VOUTn - VCCn during reverse battery condition
2.1
Absolute Maximum Ratings
Table 2.
Absolute Maximum Ratings
Symbol
VCC
Parameter
Unit
DC Supply Voltage
41
V
- VCC
Reverse DC Supply Voltage
0.3
V
- IGND
DC Reverse Ground Pin Current
200
mA
Internally
Limited
A
15
A
DC Input Current
+10 / -1
mA
DC Status Current
+10 / -1
mA
+10 / -1
mA
51
mJ
4000
4000
4000
5000
5000
V
V
V
V
V
750
V
Junction Operating Temperature
-40 to 150
°C
Storage Temperature
- 55 to 150
°C
IOUT
- IOUT
IIN
ISTAT
DC Output Current
Reverse DC Output Current
ISTAT_DIS DC Status Disable Current
EMAX
Maximum switching energy
(L=1.5mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.) )
VESD
Electrostatic Discharge (Human Body Model: R=1.5KΩ;
C=100pF)
- INPUT
- STATUS
- STAT_DIS
- OUTPUT
- VCC
VESD
Charge device model (CDM-AEC-Q100-011)
Tj
Tstg
4/28
Value
VND5050J-E / VND5050K-E
2.2
Thermal Data
Table 3.
Thermal Data
Electrical specifications
Value
Symbol
Parameter
Unit
Rthj-case
Thermal resistance junction-case (Max.)
(with one channel ON)
Rthj-amb
Thermal resistance junction-ambient (Max.)
2.3
PowerSSO-12
PowerSSO-24
2.8
2.8
°C/W
See Figure 31
See Figure 35
°C/W
Electrical Characteristics
8V<VCC<36V; -40°C<Tj<150°C, unless otherwise specified.
Table 4.
Power section
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
4.5
13
36
V
4.5
V
VCC
Operating supply voltage
VUSD
Undervoltage shutdown
3.5
VUSDhyst
Undervoltage shut-down
hysteresis
0.5
On state resistance(2)
IOUT=2A; Tj=25°C
IOUT=2A; Tj=150°C
IOUT=2A; VCC=5V; Tj=25°C
Vclamp
Clamp Voltage
IS=20mA
IS
Supply current
Off State; VCC=13V; Tj=25°C;
VIN=VOUT=VSENSE=VCSD=0V
On State; VCC=13V; VIN=5V; IOUT=0A
IL(off1)
Off state output current(2)
VIN=VOUT=0V; VCC=13V; Tj=25°C
VIN=VOUT=0V; VCC=13V; Tj=125°C
IL(off2)
current(2)
RON
VF
Off state output
41
VIN=0V; VOUT=4V
(2)
Output - VCC diode voltage
0
0
V
50
100
65
mΩ
mΩ
mΩ
46
52
V
2(1)
3
5(1)
6
µA
mA
0.01
3
5
µA
-75
0
-IOUT=4A; Tj=150°C
0.7
V
Max.
Unit
(1) PowerMOS leakage included.
(2) For each channel
Table 5.
Symbol
Switching (VCC=13V)
Parameter
Test Conditions
Min.
Typ.
td(on)
Turn-on delay time
RL=6.5Ω (see Figure 5)
20
µs
td(off)
Turn-off delay time
RL=6.5Ω (see Figure 5)
40
µs
dVOUT/dt(on) Turn-on voltage slope
RL=6.5Ω
see Figure 22
V/µs
dVOUT/dt(off) Turn-off voltage slope
RL=6.5Ω
see Figure 24
V/µs
5/28
Electrical specifications
Table 5.
Symbol
VND5050J-E / VND5050K-E
Switching (VCC=13V) (continued)
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
WON
Switching energy losses
during twon
RL=6.5Ω (see Figure 5)
0.21
mJ
WOFF
Switching energy losses
during twoff
RL=6.5Ω (see Figure 5)
0.28
mJ
Table 6.
Symbol
Status Pin (VSD=0V)
Parameter
Test Conditions
Min
Typ
Max
Unit
VSTAT
Status Low Output
Voltage
ISTAT= 1.6 mA, VSD=0V
0.5
V
ILSTAT
Status Leakage Current
Normal Operation or VSD=5V,
VSTAT= 5V
10
µA
CSTAT
Status Pin Input
Capacitance
Normal Operation or VSD=5V,
VSTAT= 5V
100
pF
VSCL
Status Clamp Voltage
ISTAT= 1mA
ISTAT= - 1mA
7
V
V
Table 7.
Symbol
Parameter
Test Conditions
DC Short circuit current
VCC=13V
5V<VCC<36V
IlimL
Short circuit current during
thermal cycling
VCC=13V
TR<Tj<TTSD
TTSD
Shutdown temperature
Min.
Typ.
Max.
Unit
12
18
24
24
A
A
7
150
TR
Reset temperature
TRS
Thermal reset of STATUS
THYST
Thermal hysteresis (TTSDTR)
tSDL
Status Delay in Overload
Conditions
Tj>TTSD (see Figure 4)
Turn-off output voltage
clamp
IOUT=2A; VIN=0; L=6mH
Output voltage drop
limitation
IOUT=0.1A; Tj= -40°C...+150°C
(see Figure 6)
VON
-0.7
Protections (1)
IlimH
VDEMAG
5.5
175
A
200
TRS + 1 TRS + 5
°C
°C
135
°C
7
°C
20
µs
VCC-41 VCC-46 VCC-52
V
25
mV
(1) To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals
must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must
limit the duration and number of activation cycles
6/28
VND5050J-E / VND5050K-E
Table 8.
Symbol
Electrical specifications
Openload Detection
Parameter
Test Conditions
IOL
Openload ON State
Detection Threshold
VIN = 5V ,8V<VCC<18V
tDOL(on)
Openload ON State
Detection Delay
IOUT = 0A, VCC=13V (see Figure 4)
tPOL
Delay between INPUT falling
edge and STATUS rising
IOUT = 0A (see Figure 4)
edge in Openload condition
VOL
Openload OFF State Voltage
Detection Threshold
VIN = 0V, 8V<VCC<16V
tDSTKON
Output Short Circuit to VCC
Detection Delay at Turn Off
(see Figure 4)
Table 9.
Symbol
Parameter
Input Low Level
IIL
Low Level Input Current
VIH
Input High Level
IIH
High Level Input Current
VI(hyst)
Input Hysteresis Voltage
Test Conditions
VIN =0.9 V
Max
Unit
10
See
Figure 19
70
mA
200
µs
200
500
1000
µs
2
See
Figure 20
4
V
tPOL
µs
180
Typ.
Max.
Unit
0.9
V
1
µA
2.1
V
10
0.25
IIN = 1mA
IIN = -1mA
Input Clamp Voltage
VSDL
STAT_DIS low level voltage
ISDL
Low level STAT_DIS current
VSDH
STAT_DIS high level voltage
ISDH
High level STAT_DIS current VSD = 2.1 V
VSD = 0.9 V
STAT_DIS hysteresis voltage
STAT_DIS clamp voltage
Min.
VIN = 2.1 V
VICL
VSDCL
Typ
Logic input
VIL
VSD(hyst)
Min
5.5
V
7
V
V
0.9
V
-0.7
1
µA
2.1
V
10
0.25
ISD=1mA
ISD=-1mA
µA
µA
V
5.5
7
-0.7
V
V
7/28
Electrical specifications
Figure 4.
VND5050J-E / VND5050K-E
Status Timings
OPEN LOAD STATUS TIMING (without external pull-up)
IOUT < IOL
VIN
VOUT < VOL
OPEN LOAD STATUS TIMING (with external pull-up)
IOUT < IOL
VIN
VOUT > VOL
VSTAT
VSTAT
tDOL(on)
tDOL(on)
tPOL
OVER TEMP STATUS TIMING
OUTPUT STUCK TO VCC
Tj > TTSD
IOUT > IOL
VIN
VOUT > VOL
VSTAT
VSTAT
tDOL(on)
Table 10.
VIN
tSDL
tDSTKON
tSDL
Truth table
INPUT
OUTPUT
SENSE (VCSD=0V)(1)
Normal Operation
L
H
L
H
H
H
Current Limitation
L
H
L
X
H
H
Overtemperature
L
H
L
L
H
L
Undervoltage
L
H
L
L
X
X
Output Voltage > VOL
L
H
H
H
L(2)
H
Output Current < IOL
L
H
L
H
H (3)
L
CONDITIONS
(1) If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.
(2) The STATUS pin is low with a delay equal to tDSTKON after INPUT falling edge.
(3) The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
8/28
VND5050J-E / VND5050K-E
Figure 5.
Electrical specifications
Switching characteristics
VOUT
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
tr
tf
t
INPUT
td(on)
td(off)
t
Figure 6.
Output Voltage Drop Limitation
Vcc-Vout
Tj=150oC
Tj=25oC
Tj=-40oC
Von
Von/Ron(T)
Iout
9/28
Electrical specifications
Table 11.
VND5050J-E / VND5050K-E
Electrical Transient Requirements
ISO 7637-2:
2004(E)
TEST LEVELS
Test Pulse
III
IV
Number of
pulses or
test times
1
2a
3a
3b
4
5b(1)
-75V
+37V
-100V
+75V
-6V
+40V
-100V
+50V
-150V
+100V
-7V
+40V
5000 pulses
5000 pulses
1h
1h
1 pulse
1 pulse
ISO 7637-2:
2004(E)
Burst cycle/pulse repetition
time
0.5 s
0.2 s
90 ms
90 ms
5s
5s
100 ms
100 ms
Delays and
Impedance
2 ms, 10 Ω
50 µs, 2 Ω
0.1 µs, 50 Ω
0.1 µs, 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
TEST LEVEL RESULTS
Test Pulse
III
IV
1
2a
3a
3b
4
5b(1)
C
C
C
C
C
C
C
C
C
C
C
C
CLASS
CONTENTS
C
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
E
(1) For load dump exceeding the above value a centralized suppressor must be adopted.
10/28
VND5050J-E / VND5050K-E
Figure 7.
Electrical specifications
Waveforms
NORMAL OPERATION
INPUT
STAT_DIS
LOAD CURRENT
STATUS
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
STAT_DIS
LOAD CURRENT
undefined
STATUS
OPEN LOAD with external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
VOL
VOUT>VOL
STATUS
OPEN LOAD without external pull-up
INPUT
STAT_DIS
LOAD VOLTAGE
IOUT<IOL
LOAD CURRENT
tPOL
STATUS
RESISTIVE SHORT TO Vcc, NORMAL LOAD
INPUT
STAT_DIS
IOUT>IOL
LOAD VOLTAGE
VOUT>VOL
VOL
STATUS
tDSTKON
OVERLOAD OPERATION
Tj
TTSD
TR
TRS
INPUT
STAT_DIS
ILIMH
ILIML
LOAD CURRENT
STATUS
current power
limitation limitation
thermal cycling
SHORTED LOAD
NORMAL LOAD
11/28
Electrical specifications
VND5050J-E / VND5050K-E
2.4
Electrical characteristics curves
Figure 8.
Off State Output Current
Figure 9.
Iloff1 (uA)
High Level Input Current
lih (uA)
1
5
4.5
0.875
Off state
Vcc=13V
Vin=Vout=0V
0.75
Vin=2.1V
4
3.5
0.625
3
0.5
2.5
2
0.375
1.5
0.25
1
0.125
0.5
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
100
125
150
175
150
175
Tc (°C)
Figure 10. Input Clamp Voltage
Figure 11. Input High Level
Vih (V)
Vicl (V)
4
8
3.5
7.75
lin=1mA
7.5
3
7.25
2.5
7
2
6.75
1.5
6.5
1
6.25
0.5
6
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Figure 12. Input Low Level
75
Figure 13. Input Hysteresis Voltage
Vil (V)
Vihyst (V)
4
2
3.5
1.75
3
1.5
2.5
1.25
2
1
1.5
0.75
1
0.5
0.5
0.25
0
0
-50
-25
0
25
50
75
Tc (°C)
12/28
50
Tc (°C)
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
100
125
VND5050J-E / VND5050K-E
Electrical specifications
Figure 14. Status Low Output Voltage
Figure 15. On State Resistance Vs Tcase
Vstat (V)
Ron (mOhm)
0.9
100
90
0.8
Istat=1.6mA
Iout=2A
Vcc=13V
80
0.7
70
0.6
60
0.5
50
0.4
40
0.3
30
0.2
20
0.1
10
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 16. Status Leakage Current
Figure 17. On State Resistance Vs VCC
Ilstat (uA)
Ron (mOhm)
0.055
100
90
0.05
Tc= 150°C
80
Vstat=5V
70
0.045
Tc= 125°C
60
0.04
0.035
50
Tc= 25°C
40
Tc= -40°C
30
20
0.03
10
0
0.025
-50
-25
0
25
50
75
100
125
150
0
175
5
10
15
20
25
30
35
40
Vcc (V)
Tc (°C)
Figure 18. Status Clamp Voltage
Figure 19. Openload On State Detection
Threshold
Vscl (V)
Iol (mA)
9
100
8.5
90
Istat=1mA
8
Vin=5V
80
7.5
70
7
60
6.5
50
6
40
5.5
30
5
20
4.5
10
4
0
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
13/28
Electrical specifications
VND5050J-E / VND5050K-E
Figure 20. Openload Off State Voltage
Detection Threshold
Figure 21. ILIM Vs Tcase
Ilimh (A)
Vol (V)
25
5
22.5
4.5
Vcc=13V
Vin=0V
4
20
3.5
17.5
3
15
2.5
12.5
2
10
1.5
7.5
5
1
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
150
175
Tc (°C)
Tc (°C)
Figure 22. Turn-on Voltage Slope
Figure 23. Undervoltage Shutdown
dVout/dt(on) (V/ms)
Vusd (V)
1000
14
900
Vcc=13V
RI=6.5Ohm
800
12
700
10
600
8
500
400
6
300
4
200
2
100
0
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
150
175
Tc (°C)
Figure 24. Turn-off Voltage Slope
Figure 25. STAT_DIS Clamp Voltage
dVout/dt(off) (V/ms)
Vsdcl(V)
1000
14
900
Vcc=13V
RI=6.5Ohm
800
12
Isd=1mA
700
10
600
8
500
400
6
300
4
200
2
100
0
0
-50
-25
0
25
50
75
Tc (°C)
14/28
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
100
125
VND5050J-E / VND5050K-E
Electrical specifications
Figure 26. High Level STAT_DIS Voltage
Figure 27. Low Level STAT_DIS Voltage
Vsdh(V)
Vsdl(V)
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
-50
-25
0
25
50
75
Tc (°C)
100
125
150
175
-50
-25
0
25
50
75
100
125
150
175
Tc (°C)
15/28
Application information
3
VND5050J-E / VND5050K-E
Application information
Figure 28. Application schematic
+5V
+5V
VCC
Rprot
STAT_DIS
Dld
Rprot
INPUT
µC
OUTPUT
Rprot
STATUS
GND
VGND
RGND
DGND
Note: Channel 2 has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
3.1.1
Solution 1:
Resistor in the ground line (RGND only). This can be used with any type of load.
The following is an indication on how to dimension the RGND resistor.
1.
RGND ≤ 600mV / (IS(on)max).
2.
RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power Dissipation in RGND (when VCC<0: during reverse battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that if the microprocessor ground is not shared by the device ground then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.
16/28
VND5050J-E / VND5050K-E
Application information
If the calculated power dissipation leads to a large resistor or several devices have to share
the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2:
A diode (DGND) in the ground line.
A resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives an
inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (≈600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the
VCC max DC rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3
µC I/Os protection:
If a ground protection network is used and negative transient are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 180kΩ.
Recommended values: Rprot =10kΩ, CEXT=10nF.
3.4
Open load detection in off state
Off state open load detection requires an external pull-up resistor (RPU) connected between
OUTPUT pin and a positive supply voltage (VPU) like the +5V line used to supply the
microprocessor.
The external resistor has to be selected according to the following requirements:
1.
no false open load indication when load is connected: in this case we have to avoid
VOUT to be higher than VOlmin; this results in the following condition
VOUT=(VPU/(RL+RPU))RL<VOlmin.
2.
no misdetection when load is disconnected: in this case the VOUT has to be higher than
VOLmax; this results in the following condition RPU<(VPU–VOLmax)/IL(off2).
17/28
Application information
VND5050J-E / VND5050K-E
Because Is(OFF) may significantly increase if Vout is pulled high (up to several mA), the pullup resistor RPU should be connected to a supply that is switched OFF when the module is in
standby.
The values of VOLmin, VOLmax and IL(off2) are available in the Electrical Characteristics
section.
Figure 29. Open Load detection in off state
V batt.
VPU
VCC
RPU
INPUT
DRIVER
+
LOGIC
IL(off2)
OUT
+
STATUS
R
VOL
GROUND
18/28
RL
VND5050J-E / VND5050K-E
Package and PCB thermal data
4
Package and PCB thermal data
4.1
PowerSSO-12 thermal data
Figure 30. PowerSSO-12 PC Board
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,
PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm2).
Figure 31. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(°C/W)
70
65
60
55
50
45
40
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
Figure 32. PowerSSO-12 Thermal Impedance Junction Ambient Single Pulse
ZTH (˚C/W)
1000
Footprint
100
2 cm2
8 cm2
10
1
0.1
0.0001
0.001
0.01
0.1
1
Time (s)
10
100
1000
Pulse Calculation Formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tP/T
19/28
Package and PCB thermal data
VND5050J-E / VND5050K-E
Figure 33. Thermal Fitting Model of a Double Channel HSD in PowerSSO-12
Thermal Parameter
Area/island (cm2)
20/28
Footprint
R1=R7 (°C/W)
0.7
R2=R8 (°C/W)
2.8
2
8
R3 (°C/W)
7
R4 (°C/W)
10
10
9
R5 (°C/W)
22
15
10
R6 (°C/W)
26
20
15
C1=C7 (W.s/°C)
0.001
C2=C8 (W.s/°C)
0.0025
C3 (W.s/°C)
0.05
C4 (W.s/°C)
0.2
0.1
0.1
C5 (W.s/°C)
0.27
0.8
1
C6 (W.s/°C)
3
6
9
VND5050J-E / VND5050K-E
4.2
Package and PCB thermal data
PowerSSO-24 thermal data
Figure 34. PowerSSO-24 PC Board
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,
PCB thickness=1.6mm, Cu thickness=70µm (front and back side), Copper areas: from minimum pad lay-out to 8cm2).
Figure 35. Rthj-amb Vs. PCB copper area in open box free air condition
RTHj_amb(°C/W)
55
50
45
40
35
30
0
2
4
6
8
10
PCB Cu heatsink area (cm^2)
Figure 36. PowerSSO-24 Thermal Impedance Junction Ambient Single Pulse
ZTH (˚C/W)
1000
100
Footprint
2 cm2
8 cm2
10
1
0.1
0.0001
0.001
0.01
0.1
1
Time (s)
10
100
1000
Pulse Calculation Formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tP/T
21/28
Package and PCB thermal data
VND5050J-E / VND5050K-E
Figure 37. Thermal Fitting Model of a Single Channel HSD in PowerSSO-12
Thermal Parameter
Area/island (cm2)
22/28
Footprint
2
8
R1=R7 (°C/W)
0.4
R2=R8 (°C/W)
2
R3 (°C/W)
6
R4 (°C/W)
7.7
R5 (°C/W)
9
9
8
R6 (°C/W)
28
17
10
C1=C7 (W.s/°C)
0.001
C2=C8 (W.s/°C)
0.0022
C3 (W.s/°C)
0.025
C4 (W.s/°C)
0.75
C5 (W.s/°C)
1
4
9
C6 (W.s/°C)
2.2
5
17
VND5050J-E / VND5050K-E
5
Package information
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.1
Package Mechanical
Figure 38. PowerSSO-12™ Package Dimensions
D
0.25 mm
GAUGE PLANE
h x 45˚
C
A2
A
B
ddd
SEATING
PLANE
C
A1
C
12
L
K
7
X
E
H
Y
1
BOTTOM
VIEW
6
e
Table 12.
PowerSSO-12™ Mechanical Data
Symbol
A
A1
A2
B
C
D
E
e
H
h
L
k
X
Y
ddd
millimeters
Min
1.250
0.000
1.100
0.230
0.190
4.800
3.800
Typ
Max
1.620
0.100
1.650
0.410
0.250
5.000
4.000
0.800
5.800
0.250
0.400
0°
1.900
3.600
6.200
0.500
1.270
8°
2.500
4.200
0.100
23/28
Package information
VND5050J-E / VND5050K-E
Figure 39. PowerSSO-24™ Package Dimensions
PowerSSO-24™ Mechanical Data
Table 13.
Symbol
millimeters
Min
Max
A
2.15
2.47
A2
2.15
2.40
a1
0
0.075
b
0.33
0.51
c
0.23
0.32
D
10.10
10.50
E
7.4
7.6
e
0.8
e3
8.8
G
0.1
G1
0.06
H
10.1
h
L
10.5
0.4
0.55
N
24/28
Typ
0.85
10deg
X
4.1
4.7
Y
6.5
7.1
VND5050J-E / VND5050K-E
5.2
Package information
Packing information
Figure 40. PowerSSO-12 Tube Shipment (No Suffix)
B
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
C
A
100
2000
532
1.85
6.75
0.6
All dimensions are in mm.
Figure 41. PowerSSO-12 Tape And Reel Shipment (Suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
2500
2500
330
1.5
13
20.2
12.4
60
18.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
All dimensions are in mm.
W
P0 (± 0.1)
P
D (± 0.05)
D1 (min)
F (± 0.1)
K (max)
P1 (± 0.1)
12
4
8
1.5
1.5
5.5
4.5
2
End
Start
Top
cover
tape
No components
Components
No components
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
25/28
Package information
VND5050J-E / VND5050K-E
Figure 42. PowerSSO-24 Tube Shipment (No Suffix)
C
Base Q.ty
Bulk Q.ty
Tube length (± 0.5)
A
B
C (± 0.1)
B
49
1225
532
3.5
13.8
0.6
All dimensions are in mm.
A
Figure 43. PowerSSO-24 Tape And Reel Shipment (Suffix “TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
1000
1000
330
1.5
13
20.2
24.4
100
30.4
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
W
Tape Hole Spacing
P0 (± 0.1)
Component Spacing
P
Hole Diameter
D (± 0.05)
Hole Diameter
D1 (min)
Hole Position
F (± 0.1)
Compartment Depth K (max)
Hole Spacing
P1 (± 0.1)
All dimensions are in mm.
24
4
12
1.55
1.5
11.5
2.85
2
End
Start
Top
cover
tape
No components
Components
Empty components pockets
saled with cover tape.
User direction of feed
26/28
No components
500mm min
500mm min
VND5050J-E / VND5050K-E
6
Revision history
Revision history
Table 14.
Document revision history
Date
Revision
30-Mar-2006
1
Changes
Initial release.
27/28
VND5050J-E / VND5050K-E
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZE REPRESENTATIVE OF ST, ST PRODUCTS ARE NOT DESIGNED,
AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS,
NOR IN PRODUCTS OR SYSTEMS, WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR
SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2006 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
28/28