STMICROELECTRONICS VN920DSP13TR

VN920DSP
HIGH SIDE DRIVER
Table 1. General Features
Type
VN920DSP
Figure 1. Package
RDS(on)
Iout
VCC
16 mΩ
25 A
36 V
CMOS COMPATIBLE INPUT
ON STATE OPEN LOAD DETECTION
■ OFF STATE OPEN LOAD DETECTION
■ SHORTED LOAD PROTECTION
■ UNDERVOLTAGE AND OVERVOLTAGE
SHUTDOWN
■ PROTECTION AGAINST LOSS OF GROUND
■ VERY LOW STAND-BY CURRENT
■
■
■
10
1
PowerSO-10
REVERSE BATTERY PROTECTION (*)
DESCRIPTION
The VN920DSP is a monolithic device made by
using
STMicroelectronics
VIPower
M0-3
Technology, intended for driving any kind of load
with one side connected to ground.
Active V CC pin voltage clamp protects the device
against low energy spikes (see ISO7637 transient
compatibility table).
Active current limitation combined with thermal
shutdown and automatic restart protect the device
against overload.
The device detects open load condition both is on
and off state. Output shorted to VCC is detected in
the off state. Device automatically turns off in case
of ground pin disconnection.
Table 2. Order Codes
Package
PowerSO-10™
Tube
VN920DSP
Tape and Reel
VN920DSP13TR
Note: (*) See application schematic at page 9
Rev. 2
October 2004
1/19
VN920DSP
Figure 2. Block Diagram
VCC
OVERVOLTAGE
DETECTION
VCC
CLAMP
UNDERVOLTAGE
DETECTION
GND
Power CLAMP
DRIVER
INPUT
OUTPUT
LOGIC
CURRENT LIMITER
ON STATE OPENLOAD
DETECTION
STATUS
OVERTEMPERATURE
DETECTION
OFF STATE OPENLOAD
AND OUTPUT SHORTED TO VCC
DETECTION
Table 3. Absolute Maximum Ratings
Symbol
VCC
- VCC
- IGND
IOUT
- IOUT
IIN
ISTAT
VESD
EMAX
Ptot
Tj
Tc
Tstg
2/19
Parameter
DC Supply Voltage
Reverse DC Supply Voltage
DC Reverse Ground Pin Current
DC Output Current
Reverse DC Output Current
DC Input Current
DC Status Current
Electrostatic Discharge (Human Body Model: R=1.5KΩ; C=100pF)
Value
41
- 0.3
- 200
Internally Limited
- 25
+/- 10
+/- 10
Unit
V
V
mA
A
A
mA
mA
- INPUT
4000
V
- CURRENT SENSE
4000
V
- OUTPUT
5000
V
- VCC
Maximum Switching Energy
5000
V
362
mJ
96.1
Internally Limited
- 40 to 150
- 55 to 150
W
°C
°C
°C
(L=0.25mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=45A)
Power Dissipation TC=25°C
Junction Operating Temperature
Case Operating Temperature
Storage Temperature
VN920DSP
Figure 3. Configuration Diagram (Top View) & Suggested Connections for Unused and N.C. Pins
GROUND
INPUT
6
5
OUTPUT
7
4
OUTPUT
STATUS
8
3
N.C.
N.C.
N.C.
9
2
OUTPUT
10
1
OUTPUT
11
VCC
Connection / Pin
Status
N.C.
Output
X
X
X
Floating
To Ground
Input
X
X
Through 10KΩ resistor
Figure 4. Current and Voltage Conventions
IS
VCC
VF
VCC
IOUT
OUTPUT
IIN
VOUT
INPUT
VIN
ISENSE
CURRENT SENSE
VSENSE
GND
IGND
Table 4. Thermal Data
Symbol
Rthj-case
Rthj-amb
Parameter
Thermal Resistance Junction-case
Thermal Resistance Junction-ambient
Max
Max
Value
1.3
51.3 (1)
37 (2)
Unit
°C/W
°C/W
Note: (1) When mounted on a standard single-sided FR-4 board with 0.5cm 2 of Cu (at least 35µm thick).
Note: (2) When mounted on a standard single-sided FR-4 board with 6 cm 2 of Cu (at least 35µm thick).
3/19
VN920DSP
ELECTRICAL CHARACTERISTICS
(8V<VCC<36V; -40°C<Tj<150°C unless otherwise specified)
Table 5. Power
Symbol
VCC
VUSD
VUSDhyst
VOV
RON
IS
Parameter
Operating Supply Voltage
Undervoltage Shut-down
Undervoltage Shut-down
hysteresis
Overvoltage Shut-down
On State Resistance
Supply Current
Test Conditions
Min
5.5
3
Typ
13
4
0.5
Off
Off
Off
Off
State
State
State
State
Output Current
Output Current
Output Current
Output Current
Unit
V
V
V
IOUT=10A; Tj=25°C
36
16
V
mΩ
IOUT=10A
30
mΩ
IOUT=3A; VCC=6V
mΩ
µA
Off State; VCC=13V; VIN=VOUT=0V
10
50
25
Off State; VCC=13V; VIN=VOUT=0V;
Tj=25°C
10
20
µA
5
50
0
5
3
mA
µA
µA
µA
µA
Typ
50
50
See
relative
diagram
See
relative
diagram
Max
Unit
µs
µs
Typ
Max
1.25
On State; VCC=13V; VIN=5V; IOUT=0A
IL(off1)
IL(off2)
IL(off3)
IL(off4)
Max
36
5.5
VIN=VOUT=0V
VIN=0V; VOUT =3.5V
VIN=VOUT=0V; VCC=13V; Tj =125°C
VIN=VOUT=0V; VCC=13V; Tj =25°C
0
-75
Table 6. Switching (V CC=13V)
Symbol
td(on)
td(off)
Parameter
Turn-on Delay Time
Turn-off Delay Time
RL=1.3Ω
RL=1.3Ω
Test Conditions
dVOUT/
dt(on)
Turn-on Voltage Slope
RL=1.3Ω
dVOUT/
dt(off)
Turn-off Voltage Slope
RL=1.3Ω
Min
V/µs
V/µs
Table 7. Input Pin
Symbol
VIL
IIL
VIH
IIH
VI(hyst)
VICL
4/19
Parameter
Input Low Level
Low Level Input Current
Input High Level
High Level Input Current
Input Hysteresis Voltage
Input Clamp Voltage
Test Conditions
VIN=1.25V
Min
1
3.25
VIN=3.25V
IIN=1mA
IIN=-1mA
10
0.5
6
6.8
-0.7
8
Unit
V
µA
V
µA
V
V
V
VN920DSP
ELECTRICAL CHARACTERISTICS (continued)
Table 8. VCC - Output Diode
Symbol
VF
Parameter
Forward on Voltage
Test Conditions
-IOUT=5A; Tj=150°C
Min
Typ
Max
0.6
Unit
V
Parameter
Test Conditions
Status Low Output Voltage ISTAT =1.6mA
Status Leakage Current
Normal Operation VSTAT=5V
Status Pin Input
Normal Operation VSTAT=5V
Capacitance
ISTAT =1mA
Status Clamp Voltage
ISTAT =-1mA
Min
Typ
Max
0.5
10
Unit
V
µA
100
pF
Table 9. Status Pin
Symbol
VSTAT
ILSTAT
CSTAT
VSCL
6
6.8
8
-0.7
V
V
Table 10. Protections (see note 1)
Symbol
TTSD
TR
Thyst
tSDL
Ilim
Vdemag
Parameter
Shut-down Temperature
Reset Temperature
Thermal Hysteresis
Status delay in overload
condition
Current limitation
Turn-off Output Clamp
Voltage
Test Conditions
Min
150
135
7
Typ
175
45
5.5V<VCC<36V
IOUT=2A; VIN=0V; L=6mH
Unit
°C
°C
°C
20
µs
75
A
75
A
15
Tj>TTSD
30
Max
200
VCC-41 VCC-48 VCC-55
V
Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be
used together with a proper software strategy. If the device operates under abnormal conditions this software must limit the duration
and number of activation cycles.
Table 11. Openload Detection
Symbol
IOL
tDOL(on)
VOL
tDOL(off)
Parameter
Openload ON State
Detection Threshold
Openload ON State
Detection Delay
Openload OFF State
Voltage Detection
Threshold
Openload Detection Delay
at Turn Off
Test Conditions
VIN=5V
Min
Typ
Max
Unit
300
500
700
mA
200
µs
3.5
V
1000
µs
IOUT =0A
VIN=0V
1.5
2.5
5/19
VN920DSP
Figure 5.
OPEN LOAD STATUS TIMING (with external pull-up)
VOUT > VOL
OVERTEMP STATUS TIMING
IOUT< IOL
Tj > TTSD
VIN
VIN
VSTAT
VSTAT
tDOL(off)
tDOL(on)
tSDL
tSDL
Figure 6. Switching time Waveforms
VOUT
90%
80%
dVOUT/dt(off)
dVOUT/dt(on)
10%
t
VIN
td(on)
td(off)
t
6/19
VN920DSP
Table 12. Truth Table
CONDITIONS
INPUT
L
H
L
H
H
L
H
L
H
L
H
L
H
L
H
Normal Operation
Current Limitation
Overtemperature
Undervoltage
Overvoltage
Output Voltage > VOL
Output Current < IOL
OUTPUT
L
H
L
X
X
L
L
L
L
L
L
H
H
L
H
STATUS
H
H
H
(Tj < TTSD) H
(Tj > TTSD) L
H
L
X
X
H
H
L
H
H
L
Table 13. Electrical Transient Requirements On V CC Pin
ISO T/R 7637/1
Test Pulse
I
II
TEST LEVELS
III
IV
1
2
3a
3b
4
5
-25 V
+25 V
-25 V
+25 V
-4 V
+26.5 V
-50 V
+50 V
-50 V
+50 V
-5 V
+46.5 V
-75 V
+75 V
-100 V
+75 V
-6 V
+66.5 V
-100 V
+100 V
-150 V
+100 V
-7 V
+86.5 V
ISO T/R 7637/1
Test Pulse
1
2
3a
3b
4
5
CLASS
C
E
I
C
C
C
C
C
C
TEST LEVELS RESULTS
II
III
C
C
C
C
C
C
C
C
C
C
E
E
Delays and
Impedance
2 ms 10 Ω
0.2 ms 10 Ω
0.1 µs 50 Ω
0.1 µs 50 Ω
100 ms, 0.01 Ω
400 ms, 2 Ω
IV
C
C
C
C
C
E
CONTENTS
All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device is not performed as designed after exposure to disturbance
and cannot be returned to proper operation without replacing the device.
7/19
VN920DSP
Figure 7. Waveforms
NORMAL OPERATION
INPUT
LOAD VOLTAGE
STATUS
UNDERVOLTAGE
VUSDhyst
VCC
VUSD
INPUT
LOAD VOLTAGE
STATUS
undefined
OVERVOLTAGE
VCC<VOV
VCC>VOV
VCC
INPUT
LOAD VOLTAGE
STATUS
OPEN LOAD with external pull-up
INPUT
VOUT >VOL
LOAD VOLTAGE
VOL
STATUS
OPEN LOAD without external pull-up
INPUT
LOAD VOLTAGE
STATUS
Tj
INPUT
LOAD CURRENT
STATUS
8/19
TTSD
TR
OVERTEMPERATURE
VN920DSP
Figure 8. Application Schematic
+5V
+5V
VCC
Rprot
STATUS
Dld
µC
Rprot
INPUT
OUTPUT
GND
RGND
VGND
GND PROTECTION
REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This
can be used with any type of load.
The following is an indication on how to dimension the
RGND resistor.
1) RGND ≤ 600mV / (IS(on)max).
2) RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can
be found in the absolute maximum rating section of the
device’s datasheet.
Power Dissipation in RGND (when VCC<0: during reverse
battery situations) is:
PD= (-VCC)2/RGND
This resistor can be shared amongst several different
HSD. Please note that the value of this resistor should be
calculated with formula (1) where IS(on)max becomes the
sum of the maximum on-state currents of the different
devices.
Please note that if the microprocessor ground is not
common with the device ground then the RGND will
produce a shift (IS(on)max * RGND) in the input thresholds
and the status output values. This shift will vary
depending on many devices are ON in the case of several
high side drivers sharing the same RGND.
If the calculated power dissipation leads to a large
resistor or several devices have to share the same
resistor then the ST suggests to utilize Solution 2 (see
below).
Solution 2: A diode (DGND) in the ground line.
A resistor (RGND=1kΩ) should be inserted in parallel to
DGND if the device will be driving an inductive load.
DGND
This small signal diode can be safely shared amongst
several different HSD. Also in this case, the presence of
the ground network will produce a shift (j600mV) in the
input threshold and the status output values if the
microprocessor ground is not common with the device
ground. This shift will not vary if more than one HSD
shares the same diode/resistor network.
Series resistor in INPUT line is also required to prevent
that, during battery voltage transient, the current exceeds
the Absolute Maximum Rating.
Safest configuration for unused INPUT pin is to leave it
unconnected, while unused SENSE pin has to be
connected to Ground pin.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the
load dump peak voltage exceeds VCC max DC rating.
The same applies if the device will be subject to
transients on the VCC line that are greater than the ones
shown in the ISO T/R 7637/1 table.
µC I/Os PROTECTION:
If a ground protection network is used and negative
transient are present on the VCC line, the control pins will
be pulled negative. ST suggests to insert a resistor (Rprot)
in line to prevent the µC I/Os pins to latch-up.
The value of these resistors is a compromise between the
leakage current of µC and the current required by the
HSD I/Os (Input levels compatibility) with the latch-up
limit of µC I/Os.
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax
Calculation example:
For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V
5kΩ ≤ Rprot ≤ 65kΩ.
Recommended Rprot value is 10kΩ.
9/19
VN920DSP
Figure 9. Off State Output Current
Figure 10. High Level Input Current
IL(off1) (uA)
Iih (uA)
9
5
8
4.5
Vin=3.25V
4
7
3.5
6
3
5
2.5
4
2
3
1.5
2
1
1
0.5
0
0
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
Tc (°C)
75
100
125
150
175
100
125
150
175
150
175
Tc (°C)
Figure 11. Input Low Level
Figure 13. Input High Level
Vil (V)
Vih (V)
2.6
3.6
2.4
3.4
2.2
3.2
2
3
1.8
2.8
1.6
2.6
1.4
2.4
1.2
2.2
1
2
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
Tc (°C)
Figure 12. Input Clamp Voltage
Figure 14. Input Hysteresis Voltage
Vhyst (V)
Vicl (V)
1.5
8
1.4
7.8
Iin=1mA
7.6
1.3
7.4
1.2
7.2
1.1
7
1
6.8
0.9
6.6
0.8
6.4
0.7
6.2
0.6
0.5
6
-50
-25
0
25
50
75
Tc (°C)
10/19
50
100
125
150
175
-50
-25
0
25
50
75
Tc (°C)
100
125
VN920DSP
Figure 15. Overvoltage Shutdown
Figure 18. ILIM Vs Tcase
Vov (V)
Ilim (A)
50
100
48
90
46
80
44
70
42
60
40
50
38
40
36
30
34
20
32
10
Vcc=13V
30
0
-50
-25
0
25
50
75
100
125
150
175
-50
-25
0
25
Tc (°C)
50
75
100
125
150
175
150
175
Tc (°C)
Figure 16. Turn-on Voltage Slope
Figure 19. Turn-off Voltage Slope
dVout/dt(on) (V/ms)
dVout/dt(off) (V/ms)
700
550
500
650
Vcc=13V
Rl=1.3Ohm
450
Vcc=13V
Rl=1.3Ohm
600
400
550
350
500
300
450
250
200
400
150
350
100
300
50
0
250
-50
-25
0
25
50
75
100
125
150
-50
175
-25
0
25
50
75
100
125
Tc (°C)
Tc (ºC)
Figure 17. On State Resistance Vs Tcase
Figure 20. On State Resistance Vs VCC
Ron (mOhm)
Ron (mOhm)
50
50
45
45
Iout=10A
Vcc=8V; 36V
40
40
35
35
30
30
25
25
20
20
15
15
10
10
5
5
Tc= 150ºC
Tc= 25ºC
Tc= - 40ºC
0
0
-50
-25
0
25
50
75
Tc (ºC)
100
125
150
175
5
10
15
20
25
30
35
40
Vcc (V)
11/19
VN920DSP
Figure 21. Status Leakage Current
Figure 23. Status Low Output Voltage
Vstat (V)
Ilstat(µA)
0.8
0.05
0.045
0.7
Vstat=5V
Istat=1.6mA
0.04
0.6
0.035
0.5
0.03
0.4
0.025
0.02
0.3
0.015
0.2
0.01
0.1
0.005
0
0
-50
-25
0
25
50
75
100
125
150
175
Figure 22. Status Clamp Voltage
Vscl (V)
8
7.8
Istat=1mA
7.6
7.4
7.2
7
6.8
6.6
6.4
6.2
6
-50
-25
0
25
50
75
Tc (ºC)
12/19
-50
-25
0
25
50
75
Tc (ºC)
Tc (ºC)
100
125
150
175
100
125
150
175
VN920DSP
Figure 24. Maximum turn off current versus load inductance
ILM AX (A)
100
A
B
C
10
1
0.1
1
10
100
L(m H )
A = Single Pulse at TJstart=150ºC
B= Repetitive pulse at T Jstart=100ºC
C= Repetitive Pulse at T Jstart=125ºC
Conditions:
VCC=13.5V
Values are generated with R L=0Ω
In case of repetitive pulses, Tjstart (at beginning of
each demagnetization) of every pulse must not
exceed the temperature specified above for
curves B and C.
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
13/19
VN920DSP
PowerSO-10™ Thermal Data
Figure 25. PowerSO-10™ PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,
Cu thickness=35µm, Copper areas: from minimum pad lay-out to 8cm2).
Figure 26. Rthj-amb Vs PCB copper area in open box free air condition
RTHj_amb (°C/W)
55
Tj-Tamb=50°C
50
45
40
35
30
0
2
4
6
PCB Cu heatsink area (cm^2)
14/19
8
10
VN920DSP
Figure 27. PowerSO-10 Thermal Impedance Junction Ambient Single Pulse
ZTH (°C/W)
100
Footprint
6 cm 2
10
1
0.1
0.01
0.0001
0.001
0.01
0.1
1
10
100
1000
Time (s)
Figure 28. Thermal fitting model of a double
channel HSD in PowerSO-10
Pulse calculation formula
Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where
δ = tp ⁄ T
Table 14. Thermal Parameter
Tj
C1
C2
C3
C4
C5
C6
R1
R2
R3
R4
R5
R6
Pd
T_amb
Area/island (cm2)
R1 (°C/W)
R2 (°C/W)
R3( °C/W)
R4 (°C/W)
R5 (°C/W)
R6 (°C/W)
C1 (W.s/°C)
C2 (W.s/°C)
C3 (W.s/°C)
C4 (W.s/°C)
C5 (W.s/°C)
C6 (W.s/°C)
Footprint
0.02
0.1
0.2
0.8
12
37
0.0015
7.00E-03
0.015
0.3
0.75
3
6
22
5
15/19
VN920DSP
PACKAGE MECHANICAL
Table 15. PowerSO-10™ Mechanical Data
millimeters
Symbol
Min
A
A (*)
A1
B
B (*)
C
C (*)
D
D1
E
E2
E2 (*)
E4
E4 (*)
e
F
F (*)
H
H (*)
h
L
L (*)
a
α (*)
Typ
Max
3.35
3.4
0.00
0.40
0.37
0.35
0.23
9.40
7.40
9.30
7.20
7.30
5.90
5.90
3.65
3.6
0.10
0.60
0.53
0.55
0.32
9.60
7.60
9.50
7.60
7.50
6.10
6.30
1.27
1.25
1.20
13.80
13.85
1.35
1.40
14.40
14.35
0.50
1.20
0.80
0º
2º
1.80
1.10
8º
8º
Note: (*) Muar only POA P013P
Figure 29. PowerSO-10™ Package Dimensions
B
0.10 A B
10
H
E
E2
E4
1
SEATING
PLANE
e
B
DETAIL "A"
h
A
C
0.25
D
= D1 =
=
=
SEATING
PLANE
A
F
A1
A1
L
DETAIL "A"
α
16/19
P095A
VN920DSP
Figure 30. PowerSO-10™ Suggested Pad Layout And Tube Shipment (no suffix)
CASABLANCA
14.6 - 14.9
MUAR
B
10.8 - 11
C
6.30
C
A
A
B
0.67 - 0.73
1
9.5
2
3
4
5
10
9
8
7
6
0.54 - 0.6
All dimensions are in mm.
1.27
Base Q.ty Bulk Q.ty Tube length (± 0.5)
A
B
C (± 0.1)
Casablanca
50
1000
532
10.4 16.4
0.8
Muar
50
1000
532
4.9 17.2
0.8
Figure 31. Tape And Reel Shipment (suffix “13TR”)
REEL DIMENSIONS
Base Q.ty
Bulk Q.ty
A (max)
B (min)
C (± 0.2)
F
G (+ 2 / -0)
N (min)
T (max)
600
600
330
1.5
13
20.2
24.4
60
30.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width
Tape Hole Spacing
Component Spacing
Hole Diameter
Hole Diameter
Hole Position
Compartment Depth
Hole Spacing
W
P0 (± 0.1)
P
D (± 0.1/-0)
D1 (min)
F (± 0.05)
K (max)
P1 (± 0.1)
24
4
24
1.5
1.5
11.5
6.5
2
End
All dimensions are in mm.
Start
Top
No components
Components
No components
cover
tape
500mm min
Empty components pockets
saled with cover tape.
500mm min
User direction of feed
17/19
VN920DSP
REVISION HISTORY
Date
Sep. 2004
Oct. 2004
18/19
Revision
1
- First Issue.
2
- Minor text change.
Description of Changes
VN920DSP
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
© 2004 STMicroelectronics - All rights reserved
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19/19