UNISONIC TECHNOLOGIES CO., LTD M4334 CMOS IC STEREO AUDIO D/A CONVERTER 24BITS,96KHZ SAMPLING DESCRIPTION The UTC M4334 is a complete low cost stereo audio digital to analog converter(DAC), its contains interpolation, 1-bit D/A conversion and analog output filtering. The M4334 is based on a 4th order Δ-Σ modulation, where the modulator output controls the reference voltage input to an ultra-liner analog low-pass filter. This architecture allows for infinite adjustment of sample rate between 2 kHz and 100 kHz simply by changing the master clock frequency. The M4334 also contains digital de-emphasis function, operates from a single +5V power supply, for best performance, decoupling capacitors should be located as close to the device package as possible with the smallest capacitor closest, the M4334 requires minimal support circuitry. The M4334 is ideal for DVD players, set-top boxes, SVCD players and A/V receivers. SOP-8 FEATURES * Complete stereo DAC: Includes Output Analog Filter and DAC * Dynamic Range: 96dB * THD+N: -88dB * Multiple Sampling Frequencies: 16kHz to 96kHz * Low Clock Jitter Sensitivity * Single Power Supply: 5V * Filtered Line Level Outputs * On-Chip Digital De-emphasis * Normal or I2S Data Input Formats * 24Bits Conversion ORDERING INFORMATION Ordering Number M4334G-S08-R Package SOP-8 www.unisonic.com.tw Copyright © 2010 Unisonic Technologies Co., Ltd Packing Tape Reel 1 of 9 QW-R502-441A M4334 CMOS IC PIN CONFIGURATIONS PIN DESCRIPTION PIN NO PIN NAME PIN TYPE 1 SDATA I 2 DEM/SCLK I 3 LRCK I 4 MCLK I 5 6 7 8 AOUTR AGND VA AOUTL O I I O PIN DESCRIPTION Serial audio data input: two’s complement MSB-first serial data is input on this pin. The data is clocked into the M4334 via internal or external SCLK, and the channel is determined by LRCK. De-emphasis control and clock input for audio data: used for de-emphasis filter control or external serial clock input. Sample rata clock input: determines which channel is currently being input on the audio serial data input pin. System clock input: frequency must be 256x, 384x, or 512x the input sample rate in BRM and either 128x or 192x the input sample rate in HRM. Right-channel analog output Ground pin Power supply pin for the internal control circuits Left-channel analog output UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 2 of 9 QW-R502-441A M4334 CMOS IC BLOCK DIAGRAM UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 3 of 9 QW-R502-441A M4334 CMOS IC ABSOLUTE MAXIMUM RATING PARAMETER SYMBOL RATINGS UNIT DC Power Supply VA -0.3~6 V Digital Input Voltage VIND -0.3~ VA +0.4 V Input Current, Any Pin Except Supplies IIN ±10 mA Ambient Operating Temperature TA -55 ~ +125 °C Storage Temperature TSTG -65 ~ +150 °C Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. RECOMMENDED OPERATING CONDITIONS(Note1) PARAMETER SYMBOL RANGE DC Power Supply VA 4.75 ~ 5.5 Note: 1. All voltage values are with respect to the network ground terminal unless otherwise noted. 2. The VOUT tracks the VREF with additional voltage offset and load regulation. UNIT V ELECTRICAL CHARACTERISTICS All specifications at 25°C,VA=+5V, full-scale output sine wave,997Hz; MCLK=12.288MHz; Fs for =48kHz, SCLK=3.072MHz, measurement bandwidth 10Hz to 20kHz, unless otherwise specified; fS for HRM=96kHz, SCLK=6.144MHz, measurement bandwidth 10Hz to 40kHz, unless otherwise specified. RL=10KΩ, CL=10pF. PARAMETER POWER AND THERMAL SYMBOL Power supply current IA Power Dissipation PD Package Thermal Resistance Power Supply Rejection Ratio DC ACCURACY Inter Channel Gain Mismatch Gain Error Gain Drift ANALOG OUTPUT Full Scale Output Voltage Quiescent Voltage Max AC-Load Resistance Max Load Capacitance DIGITAL INPUT/OUTPUT High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance θJA PSRR TEST CONDITIONS MIN Normal operation Power-down state Normal operation Power-down state f=1kHz 3.25 VQ RL CL VIH VIL II(Leak) CIN UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw TYP MAX UNIT 15 40 75 0.2 110 79 19 mA uA 104 mW °C /W dB 0.1 ±5 100 0.4 dB % ppm/°C 3.5 2.2 3 100 3.75 Vpp VDC KΩ pF 2.0 0.8 ±10 8 V V μA pF 4 of 9 QW-R502-441A M4334 CMOS IC ELECTRICAL CHARACTERISTICS (Cont.) PARAMETER SYMBOL Ambient Operating Temperature TOPR Dynamic Range Total Harmonic Distortion +Noise THD+N Base-Rate Mode TEST CONDITIONS MIN TYP MAX -40 85 16-bit , 83 91 un-weighted 16-bit , 86 94 a-weighted 18 to 24-bit, un-weighted 85 93 18 to 24-bit , a-weighted 88 96 High-Rate Mode MIN TYP MAX -40 85 UNIT °C 88 86 94 dB 90 88 96 16-bit, 0dB -86 -70 -86 -80 16-bit, -20dB -71 -63 -68 -60 16-bit, -60dB -31 -23 -28 -20 18 to 24-bit, 0dB -88 -82 -88 -82 18 to 24-bit, -20dB -73 -65 -70 -62 18 to 24-bit, -60dB -33 -25 -30 -22 dB SWITCHING CHARCTERISTICS (TA=-40 to 85°C;VA=4.75V~5.5V; Input: Logic 0=0V, Logic 1=VA, CL=20pF) PARAMETER Input Sample Rate MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width High MCLK Pulse Width Low MCLK Pulse Width High MCLK Pulse Width Low EXTERNAL SCLK MODE LRCK Duty Cycle SCLK Pulse Width High SCLK Pulse Width Low SYMBOL fS TEST CONDITIONS MCLK/LRCK=512 MCLK/LRCK=512 MCLK/LRCK=384 or 192 MCLK/LRCK=384 or 192 MCLK/LRCK=256 or 128 MCLK/LRCK=256 or 128 tSCLKH tSCLKL MIN 2 10 10 21 21 31 31 TYP 40 20 20 50 MAX UNIT 100 kHz 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns 60 % ns ns MCLK/LRCK=512,256 or 384 1 (128) Fs ns MCLK/LRCK=128 or 192 1 (64) Fs ns tSLRD tSLRS tSDLRS tSDH 20 20 20 20 ns ns ns ns SCLK Period tSCLKW 1 SCLK SCLK rising to LRCK edge tSCLKR SCLK Period SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time INTERNAL SCLK MODE LRCK duty cycle SDATA valid to SCLK rising setup time SCLK rising to SDATA hold time SCLK rising to SDATA hold time tSCLKW 50 ns tsclkw 2 μs tSDLRS 1 + 10 (512) Fs ns tSDH MCLK/LRCK=128 , 256 or 512 1 +15 (512) Fs ns MCLK/LRCK=192 or 384 1 + 15 (384) Fs ns tSDH UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw % 5 of 9 QW-R502-441A M4334 CMOS IC TIMING DIAGRAMS Inernal SCLK Mode External SCLK Mode I2S, 16-Bit data and internal SCLK=32fs 2 I S, up to 24-Bit data if MCLK/LRCK=128, 256 or 512 2 Data valid on rising edge of SCLK I S, up to 24-Bit data and internal SCLK=48fs if MCLK/LRCK=192 or 384 Figure 1. I2S Data Input Timing UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 6 of 9 QW-R502-441A M4334 CMOS IC TYPICAL APPLICATION CIRCUIT UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 7 of 9 QW-R502-441A M4334 CMOS IC APPLICATION CONSIDERATION The M4334 is a complete low cost stereo digital-to-analog output system contains digital interpolation, fourth-order delta-sigma digital-to-analog conversion, digital de-emphasis and analog low pass filter. The M4334 used the Δ-Σ modulation techniques is to avoid the limitations of resistive laser trimmed DAC architectures by using an inherently linear 1-bit DAC. The M4334 supports two modes of operation. The devices operate in Base Rate Mode (BRM) when MCLK/LRCK is 256, 384 or 512 and in High Rate Mode (HRM) when MCLK/LRCK is 128 or 192. HRM allows input sample rates up to 100 kHz. The M4334 also has the de-emphasis function, the de-emphasis filter is active when the DEM/SCLK pin is low for 5 consecutive falling edges of LRCK, but this function is available only in the internal SCLK mode. When the M4334 is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to AGND. After a sh- ort delay of approximately 1000 sample periods, each output begins to ramp towards its quiescent voltage, VQ. App- roximately 10,000 sample cycles later, the outputs reach VQ and audio output begins. This gradual voltage ramping allows time for the external DC-blocking capacitor to charge to VQ, effectively blocking the quiescent DC voltage. To prevent transients at power-down, the device must first enter its power-down state. This is accomplished by rem- oving MCLK or LRCK. When this occurs, audio output ceases and the internal output buffers are disconnected from AOUTL and AOUTR. A soft-start current sink is substituted in place of AOUTL and AOUTR which allows the DC-blo- cking capacitors to slowly discharge. Once this charge is dissipated, the power to the device may be turned off, and the system is ready for the next power-on. To prevent an audio transient at the next power-on, the DC-blocking capacitors must fully discharge before turning off the power or exiting the power-down state. If full discharge does not occur, a transient will occur when the audio outputs are initially clamped to AGND. The time that the device must remain in the power-down state is related to the value of the DC-blocking capacitance. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 8 of 9 QW-R502-441A M4334 CMOS IC SYSTEM CLOCK The M4334 accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in BRM and 96, 88.2 and 64 kHz in HRM. The LRCK chooses the channel and delineation of data, and the SCLK clocks audio data into the input data buffer. MCLK MCLK must be either 256x, 384x or 512x the desired input sample rate in BRM and either 128x or 192x the desired input sample rate in HRM. The LRCK frequency is equal to Fs, the frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected automatically during the initialization sequence by counting the number of MCLK transitions during a single LRCK period. Internal dividers are set to generate the proper clocks. The MCLK, LRCK and SCLK must be synchronous. Table 1 illustrates several standard audio sample rates and the required MCLK and LRCK frequencies. MCLK(MHz) HRM LRCK(kHz) 32 44.1 48 64 88.2 96 128x 4.0960 5.6448 6.1440 8.1920 11.2896 12.2880 192x 256x 6.1440 8.1920 8.4672 11.2896 9.2160 12.2880 12.2880 16.9344 18.4320 Table 1. Common Clock Frequencies BRM 384x 12.2880 16.9344 18.4320 512x 16.3840 22.5792 24.5760 SCLK The SCLK controls the shifting of data into the input data buffers. The M4334 supports both internal and external SCLK generation modes. Internal SCLK Mode In the Internal SCLK Mode, the SCLK is internally derived and synchronous with MCLK and LRCK. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending upon data format. Operation in this mode is identical to operation w- ith an external SCLK synchronized with LRCK. This mode allows access to the digital de-emphasis function. While the Internal SCLK Mode is provided to allow access to the de-emphasis filter, the Internal SCLK Mode also eliminates possible clock interference from an external SCLK. External SCLK Mode The M4334 will enter the external SCLK mode when 16 low to high transitions are detected on the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal SCLK Mode and de-emphasis filter cannot be accessed. The M4334 will switch to Internal SCLK Mode if no low to high transitions are detected on the DEM/SCLK pin for 2 consecutive frames of LRCK. UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 9 of 9 QW-R502-441A