UTC-IC M1725

UNISONIC TECHNOLOGIES CO., LTD
M1725
CMOS IC
16-BIT,96KHZ STEREO AUDIO
D/A CONVERTER
„
DESCRIPTION
The UTC M1725 is a complete stereo digital-to-analog output
system including a 16-bit D/A conversion, a 5-level 3rd-order ∆Σ
modulator, a digital interpolation filter, and an analog output amplifier
in a small 14-pin package.
The UTC M1725 can be operating with from a single 5V power
supply and requires minimal support circuitry. These features are
ideal for set-top boxes, DVD players and A/V receivers, etc.
„
FEATURES
* Complete Stereo DAC System: Interpolation, D/A, Output Analog
Filtering
* 16-Bit Conversion
* 95dB Dynamic Range
* Single +5V Power Supply
* 16kHz to 96kHz Multiple Sampling Frequencies
* 8X Oversampling Digital Filter
* 256 fS /384 fS System Clock
* Normal or I2S Data Input Formats
„
SOP-14
ORDERING INFORMATION
Ordering Number
M1725G-S14-R
Package
SOP-14
www.unisonic.com.tw
Copyright © 2010 Unisonic Technologies Co., Ltd
Packing
Tape Reel
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M1725
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CMOS IC
PIN CONFIGURATIONS
LRCIN
1
14
SCKI
DIN
2
13
FORMAT
BCKIN
3
12
DM
NC
4
11
NC
CAP
5
10
NC
VOUTR
6
9
VOUTL
GND
7
8
VCC
PIN DESCRIPTION
PIN NO
1
2
3
4
5
6
7
8
9
10
11
PIN NAME
LRCIN
DIN
BCKIN
NC
CAP
VOUTR
GND
VCC
VOUTL
NC
NC
PIN TYPE
I
I
I
-I/O
O
I/O
I/O
O
---
12
DM
I
13
FORMAT
I
14
SCKI
I
PIN DESCRIPTION
Left/Right Clock Input
Serial Audio Data Input
Bit Clock Input for Audio Data
No Connection
Common Pin of Analog Output Amp
Right-Channel Analog Output
Ground
Power Supply
Left-Channel Analog Output
No Connection
No Connection
De-emphasis Control
High: De-emphasis OFF
Low: De-emphasis ON(44.1kHz)
Audio Data Format Select
High: I2S Data Format
Low: Standard Data Format
System Clock Input (256 fS or 384 fS)
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CMOS IC
BLOCK DIAGRAM
SCKI
256fS/384fS
Power Supply
BCKIN
LRCIN
DM
FORMAT
5-Level
3rd-order ∆Σ
Modulator
Serial Input
Interface
DIN
Deemphasis
GND
VCC
DAC
Analog
Low-Pass
Filter
8X
Oversampling
Digital Filter
Normal or
I2S Data
Input Format
UNISONIC TECHNOLOGIES CO., LTD
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VOUTL
CAP
5-Level
3rd-order ∆Σ
Modulator
DAC
Analog
Low-Pass
Filter
VOUTR
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CMOS IC
ABSOLUTE MAXIMUM RATING (Ta=25°C, unless otherwise specified)
PARAMETER
SYMBOL
RATINGS
UNIT
Power Supply Voltage
VCC
+6.5
V
+ VCC to+ VDD Difference
VD
±0.1
V
Input Logic Voltage
VLGC
-0.3V to (VDD +0.3V)
W
Power Dissipation
PD
300
mW
Operating Temperature Range
TOPR
-25 ~ +85
°C
Storage Temperature
TSTG
-55 ~ +125
°C
Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
„
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Power Supply Voltage
Junction Temperature
Storage Temperature
„
RATINGS
4.5 ~ 5.5
-25 ~ +85
-55 ~ +100
UNIT
V
°C
°C
SYMBOL
θJA
RATINGS
70
UNIT
°C/W
THERMAL DATA
PARAMETER
Junction to Ambient
„
SYMBOL
VCC
TJ
TSTG
ELECTRICAL CHARACTERISTICS
(Ta=25°C, VCC=+5V, fS=44.1kHz, CAP=10uF, 16-Bit Input Data, SCKI=384 fS, unless otherwise specified)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DATA FORMAT
Data Bit Length
16
Bits
Input sample Rate
fS
16
96
kHz
Internal System Clock Frequency
SCKI
256/384
fS
DIGITAL INPUT/OUTPUT
Logic Level
TTL
VIH
2
V
Input Logic Level (Note1)
VIL
0.8
V
Input Logic Current (Note1)
IIN
±0.8
uA
DYNAMIC PERFORMANCE (Note2)
THD+N at FS (0dB)
f=991kHz
-83
-78
dB
THD+N at -60dB
f=991kHz
-32
dB
Dynamic Range
DR
f=991kHz,A-weighted
90
95
dB
Signal-to-Noise Ratio
SNR
f=991kHz,A-weighted
90
97
dB
Channel Separation
CS
f=991kHz
88
95
dB
DC ACCURACY
Gain Arror
±1.0
±5.0
% of FSR
Gain Mis-match(Channel-to-Channel)
±1.0
±5.0
% of FSR
Bipolar Zero Error
BZE
VOUT=VCC/2 at BPZ
±20
±50
mV
ANALOG OUTPUT
Output Voltage
VO
Full Scale(0dB)
VP-P
0.62*VCC
Center Voltage
VC
VCC/2
V
Load Impedance
RL
AC Load
10
kΩ
Note: 1. Pins 1, 2, 3, 12, 13: LRCIN, DIN, BCKIN, DM, FORMAT (Schmitt Trigger Input); Pin 14: SCKI.
2. Dynamic performance specs are tested with 20kHz low pass filter and THD+N specs are tested with 30kHz
LPF, 400Hz HPF, Average-Mode.
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CMOS IC
ELECTRICAL CHARACTERISTICS (Cont.)
PARAMETER
DIGITAL FILTER PERFORMANCE
Passband
Stopband
Passband Ripple
Stopband Attenuation
Delay Time
INTERNAL ANALOG FILTER
-3dB Bandwidth
Passband Response
POWER SUPPLY REQUIREMENTS
Voltage Range
Supply Current
Power Dissipation
SYMBOL
TEST CONDITIONS
TYP
MAX
UNIT
0.445
11.125/ fS
fS
fS
dB
dB
Sec
100
-0.16
kHz
dB
0.555
±0.17
-35
TD
f=20kHz
VCC
IQ
PD
UNISONIC TECHNOLOGIES CO., LTD
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MIN
4.5
5
13
65
5.5
18
90
V
mA
mW
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CMOS IC
TYPICAL APPLICATIONS CIRCUIT
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CMOS IC
TIMING DIAGRAMS
1.4V
LRCKIN
tBCKH
tBCKL
tBL
tLB
1.4V
BCKIN
tCY
DIN
1.4V
tDH
tDS
tCY
BCKIN Pulse Cycle Time
≥100ns
tBCKH
BCKIN Pulse Width High
≥50ns
tBCKL
BCKIN Pulse Width Low
≥50ns
tBL
BCKIN Rising Edge to LRCIN Edge
≥30ns
tLB
LRCIN Edge to BCKIN Rising Edge
≥30ns
tDS
DIN Set Up Time
≥30ns
tDH
DIN Hold Time
≥30ns
Figure 1.Audio Data Input Timing
Figure 2.Normal Data Input Timing
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CMOS IC
TIMING DIAGRAMS (Cont.)
1/fS
LRCIN
RIGHT
LEFT
BCKIN
15 14 13
DIN
MSB
2
0
1
15 14 13
2
1
MSB
LSB
0
15 14
LSB
2
Figure 3. I S Data Input Timing
tSCKIH
2.0V
SCKI
0.8V
tSCKIL
tSCKIH
System Clock Pulse Width High
≥13ns
tSCKIL
System Clock Pulse Width Low
≥13ns
Figure 4. System Clock Timing
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CMOS IC
FUNCTIONAL DESCRIPTION
SYSTEM CLOCK
The system clock (SCKI) must be either 256 fS or 384 fS, where fS is the audio sampling frequency (LRCIN),typically
32kHz, 44.1kHz or 48kHz. The system clock is used to operate the digital filter and the noise shaper. Timing
conditions for SCKI are shown in Figure4.
M1725 includes a system clock detection circuit which auto-matically detects the frequency, either 256 fS or 384 fS.
The system clock should be synchronized with LRCIN,but M1725 can compensate for phase differences. If the
phase difference between LRCIN and system clock is greater than ±6 bit clocks (BCKIN), the synchronization is
performed automatically. The analog outputs are forced to a bipolar zero state (VCC/2) during the synchronization
function. The typical system clock frequency inputs vs sampling rate for the M1725 is shown below.
SAMPLING RATE(LRCIN)(kHz)
32
44.1
48
SYSTEM CLOCK FREQUENCY(MHz)
256 fS
384 fS
8.192
12.288
11.2896
16.934
12.288
18.432
INPUT DATA FORMAT
M1725 can accept input data in either normal (MSB-first, right-justified) or I2S format by applying LOW or HIGH
voltage level on FORMAT-pin.
FORMAT
Low
High
INPUT DATA FORMAT SELECTED
Normal Format (MSB-first, right-justified)
I2S Format (Philips serial data protocol)
DE-EMPHASIS CONTROL
DM-pin enables M1725’s de-emphasis function. De-emphasis operates only at 44.1kHz.
DM
DE-EMPHASIS FUNCTION SELECTED
Low
De-emphasis ON (44.1kHz)
High
De-emphasis OFF
RESET
M1725 includes an internal power-on reset circuit. The power-on reset initializes and has an initialization period
equal to 1024 system clock periods after VCC>2.2V. During the initialization period, the DAC outputs are invalid, and
the analog outputs are forced to VCC/2.
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CMOS IC
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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www.unisonic.com.tw
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