CS4334/5/8/9
8-Pin, 24-Bit, 96 kHz Stereo D/A Converter
Features
Description
Complete Stereo DAC System: Interpolation,
D/A, Output Analog Filtering
24-Bit Conversion
96 dB Dynamic Range
The CS4334 family members are complete, stereo
digital-to-analog output systems including interpolation,
1-bit D/A conversion and output analog filtering in an
8-pin package. The CS4334/5/8/9 support all major
audio data interface formats, and the individual devices
differ only in the supported interface format.
The CS4334 family is based on Delta-Sigma modulation,
where the modulator output controls the reference voltage input to an ultra-linear analog low-pass filter. This
architecture allows for infinite adjustment of sample rate
between 2 kHz and 100 kHz simply by changing the
master clock frequency.
-88 dB THD+N
Low Clock Jitter Sensitivity
Single +5 V Power Supply
Filtered Line Level Outputs
The CS4334 family contains on-chip digital de-emphasis, operates from a single +5V power supply, and
requires minimal support circuitry. These features are
ideal for set-top boxes, DVD players, SVCD players, and
A/V receivers.
On-Chip Digital De-emphasis
Popguard® Technology
Functionally Compatible with CS4330/31/33
ORDERING INFORMATION
See page 24
I
LRCK
SDATA
DEM/SCLK
2
AGND
6
VA
7
Serial Input
Interface
De-emphasis
Voltage Reference
Interpolator
∆Σ
Modulator
DAC
Analog
Low-Pass
Filter
8
Interpolator
∆Σ
Modulator
DAC
Analog
Low-Pass
Filter
5
3
1
AOUTL
AOUTR
4
MCLK
Cirrus Logic, Inc.
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2004
(All Rights Reserved)
JUL ‘04
DS248F3
1
CS4334/5/8/9
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ....................................................................... 4
SPECIFIED OPERATING CONDITIONS ................................................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4
ANALOG CHARACTERISTICS ................................................................................................ 5
POWER AND THERMAL CHARACTERISTICS....................................................................... 7
DIGITAL INPUT CHARACTERISTICS ..................................................................................... 8
SWITCHING CHARACTERISTICS .......................................................................................... 9
2. TYPICAL CONNECTION DIAGRAM ..................................................................................... 11
3. GENERAL DESCRIPTION .................................................................................................... 12
3.1 Digital Interpolation Filter ................................................................................................. 12
3.2 Delta-Sigma Modulator .................................................................................................... 12
3.3 Switched-Capacitor DAC ................................................................................................. 12
3.4 Analog Low-Pass Filter .................................................................................................... 12
4. SYSTEM DESIGN .................................................................................................................. 13
4.1 Master Clock .................................................................................................................... 13
4.2 Serial Clock ...................................................................................................................... 13
4.2.1 External Serial Clock Mode ................................................................................. 13
4.2.2 Internal Serial Clock Mode .................................................................................. 13
4.3 De-Emphasis ................................................................................................................... 13
4.4 Initialization and Power-Down .......................................................................................... 14
4.5 Output Transient Control .................................................................................................. 14
4.6 Grounding and Power Supply Decoupling ....................................................................... 14
4.7 Analog Output and Filtering ............................................................................................. 14
4.8 Overall Base-Rate Frequency Response ........................................................................ 18
4.9 Overall High-Rate Frequency Response ......................................................................... 19
4.10 Base Rate Mode Performance Plots .............................................................................. 20
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to http://www.cirrus.com/
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain
the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are
sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for
manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing
this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other
intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of
the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend
to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR
SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE
BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS,
STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE,
WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES
OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY
CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING
ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
I²C is a registered trademark of Philips Semiconductor. Purchase of I²C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I²C Patent Rights to use those components in a standard I²C system.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, and Popguard® are trademarks of Cirrus Logic, Inc. All other brand and product names in
this document may be trademarks or service marks of their respective owners.
2
DS248F3
CS4334/5/8/9
4.11 High Rate Mode Performance Plots .............................................................................. 21
5. PIN DESCRIPTIONS ............................................................................................................. 22
6. PARAMETER DEFINITIONS ................................................................................................. 23
7. REFERENCES ....................................................................................................................... 23
8. ORDERING INFORMATION: ............................................................................................... 24
9. FUNCTIONAL COMPATIBILITY ........................................................................................... 24
10. PACKAGE DIMENSIONS ................................................................................................... 25
LIST OF FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Output Test Load .......................................................................................................... 7
Maximum Loading......................................................................................................... 7
Power vs. Sample Rate ................................................................................................ 7
External Serial Mode Input Timing .............................................................................. 10
Internal Serial Mode Input Timing ............................................................................... 10
Internal Serial Clock Generation ................................................................................ 10
Recommended Connection Diagram.......................................................................... 11
System Block Diagram................................................................................................ 12
De-Emphasis Curve (Fs = 44.1kHz) ........................................................................... 13
CS4334 Data Format (I2S).......................................................................................... 15
CS4335 Data Format .................................................................................................. 15
CS4338 Data Format .................................................................................................. 15
CS4339 Data Format .................................................................................................. 16
CS4334/5/8/9 Initialization and Power-Down Sequence ............................................ 17
Stopband Rejection..................................................................................................... 18
Transition Band ........................................................................................................... 18
Transition Band ........................................................................................................... 18
Passband Ripple ......................................................................................................... 18
Stopband Rejection..................................................................................................... 19
Transition Band ........................................................................................................... 19
Transition Band ........................................................................................................... 19
Passband Ripple ......................................................................................................... 19
0 dBFS FFT (BRM) ..................................................................................................... 20
-60 dBFS FFT (BRM).................................................................................................. 20
Idle Channel Noise FFT (BRM)................................................................................... 20
Twin Tone IMD FFT (BRM)......................................................................................... 20
THD+N vs. Amplitude (BRM) ...................................................................................... 20
THD+N vs. Frequency (BRM) ..................................................................................... 20
0 dBFS FFT (HRM)..................................................................................................... 21
-60 dBFS FFT (HRM).................................................................................................. 21
Idle Channel Noise FFT (HRM) .................................................................................. 21
Twin Tone IMD FFT (HRM) ........................................................................................ 21
THD+N vs. Amplitude (HRM)...................................................................................... 21
THD+N vs. Frequency (HRM)..................................................................................... 21
LIST OF TABLES
Table 1.
Table 2.
DS248F3
Common Clock Frequencies ..................................................................................... 13
3
CS4334/5/8/9
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltages
and TA = 25°C.)
SPECIFIED OPERATING CONDITIONS (AGND = 0V; all voltages with respect to ground.)
Parameters
DC Power Supply
Ambient Operating Temperature (Power Applied)
Symbol
VA
-KS
-BS/-DS
TA
Min
4.75
-10
-40
Nom
5.0
-
Max
5.5
+70
+85
Units
V
°C
°C
ABSOLUTE MAXIMUM RATINGS (AGND = 0V; all voltages with respect to ground.)
Parameters
DC Power Supply
Input Current, Any Pin Except Supplies
Digital Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
Symbol
VA
Iin
VIND
TA
Tstg
Min
-0.3
-0.3
-55
-65
Max
6.0
±10
VA+0.4
125
150
Units
V
mA
V
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these extremes.
4
DS248F3
CS4334/5/8/9
ANALOG CHARACTERISTICS (Full-Scale Output Sine Wave, 997 Hz; Test load RL = 10 kΩ, CL =
10 pF (see Figure 1). Fs for Base-Rate Mode = 48 kHz, Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified; Fs for High-Rate Mode = 96 kHz, Measurement Bandwidth 10 Hz to 40 kHz, unless otherwise specified.)
Base-Rate Mode
Parameter
Symbol
High-Rate Mode
Min
Typ
Max
Min
Typ
Max
Unit
88
91
86
89
93
96
91
94
-
91
89
90
96
88
94
-
dB
dB
dB
dB
-
-88
-73
-33
-86
-71
-31
-83
-68
-28
-81
-66
-26
-
-88
-70
-30
-86
-68
-28
-83
-65
-25
-81
-63
-23
dB
dB
dB
dB
dB
dB
-
94
-
-
95
-
dB
85
88
83
86
93
96
91
94
-
88
86
90
96
88
94
-
dB
dB
dB
dB
-
-88
-73
-33
-86
-71
-31
-82
-65
-25
-70
-63
-23
-
-88
-70
-30
-86
-68
-28
-82
-62
-22
-80
-60
-20
dB
dB
dB
dB
dB
dB
-
94
-
-
95
-
dB
Dynamic Performance for CS4334/5/8/9-KS
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
Interchannel Isolation
(Note 1)
unweighted
A-Weighted
unweighted
A-Weighted
(Note 1) THD+N
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
(1 kHz)
Dynamic Performance for CS4334/5/8/9-BS/-DS
Dynamic Range
18 to 24-Bit
16-Bit
Total Harmonic Distortion + Noise
18 to 24-Bit
16-Bit
Interchannel Isolation
Note:
(Note 1)
unweighted
A-Weighted
unweighted
A-Weighted
(Note 1) THD+N
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
(1 kHz)
1. One-half LSB of triangular PDF dither added to data.
DS248F3
5
CS4334/5/8/9
ANALOG CHARACTERISTICS (Continued)
Base-Rate Mode
Parameter
Symbol
Min
Typ
High-Rate Mode
Max
Min
Typ
Max Unit
Combined Digital and On-chip Analog Filter Response (Note 2)
Passband
(Note 3)
to -0.05 dB corner
to -0.1 dB corner
to -3 dB corner
Frequency Response 10 Hz to 20 kHz
Passband Ripple
StopBand
0
0
-
.4780
.4996
0
0
-
.4650
.4982
Fs
Fs
Fs
-.01
-
+.08
-.05
-
+.2
dB
-
-
±.08
-
-
±.2
dB
.5465
-
-
.5770
-
-
Fs
50
-
-
55
-
-
dB
-
9/Fs
-
-
4/Fs
-
s
Passband Group Delay Deviation 0 - 40 kHz
0 - 20 kHz
-
±0.36/Fs
-
-
±1.39/Fs
±0.23/Fs
-
s
s
De-emphasis Error
-
-
+1.5/+0
+.05/-.25
-.2/-.4
StopBand Attenuation
(Note 4)
Group Delay
tgd
Fs = 32 kHz
Fs = 44.1 kHz
Fs = 48 kHz
Parameters
DC Accuracy
Interchannel Gain Mismatch
Gain Error
Gain Drift
Analog Output
Full Scale Output Voltage
Quiescent Voltage
Max AC-Load Resistance
Max Load Capacitance
Symbol
(Note 6)
(Note 6)
VQ
RL
CL
(Note 5)
dB
dB
dB
Min
Typ
Max
Units
-
0.1
±5
100
0.4
-
dB
%
ppm/°C
3.25
-
3.5
2.2
3
100
3.75
-
Vpp
VDC
kΩ
pF
Notes: 2. Filter response is not tested but is guaranteed by design.
3. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 15-22) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
4. For Base-Rate Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs.
For High-Rate Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs.
5. De-emphasis is not available in High-Rate Mode.
6. Refer to Figure 2.
6
DS248F3
CS4334/5/8/9
POWER AND THERMAL CHARACTERISTICS
Parameters
Power Supplies
Power Supply Current
normal operation
power-down state
(Note 7)
normal operation
power-down
Power Dissipation
Package Thermal Resistance
Power Supply Rejection Ratio
(1 kHz)
Symbol
Min
Typ
Max
Units
IA
IA
-
15
40
19
-
mA
µA
θJA
PSRR
-
75
0.2
110
79
104
-
mW
mW
°C/Watt
dB
Notes: 7. Refer to Figure 3. Max Power Dissipation is measured at VA=5.5V.
10 µF
V
out
AOUTx
R
C
L
L
AGND
100
70
75
Safe Operating
Region
50
25
2.5
3
65
HR
M
60
55
5
10
15
Resistive Load -- RL (kΩ )
Figure 2. Maximum Loading
DS248F3
M
75
BR
125
Power (mW)
Capacitive Load -- C L (pF)
Figure 1. Output Test Load
20
50
30
40
50
60
70
80
Sample Rate (kHz)
90
100
Figure 3. Power vs. Sample Rate
7
CS4334/5/8/9
DIGITAL INPUT CHARACTERISTICS
Parameters
High-Level Input Voltage
Low-Level Input Voltage
Input Leakage Current
Input Capacitance
(Note 8)
Symbol
VIH
VIL
Iin
Min
2.0
-
Typ
8
Max
0.8
±10
-
Units
V
V
µA
pF
8. Iin for CS433X LRCK is ±20µA max.
8
DS248F3
CS4334/5/8/9
SWITCHING CHARACTERISTICS
Parameters
Symbol
Input Sample Rate
Typ
Max
Units
2
-
100
kHz
MCLK Pulse Width High
MCLK/LRCK = 512
10
-
1000
ns
MCLK Pulse Width Low
MCLK/LRCK = 512
10
-
1000
ns
MCLK Pulse Width High MCLK / LRCK = 384 or 192
21
-
1000
ns
MCLK Pulse Width Low
Fs
Min
MCLK / LRCK = 384 or 192
21
-
1000
ns
MCLK Pulse Width High MCLK / LRCK = 256 or 128
31
-
1000
ns
MCLK Pulse Width Low
31
-
1000
ns
MCLK / LRCK = 256 or 128
External SCLK Mode
LRCK Duty Cycle (External SCLK only)
40
50
60
%
SCLK Pulse Width Low
tsclkl
20
-
-
ns
SCLK Pulse Width High
tsclkh
20
-
-
ns
-
-
ns
-
-
ns
SCLK Period
MCLK / LRCK = 512, 256 or 384
Base-Rate Mode
tsclkw
SCLK Period
MCLK / LRCK = 128 or 192
High-Rate Mode
tsclkw
1
---------------------( 128 )Fs
1
------------------( 64 )Fs
SCLK rising to LRCK edge delay
tslrd
20
-
-
ns
SCLK rising to LRCK edge setup time
tslrs
20
-
-
ns
SDATA valid to SCLK rising setup time
tsdlrs
20
-
-
ns
SCLK rising to SDATA hold time
tsdh
20
-
-
ns
-
50
-
%
-
-
ns
-
µs
-
-
ns
-
-
ns
-
-
ns
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only)
SCLK Period
(Note 9)
(Note 10)
SCLK rising to LRCK edge
tsclkw
tsclkr
1
----------------SCLK
tsclkw
-----------------2
SDATA valid to SCLK rising setup time
tsdlrs
SCLK rising to SDATA hold time
MCLK / LRCK = 512, 256 or 128
tsdh
SCLK rising to SDATA hold time
MCLK / LRCK = 384 or 192
tsdh
1
---------------------- + 10
( 512 ) Fs
1
---------------------- + 15
( 512 )Fs
1
---------------------- + 15
( 384 )Fs
Notes: 9. In Internal SCLK Mode, the Duty Cycle must be 50% +/− 1/2 MCLK Period.
10. The SCLK / LRCK ratio may be either 32, 48, or 64. This ratio depends on part type and MCLK/LRCK
ratio. (See figures 10-13)
DS248F3
9
CS4334/5/8/9
LRCK
t sclkh
t slrs
t slrd
t sclkl
SCLK
t sdh
t sdlrs
SDATA
Figure 4. External Serial Mode Input Timing
LRCK
t sclkr
SDATA
t sclkw
t sdlrs
t sdh
*INTERNAL SCLK
Figure 5. Internal Serial Mode Input Timing
* The SCLK pulses shown are internal to the CS4334/5/8/9.
LRCK
MCLK
1
N
2
N
*INTERNAL SCLK
SDATA
Figure 6. Internal Serial Clock Generation
* The SCLK pulses shown are internal to the CS4334/5/8/9.
N equals MCLK divided by SCLK
10
DS248F3
CS4334/5/8/9
2. TYPICAL CONNECTION DIAGRAM
+5V
+
7
0.1 µF
1 µF
VA
1
Audio
Data
Processor
2
3
SDATA
3.3 µF
8
DEM /SCLK
AOUTL
LRCK
560 Ω
Left A udio
O utput
+
267 k Ω
C
10 k Ω
RL
CS4334
CS4335
CS4338
CS4339
3.3 µF
560 Ω
5
AO UTR
External C lock
4
MCLK
Right Audio
O utput
+
267 k Ω
C
10 k Ω
AG ND
C=
RL
R L + 560
4 π Fs(R L560)
6
Figure 7. Recommended Connection Diagram
DS248F3
11
CS4334/5/8/9
3. GENERAL DESCRIPTION
The CS4334 family of devices offers a complete
stereo digital-to-analog system including digital
interpolation, fourth-order delta-sigma digital-toanalog conversion, digital de-emphasis and analog
filtering, as shown in Figure 8. This architecture
provides a high tolerance to clock jitter.
The primary purpose of using delta-sigma modulation techniques is to avoid the limitations of resistive laser trimmed digital-to-analog converter
architectures by using an inherently linear 1-bit
digital-to-analog converter. The advantages of a
1-bit digital-to-analog converter include: ideal differential linearity, no distortion mechanisms due to
resistor matching errors and no linearity drift over
time and temperature due to variations in resistor
values.
filter eliminates images of the baseband audio signal which exist at multiples of the input sample
rate. The resulting frequency spectrum has images
of the input signal at multiples of 4 Fs. These images are easily removed by the on-chip analog lowpass filter and a simple external analog filter (see
Figure 7).
3.2 Delta-Sigma Modulator
The interpolation filter is followed by a fourth
order delta-sigma modulator which converts the
interpolation filter output into 1-bit data at a rate of
128 Fs in BRM (or 64 Fs in HRM).
3.3 Switched-Capacitor DAC
The CS4334 family of devices supports two modes
of operation. The devices operate in Base Rate
Mode (BRM) when MCLK/LRCK is 256, 384 or
512 and in High Rate Mode (HRM) when
MCLK/LRCK is 128 or 192. High Rate Mode allows input sample rates up to 100 kHz.
The delta-sigma modulator is followed by a digitalto-analog converter which translates the 1-bit data
into a series of charge packets. The magnitude of
the charge in each packet is determined by sampling of a voltage reference onto a switched capacitor, where the polarity of each packet is controlled
by the 1-bit data. This technique greatly reduces the
sensitivity to clock jitter and provides low-pass filtering of the output.
3.1 Digital Interpolation Filter
3.4 Analog Low-Pass Filter
The digital interpolation filter increases the sample
rate, Fs, by a factor of 4 and is followed by a
32× digital sample-and-hold (16× in HRM). This
The final signal stage consists of a continuous-time
low-pass filter which serves to smooth the output
and attenuate out-of-band noise.
Digital
Input
Interpolator
Delta-Sigma
Modulator
DAC
Analog
Low-Pass
Filter
Analog
Output
Figure 8. System Block Diagram
12
DS248F3
CS4334/5/8/9
4. SYSTEM DESIGN
4.2.1 External Serial Clock Mode
The CS4334 family accepts data at standard audio
sample rates including 48, 44.1 and 32 kHz in
BRM and 96, 88.2 and 64 kHz in HRM. Audio data
is input via the serial data input pin (SDATA). The
Left/Right Clock (LRCK) defines the channel and
delineation of data, and the Serial Clock (SCLK)
clocks audio data into the input data buffer. The
CS4334/5/8/9 differ in serial data formats as shown
in Figures 10-13.
The CS4334 family will enter the External Serial
Clock Mode when 16 low to high transitions are
detected on the DEM/SCLK pin during any phase
of the LRCK period. When this mode is enabled,
the Internal Serial Clock Mode and de-emphasis
filter cannot be accessed. The CS4334 family will
switch to Internal Serial Clock Mode if no low to
high transitions are detected on the DEM/SCLK
pin for 2 consecutive frames of LRCK. Refer to
Figure 14.
4.1 Master Clock
MCLK must be either 256x, 384x or 512x the desired input sample rate in BRM and either 128x or
192x the desired input sample rate in HRM. The
LRCK frequency is equal to Fs, the frequency at
which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio is detected automatically during the initialization
sequence by counting the number of MCLK transitions during a single LRCK period. Internal dividers are set to generate the proper clocks. Table 1
illustrates several standard audio sample rates and
the required MCLK and LRCK frequencies. Please
note there is no required phase relationship, but
MCLK, LRCK and SCLK must be synchronous.
LRCK
(kHz)
32
44.1
48
64
88.2
96
MCLK (MHz)
HRM
BRM
128x
192x
256x
384x
512x
4.0960 6.1440 8.1920 12.2880 16.3840
5.6448 8.4672 11.2896 16.9344 22.5792
6.1440 9.2160 12.2880 18.4320 24.5760
8.1920 12.2880
11.2896 16.9344
12.2880 18.4320
-
4.2.2 Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock
is internally derived and synchronous with MCLK
and LRCK. The SCLK/LRCK frequency ratio is either 32, 48, or 64 depending upon data format. Operation in this mode is identical to operation with
an external serial clock synchronized with LRCK.
This mode allows access to the digital de-emphasis
function. Refer to Figures 10 - 14 for details.
4.3 De-Emphasis
The CS4334 family includes on-chip digital de-emphasis. Figure 9 shows the de-emphasis curve for
Fs equal to 44.1 kHz. The frequency response of
the de-emphasis curve will scale proportionally
with changes in sample rate, Fs.
The de-emphasis filter is active (inactive) if the
DEM/SCLK pin is low (high) for 5 consecutive
falling edges of LRCK. This function is available
only in the internal serial clock mode.
Gain
dB
T1=50 µs
Table 1. Common Clock Frequencies
0dB
4.2 Serial Clock
The serial clock controls the shifting of data into
the input data buffers. The CS4334 family supports
both external and internal serial clock generation
modes. Refer to Figures 10-13 for data formats.
DS248F3
T2 = 15 µs
-10dB
F1
3.183 kHz
F2
Frequency
10.61 kHz
Figure 9. De-Emphasis Curve (Fs = 44.1kHz)
13
CS4334/5/8/9
4.4 Initialization and Power-Down
The Initialization and Power-Down sequence flow
chart is shown in Figure 14. The CS4334 family enters the Power-Down State upon initial power-up.
The interpolation filters and delta-sigma modulators are reset, and the internal voltage reference,
one-bit digital-to-analog converters and switchedcapacitor low-pass filters are powered down. The
device will remain in the Power-Down mode until
MCLK and LRCK are present. Once MCLK and
LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the
MCLK/LRCK frequency ratio. Power is then applied to the internal voltage reference. Finally, power is applied to the D/A converters and switchedcapacitor filters, and the analog outputs will ramp to
the quiescent voltage, VQ.
4.5 Output Transient Control
The CS4334 family uses Popguard® technology to
minimize the effects of output transients during
power-up and power-down. This technique eliminates the audio transients commonly produced by
single-ended single-supply converters when it is
implemented with external DC-blocking capacitors
connected in series with the audio outputs. To
make best use of this feature, it is necessary to understand its operation.
When the device is initially powered-up, the audio
outputs, AOUTL and AOUTR, are clamped to
AGND. After a short delay of approximately 1000
sample periods, each output begins to ramp towards its quiescent voltage, VQ. Approximately
10,000 sample cycles later, the outputs reach VQ
and audio output begins. This gradual voltage
ramping allows time for the external DC-blocking
capacitor to charge to VQ, effectively blocking the
quiescent DC voltage.
complished by removing MCLK or LRCK. When
this occurs, audio output ceases and the internal
output buffers are disconnected from AOUTL and
AOUTR. A soft-start current sink is substituted in
place of AOUTL and AOUTR which allows the
DC-blocking capacitors to slowly discharge. Once
this charge is dissipated, the power to the device
may be turned off, and the system is ready for the
next power-on.
To prevent an audio transient at the next power-on,
the DC-blocking capacitors must fully discharge
before turning off the power or exiting the powerdown state. If full discharge does not occur, a transient will occur when the audio outputs are initially
clamped to AGND. The time that the device must
remain in the power-down state is related to the
value of the DC-blocking capacitance. For example, with a 3.3 µF capacitor, the time that the device
must remain in the power-down state will be approximately 0.4 seconds.
4.6 Grounding and Power Supply
Decoupling
As with any high resolution converter, the CS4334
family requires careful attention to power supply
and grounding arrangements to optimize performance. Figure 7 shows the recommended power arrangement with VA connected to a clean +5V
supply. For best performance, decoupling capacitors should be located as close to the device package as possible with the smallest capacitor closest.
4.7 Analog Output and Filtering
The analog filter present in the CS4334 family is a
switched-capacitor filter followed by a continuous
time low pass filter. Its response, combined with
that of the digital interpolator, is given in Figures
15 - 22.
To prevent transients at power-down, the device
must first enter its power-down state. This is ac-
14
DS248F3
CS4334/5/8/9
Left Channel
LRCK
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
Internal SCLK Mode
+5 +4 +3 +2 +1 LSB
External SCLK Mode
2
I S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128
I2S, Up to 24-Bit data and INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
2
I S, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 10. CS4334 Data Format (I2S)
Left Channel
LRCK
Right Channel
SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
Internal SCLK Mode
+5 +4 +3 +2 +1 LSB
External SCLK Mode
Left Justified, up to 24-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Left Justified, up to 24-Bit Data
Data Valid on Rising Edge of SCLK
Figure 11. CS4335 Data Format
LRCK
Right Channel
Left Channel
SCLK
SDATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 16-Bit Data
INT SCLK = 32 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 16-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 12. CS4338 Data Format
DS248F3
15
CS4334/5/8/9
LRCK
Right Channel
Left Channel
SCLK
SDATA
1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
32 clocks
Internal SCLK Mode
External SCLK Mode
Right Justified, 18-Bit Data
INT SCLK = 64 Fs if MCLK/LRCK = 512, 256 or 128
INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
Right Justified, 18-Bit Data
Data Valid on Rising Edge of SCLK
SCLK Must Have at Least 36 Cycles per LRCK Period
Figure 13. CS4339 Data Format
16
DS248F3
CS4334/5/8/9
Figure 14. CS4334/5/8/9 Initialization and Power-Down Sequence
DS248F3
17
CS4334/5/8/9
4.8 Overall Base-Rate Frequency Response
18
Figure 15. Stopband Rejection
Figure 16. Transition Band
Figure 17. Transition Band
Figure 18. Passband Ripple
DS248F3
CS4334/5/8/9
4.9 Overall High-Rate Frequency Response
Figure 19. Stopband Rejection
Figure 21. Transition Band
DS248F3
Figure 20. Transition Band
Figure 22. Passband Ripple
19
CS4334/5/8/9
4.10 Base Rate Mode Performance Plots
+0
+0
+0
-10
-10
-10
-20
-20
-20
-30
-30
-30
+0
+0
+0
-1 0
-10
-10
-2 0
-20
-20
-3 0
-30
-30
-4 0
-40
-40
-5 0
-50
-50
-6 0
-60
-60
-40
-40
-40
-50
-50
-50
d
B
r
-7 0
-70
-70
-8 0
-80
-80
-9 0
-90
-90
-90
-90
-90
-10 0
-100
-100
-11 0
-110
-110
-12 0
-120
-120
-13 0
-130
-130
-14 0
-140
-140
-100
-100
-100
-110
-110
-110
-120
-120
-120
-130
-130
-130
2k
2k
2k
4k
4k
4k
6k
6k
6k
8k
8k
8k
10k
10k
10k
Hz
Hz
Hz
12k
12k
12k
14k
14k
14k
16k
16k
16k
1 8k
18k
18k
-140
-140
-140
20k
20k
20k
6k
6k
6k
8k
8k
8k
10k
10k
10k
Hz
Hz
Hz
12k
12k
12k
14k
14k
14k
16k
16k
16k
(16k FFT of a 1 kHz input signal)
Figure 23. 0 dBFS FFT (BRM)
Figure 24. -60 dBFS FFT (BRM)
18k
18k
18k
20k
20k
20k
18k
2 0k
20k
+0
+0
+0
-1 0
-10
-10
-2 0
-20
-20
-3 0
-30
-30
-4 0
-40
-40
dBr
A
dBr A
-5 0
-50
-50
d
B
r
A
-6 0
-60
-60
-7 0
-70
-70
-8 0
-80
-80
-9 0
-90
-90
-10 0
-100
-100
-11 0
-110
-110
-12 0
-120
-120
-13 0
-130
-130
-140
-140
4k
4k
4k
(16k FFT of a 1 kHz input signal)
-70
-70
-70
-80
-80
-80
-90
-90
-90
A
2k
2k
2k
20k
+0
+0
+0
-10
-10
-10
-20
-20
-20
-30
-30
-30
-40
-40
-40
-50
-50
-50
-60
-60
-60
d
B
r
-70
-70
-70
-80
-80
-80
A
dBr
dBr A
A
A
-60
-60
-60
dBr
A
dBr A
dBr
A
dBr A
d
B
r
-10 0
-100
-100
-11 0
-110
-110
-12 0
-120
-120
-13 0
-130
-130
-14 0
2k
2k
2k
4k
4k
4k
6k
6k
6k
8k
8k
8k
10k
10k
10k
Hz
Hz
Hz
12k
12k
12k
1 4k
14k
14k
16 k
16k
16k
18k
18k
18k
20k
20k
20k
-14 0
-140
-140
2k
2k
2k
4k
4k
4k
6k
6k
6k
8k
8k
8k
10 k
10k
10k
Hz
Hz
Hz
12 k
12k
12k
14k
14k
14k
1 6k
16k
16k
118k
8k
20k
(16k FFT with no input signal)
(16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals)
Figure 25. Idle Channel Noise FFT (BRM)
Figure 26. Twin Tone IMD FFT (BRM)
-60
-60
+0
+0
+0
-10
-10
-10
-20
-20
-20
-70
-70
-30
-30
-30
A
-90
-90
-40
-40
-40
dBr
dBrAA
dBr A
d
B
r
-80
-80
d
B
r
A
-50
-50
-50
-60
-60
-60
-70
-70
-70
-80
-80
-80
-100
-100
-90
-90
-90
-100
-100
-100
-110
-110
-60
-60
-50
-50
-40
-40
-30
-30
-20
-20
-10
-10
+0
+0
dBFS
dBFS
-110
-110
-110
20
20
20
50
50
50
100
100
100
200
200
200
500
500
500
Hz
Hz
Hz
1k
1k
1k
2k
2k
2k
5k
5k
5k
10k
10k
10k
20k
20k
20k
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
Figure 27. THD+N vs. Amplitude (BRM)
Figure 28. THD+N vs. Frequency (BRM)
All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain
System Two Cascade.
20
DS248F3
CS4334/5/8/9
4.11 High Rate Mode Performance Plots
d
B
r
d
B
r
-70
-70
-70
-80
-80
-80
-90
-90
-90
A
+0
+0
+0
-10
-10
-10
-20
-20
-20
-30
-30
-30
-40
-40
-40
-50
-50
-50
-60
-60
-60
dBr
A
dBr A
dBr
A
dBr A
+0
+0
+0
-10
-10
-10
-20
-20
-20
-30
-30
-30
-40
-40
-40
-50
-50
-50
-60
-60
-60
A
-70
-70
-70
-80
-80
-80
-90
-90
-90
-100
-100
-100
-110
-110
-110
-1 00
-100
-100
-1 10
-110
-110
-120
-120
-120
-130
-130
-130
-1 20
-120
-120
-1 30
-130
-130
-140
-140
-140
2k
2k
2k
4k
4k
4k
6k
6k
6k
8k
8k
8k
10k
10k
10k
Hz
Hz
Hz
12 k
12k
12k
14 k
14k
14k
1 6k
16k
16k
18k
18k
18k
-1 40
-140
-140
2 0k
20k
20k
2k
2k
2k
4k
4k
4k
12 k
12k
12k
14k
14k
14k
16k
16k
16k
Figure 29. 0 dBFS FFT (HRM)
Figure 30. -60 dBFS FFT (HRM)
+0
+0
+0
-10
-10
-10
-20
-20
-20
-30
-30
-30
+0
+0
+0
-10
-10
-10
-20
-20
-20
-40
-40
-40
-50
-50
-50
-60
-60
-60
-40
-40
-40
D -A C C IF IMD vs A MP LIT UD E
18k
18k
18k
20 k
20k
20k
0 8/05 /99 1 1:1 1:36
-30
-30
-30
dBr
A
dBr A
-50
-50
-50
d
B
r
-70
-70
-70
-80
-80
-80
-90
-90
-90
-60
-60
-60
-70
-70
-70
-80
-80
-80
-90
-90
-90
A
-1 00
-100
-100
-1 10
-110
-110
-100
-100
-100
-110
-110
-110
-1 20
-120
-120
-1 30
-130
-130
-1 40
-140
-140
1 0k
10k
10k
Hz
Hz
Hz
(16k FFT of a 1 kHz input signal)
dBr
A
dBr A
A
8k
8k
8k
(16k FFT of a 1 kHz input signal)
A udio P rec is io n
d
B
r
6k
6k
6k
-120
-120
-120
-130
-130
-130
2k
2k
4k
4k
4k
2k
6k
6k
6k
8k
8k
8k
10k
10k
10k
Hz
Hz
Hz
12 k
12k
12k
14 k
14k
14k
16k
16k
16k
18 k
18k
18k
-140
-140
-140
20k
20k
20k
2k
2k
2k
4k
4k
4k
6k
6k
6k
8k
8k
8k
10k
10k
10k
Hz
HzHz
12k
12k
12k
14k
14k
14k
16k
16k
16k
18k
18k
18k
20k
20k
20k
(16k FFT with no input signal)
(16k FFT of intermodulation distortion using 13 kHz and 14 kHz input signals)
Figure 31. Idle Channel Noise FFT (HRM)
Figure 32. Twin Tone IMD FFT (HRM)
-60
-60
+0
+0
-10
-10
-10
-20
-20
-20
-70
-70
-30
-30
-30
A
-90
-90
d
B
r
dBr A
-80
-40
-40
-40
dBrdBrAA
-80
d
B
r
-50
-50
-50
-60
-60
-60
A
-70
-70
-70
-80
-80
-80
-100
-100
-90
-90
-90
-100
-100
-100
-110
-110
-60
-60
-50
-50
-40
-40
-30
-30
-20
-20
-10
-10
+0
+0
dBFS
dBFS
-110
-110
-110
20
20
20
50
50
100
100
100
200
200
200
500
500
Hz
Hz
Hz
1k
1k
2k
2k
2k
5k
5k
10k
10k
10k
20k
20k
20k
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
(THD+N plots measured using a 1kHz 24-bit dithered input signal)
Figure 33. THD+N vs. Amplitude (HRM)
Figure 34. THD+N vs. Frequency (HRM)
All measurements were taken from the CDB4334 evaluation board using the Audio Precision Dual Domain
System Two Cascade.
DS248F3
21
CS4334/5/8/9
5. PIN DESCRIPTIONS
SERIAL DATA INPUT
SDATA
1
8
AOUTL
ANALOG LEFT CHANNEL OUTPUT
DE-EMPHASIS / SCLK
DEM/SCLK
2
7
VA
ANALOG POWER
LEFT / RIGHT CLOCK
LRCK
3
6
AGND
ANALOG GROUND
MASTER CLOCK
MCLK
4
5
AOUTR
ANALOG RIGHT CHANNEL OUTPUT
No.
1
Pin Name
SDATA
2
DEM/SCLK
3
LRCK
4
MCLK
5
6
7
8
AOUTR
AGND
VA
AOUTL
22
I/O
Pin Function and Description
I Serial Audio Data Input - two’s complement MSB-first serial data is input on this pin.
The data is clocked into the CS4334/5/8/9 via internal or external SCLK, and the channel
is determined by LRCK.
I De-Emphasis/External Serial Clock Input - used for de-emphasis filter control or external serial clock input.
I Left/Right Clock - determines which channel is currently being input on the Audio Serial
Data Input pin, SDATA.
I Master Clock - frequency must be 256x, 384x, or 512x the input sample rate in BRM and
either 128x or 192x the input sample rate in HRM.
O Analog Right Channel Output - typically 3.5 Vp-p for a full-scale input signal.
I Analog Ground - analog ground reference is 0V.
I Analog Power - analog power supply is nominally +5V.
O Analog Left Channel Output - typically 3.5 Vp-p for a full-scale input signal.
DS248F3
CS4334/5/8/9
6. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)- The ratio of the rms value of the signal to the
rms sum of all other spectral components over the specified bandwidth (typically 10Hz to
20kHz), including distortion components. Expressed in decibels.
Dynamic Range - The ratio of the full scale rms value of the signal to the rms sum of all other
spectral components over the specified bandwidth. Dynamic range is a signal-to-noise
measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added
to the resulting measurement to refer the measurement to full scale. This technique ensures that
the distortion components are below the noise level and do not effect the measurement. This
measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and
the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation - A measure of crosstalk between the left and right channels. Measured
for each channel at the converter's output with all zeros to the input under test and a full-scale
signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch - The gain difference between left and right channels. Units in
decibels.
Gain Error - The deviation from the nominal full scale analog output for a full scale digital
input.
Gain Drift - The change in gain value with temperature. Units in ppm/°C.
7. REFERENCES
1) "How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters" by Steven Harris.
Paper presented at the 93rd Convention of the Audio Engineering Society, October 1992.
2) CDB4334/5/8/9 Evaluation Board Datasheet
DS248F3
23
CS4334/5/8/9
8. ORDER INFORMATION:
Model
CS4334-KS
CS4335-KS
CS4334-KSZ
CS4335-KSZ
CS4338-KS
CS4339-KS
CS4334-BS
CS4339-BS
CS4334-DS
CS4335-DS
CS4338-DS
CS4339-DS
Temperature
-10 to +70 °C
-10 to +70 °C
-10 to +70 °C
-10 to +70 °C
-10 to +70 °C
-10 to +70 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
-40 to +85 °C
Package
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC, lead free
8-pin Plastic SOIC, lead free
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
8-pin Plastic SOIC
Serial Interface
16 to 24-bit, I2S
16 to 24-bit, left justified
16 to 24-bit, I2S
16 to 24-bit, left justified
16-bit, right justified
18-bit, right justified, 32 Fs Internal SCLK mode
16 to 24-bit, I2S
18-bit, right justified, 32 Fs Internal SCLK mode
16 to 24-bit, I2S
16 to 24-bit, left justified
16-bit, right justified
18-bit, right justified, 32 Fs Internal SCLK mode
9. FUNCTIONAL COMPATIBILITY
⇒ CS4339-KS
CS4331-KS ⇒ CS4334-KS
CS4333-KS ⇒ CS4338-KS
CS4330-BS ⇒ CS4339-BS/-DS
CS4331-BS ⇒ CS4334-BS/-DS
CS4333-BS ⇒ CS4338-DS
CS4330-KS
Revision
F3
Date
July 2004
Changes
Removed CS4335-BS and CS4339-BS from the Ordering Information section.
Table 2. Revision History
24
DS248F3
CS4334/5/8/9
10. PACKAGE DIMENSIONS
8L SOIC (150 MIL BODY) PACKAGE DRAWING
E
H
1
b
c
D
SEATING
PLANE
∝
A
L
e
A1
INCHES
DIM
A
A1
B
C
D
E
e
H
L
∝
MIN
0.053
0.004
0.013
0.007
0.189
0.150
0.040
0.228
0.016
0°
MAX
0.069
0.010
0.020
0.010
0.197
0.157
0.060
0.244
0.050
8°
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
4.80
5.00
3.80
4.00
1.02
1.52
5.80
6.20
0.40
1.27
0°
8°
JEDEC # : MS-012
DS248F3
25