TM FQP9N50C/FQPF9N50C 500V N-Channel MOSFET General Description Features These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switched mode power supplies, active power factor correction, electronic lamp ballasts based on half bridge topology. • • • • • • 9 A, 500V, RDS(on) = 0.8 Ω @VGS = 10 V Low gate charge ( typical 28 nC) Low Crss ( typical 24 pF) Fast switching 100% avalanche tested Improved dv/dt capability D ! ● ◀ G! G DS TO-220 TO-220F GD S FQP Series ▲ ● ● FQPF Series ! S Absolute Maximum Ratings Symbol VDSS ID TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current FQP9N50C FQPF9N50C 500 - Continuous (TC = 100°C) Units V 9 9* A 5.4 5.4 * A 36 * A IDM Drain Current VGSS Gate-Source Voltage EAS Single Pulsed Avalanche Energy (Note 2) IAR Avalanche Current (Note 1) 9 A EAR Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TC = 25°C) (Note 1) 13.5 4.5 -55 to +150 mJ V/ns W W/°C °C 300 °C dv/dt PD TJ, TSTG TL - Pulsed (Note 1) 36 (Note 3) - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds ± 30 V 360 mJ 135 1.07 44 0.35 * Drain current limited by maximum junction temperature Thermal Characteristics Symbol RθJC Parameter Thermal Resistance, Junction-to-Case RθCS Thermal Resistance, Case-to-Sink Typ. 0.5 -- °C/W RθJA Thermal Resistance, Junction-to-Ambient 62.5 62.5 °C/W ©2003 Fairchild Semiconductor Corporation FQP9N50C 0.93 FQPF9N50C 2.86 Units °C/W Rev. A, June 2003 FQP9N50C/FQPF9N50C QFET Symbol TC = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units 500 -- -- V -- 0.57 -- V/°C Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C IDSS IGSSF IGSSR VDS = 500 V, VGS = 0 V -- -- 1 µA VDS = 400 V, TC = 125°C -- -- 10 µA Gate-Body Leakage Current, Forward VGS = 30 V, VDS = 0 V -- -- 100 nA Gate-Body Leakage Current, Reverse VGS = -30 V, VDS = 0 V -- -- -100 nA 2.0 -- 4.0 V -- 0.65 0.8 Ω -- 6.5 -- S -- 790 1030 pF -- 130 170 pF -- 24 30 pF -- 18 45 ns -- 65 140 ns -- 93 195 ns -- 64 125 ns -- 28 35 nC -- 4 -- nC -- 15 -- nC Zero Gate Voltage Drain Current On Characteristics VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 µA RDS(on) Static Drain-Source On-Resistance VGS = 10 V, ID = 4.5 A gFS Forward Transconductance VDS = 40 V, ID = 4.5 A (Note 4) Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = 250 V, ID = 9 A, RG = 25 Ω (Note 4, 5) VDS = 400 V, ID = 9 A, VGS = 10 V (Note 4, 5) Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current -- -- 9 A ISM -- -- 36 A VSD Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 9 A Drain-Source Diode Forward Voltage -- -- 1.4 V trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 9 A, dIF / dt = 100 A/µs (Note 4) -- 335 -- ns -- 2.95 -- µC Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 8 mH, IAS = 9A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C 3. ISD ≤ 9A, di/dt ≤ 200A/µs, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2% 5. Essentially independent of operating temperature ©2003 Fairchild Semiconductor Corporation Rev. A, June 2003 FQP9N50C/FQPF9N50C Electrical Characteristics FQP9N50C/FQPF9N50C Typical Characteristics VGS 15.0 V 10.0 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom : 4.5 V Top : ID, Drain Current [A] 1 10 o 150 C ID, Drain Current [A] 1 10 0 10 o -55 C o 25 C 0 10 ※ Notes : 1. 250μ s Pulse Test 2. TC = 25℃ ※ Notes : 1. VDS = 40V 2. 250μ s Pulse Test -1 -1 10 10 -1 0 10 2 1 10 10 4 6 8 10 VGS, Gate-Source Voltage [V] VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 2.0 1 10 IDR, Reverse Drain Current [A] RDS(ON) [Ω ], Drain-Source On-Resistance VGS = 10V 1.5 1.0 VGS = 20V 0.5 ※ Note : TJ = 25℃ 0 10 150℃ ※ Notes : 1. VGS = 0V 2. 250μ s Pulse Test 25℃ -1 0 5 10 15 20 25 10 0.2 0.4 ID, Drain Current [A] Figure 3. On-Resistance Variation vs Drain Current and Gate Voltage 0.8 1.0 1.2 1.4 Figure 4. Body Diode Forward Voltage Variation with Source Current and Temperature 2000 12 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 1200 Coss 800 ※ Notes ; 1. VGS = 0 V 2. f = 1 MHz Crss 400 VGS, Gate-Source Voltage [V] Ciss VDS = 100V 10 1600 Capacitance [pF] 0.6 VSD, Source-Drain voltage [V] VDS = 250V 8 VDS = 400V 6 4 2 ※ Note : ID = 9A 0 0 -1 10 0 10 1 10 0 5 10 15 20 25 30 VDS, Drain-Source Voltage [V] QG, Total Gate Charge [nC] Figure 5. Capacitance Characteristics Figure 6. Gate Charge Characteristics ©2003 Fairchild Semiconductor Corporation Rev. A, June 2003 FQP9N50C/FQPF9N50C Typical Characteristics (Continued) 1.2 3.0 RDS(ON) , (Normalized) Drain-Source On-Resistance BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.5 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μ A 0.9 0.8 -100 -50 0 50 100 150 2.0 1.5 1.0 ※ Notes : 1. VGS = 10 V 2. ID = 4.5 A 0.5 0.0 -100 200 10 µ s 1 10 0 ※ Notes : -1 1 ms 10 ms 100 ms DC 0 10 ※ Notes : -1 10 o 1. TC = 25 C o 1. TC = 25 C o o 2. TJ = 150 C 3. Single Pulse 2. TJ = 150 C 3. Single Pulse -2 -2 10 200 100 µ s 100 µs 10 10 150 Operation in This Area is Limited by R DS(on) 10 ID, Drain Current [A] ID, Drain Current [A] 10 100 10 µs 1 ms 10 ms 100 ms DC 1 50 Figure 8. On-Resistance Variation vs Temperature 2 Operation in This Area is Limited by R DS(on) 2 0 o Figure 7. Breakdown Voltage Variation vs Temperature 10 -50 TJ, Junction Temperature [ C] o TJ, Junction Temperature [ C] 10 0 1 10 2 10 3 10 10 VDS, Drain-Source Voltage [V] 0 10 1 10 2 10 3 10 VDS, Drain-Source Voltage [V] Figure 9-1. Maximum Safe Operating Area for FQP9N50C Figure 9-2. Maximum Safe Operating Area for FQPF9N50C 10 ID, Drain Current [A] 8 6 4 2 0 25 50 75 100 125 150 TC, Case Temperature [℃] Figure 10. Maximum Drain Current vs Case Temperature ©2003 Fairchild Semiconductor Corporation Rev. A, June 2003 (Continued) 0 D = 0 .5 0 .2 10 ※ N o te s : 1 . Z θ J C( t ) = 0 . 9 3 ℃ / W M a x . 2 . D u ty F a c t o r , D = t 1 / t 2 3 . T J M - T C = P D M * Z θ J C( t ) 0 .1 -1 0 .0 5 0 .0 2 PDM 0 .0 1 θ JC (t), T h e rm a l R e s p o n s e 10 FQP9N50C/FQPF9N50C Typical Characteristics t1 Z s in g le p u ls e 10 t2 -2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ] D = 0 .5 10 0 0 .2 ※ N o te s : 1 . Z θ J C( t ) = 2 . 8 6 ℃ / W M a x . 2 . D u ty F a c t o r , D = t 1 / t 2 3 . T J M - T C = P D M * Z θ J C( t ) 0 .1 0 .0 5 10 -1 0 .0 2 PDM 0 .0 1 θ JC (t), T h e rm a l R e s p o n s e Figure 11-1. Transient Thermal Response Curve for FQP9N50C Z t1 t2 s in g le p u ls e 10 -2 10 -5 10 -4 10 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ] Figure 11-2. Transient Thermal Response Curve for FQPF9N50C ©2003 Fairchild Semiconductor Corporation Rev. A, June 2003 FQP9N50C/FQPF9N50C Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50KΩ Qg 200nF 12V 10V 300nF VDS VGS Qgs Qgd DUT 3mA Charge Resistive Switching Test Circuit & Waveforms VDS RL VDS 90% VDD VGS RG VGS DUT 10V 10% td(on) tr td(off) t on tf t off Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS BVDSS IAS ID RG VDD DUT 10V tp ©2003 Fairchild Semiconductor Corporation ID (t) VDS (t) VDD tp Time Rev. A, June 2003 FQP9N50C/FQPF9N50C Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2003 Fairchild Semiconductor Corporation Rev. A, June 2003 TO-220 4.50 ±0.20 2.80 ±0.10 (3.00) +0.10 1.30 –0.05 18.95MAX. (3.70) ø3.60 ±0.10 15.90 ±0.20 1.30 ±0.10 (8.70) (1.46) 9.20 ±0.20 (1.70) 9.90 ±0.20 1.52 ±0.10 0.80 ±0.10 2.54TYP [2.54 ±0.20] 10.08 ±0.30 (1.00) 13.08 ±0.20 ) (45° 1.27 ±0.10 +0.10 0.50 –0.05 2.40 ±0.20 2.54TYP [2.54 ±0.20] 10.00 ±0.20 Dimensions in Millimeters ©2003 Fairchild Semiconductor Corporation Rev. A, June 2003 FQP9N50C/FQPF9N50C Package Dimensions (Continued) 3.30 ±0.10 TO-220F 10.16 ±0.20 2.54 ±0.20 ø3.18 ±0.10 (7.00) (1.00x45°) 15.87 ±0.20 15.80 ±0.20 6.68 ±0.20 (0.70) 0.80 ±0.10 ) 0° (3 9.75 ±0.30 MAX1.47 #1 +0.10 0.50 –0.05 2.54TYP [2.54 ±0.20] 2.76 ±0.20 2.54TYP [2.54 ±0.20] 9.40 ±0.20 4.70 ±0.20 0.35 ±0.10 Dimensions in Millimeters ©2003 Fairchild Semiconductor Corporation Rev. A, June 2003 FQP9N50C/FQPF9N50C Package Dimensions TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT™ ActiveArray™ FACT Quiet series™ Bottomless™ FAST® FASTr™ CoolFET™ CROSSVOLT™ FRFET™ GlobalOptoisolator™ DOME™ EcoSPARK™ GTO™ E2CMOS™ HiSeC™ EnSigna™ I2C™ Across the board. Around the world.™ The Power Franchise™ Programmable Active Droop™ ImpliedDisconnect™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC® OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench® QFET™ QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ SILENT SWITCHER® SMART START™ SPM™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic® TruTranslation™ UHC™ UltraFET® VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component is any component of a life support which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be or (b) support or sustain life, or (c) whose failure to perform reasonably expected to cause the failure of the life support when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness. provided in the labeling, can be reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. ©2003 Fairchild Semiconductor Corporation Rev. I2