ACTEL RH1020

v3.1
Radiation-Hardened FPGAs
Features
•
•
•
•
•
•
•
•
Guaranteed Total Dose Radiation Capability
Low Single Event Upset Susceptibility
High Dose Rate Survivability
Latch-Up Immunity Guaranteed
QML Qualified Devices
Commercial Devices Available for Prototyping and
Pre-Production Requirements
Gate Capacities of 2,000 and 8,000 Gate Array
Gates
More Design Flexibility than Custom ASICs
•
•
•
•
•
•
•
•
•
•
Significantly Greater Densities than Discrete Logic
Devices
Replaces up to 200 TTL Packages
Design Library with over 500 Macro Functions
Single-Module Sequential Functions
Wide-Input Combinatorial Functions
Up to Two High-Speed, Low-Skew Clock Networks
Two In-Circuit Diagnostic Probe Pins Support
Speed Analysis to 50 MHz
Non-Volatile, User Programmable Devices
Fabricated in 0.8 µ Epitaxial Bulk CMOS Process
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer
Product Family Profile
Device
RH1020
RH1280
3,000
2,000
6,000
50
20
12,000
8,000
20,000
200
80
Logic Modules
S-Modules
C-Modules
547
0
547
1,232
624
608
Flip-Flops (Maximum)
273
998
22
13
186,000
35
15
750,000
User I/Os (Maximum)
69
140
Packages (by Pin Count)
Ceramic Quad Flat Pack (CQFP)
84
172
Capacity
System Gates
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Channel
PLICE Antifuse Elements
April 2005
© 2005 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
Radiation-Hardened FPGAs
Ordering Information
RH1280 –
CQ
172
V
Application
V = QML Qualified
Package Lead Count
Package Type
CQ = Ceramic Quad Flat Pack
Part Number
RH1280 = 8000 Gates
RH1020 = 2000 Gates
Figure 1-1 • Ordering Information
Ceramic Device Resources
CQFP 84-Pin
CQFP 172-Pin
RH1020
69
–
RH1280
–
140
ii
v3.1
Radiation-Hardened FPGAs
Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Radiation Survivability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
QML Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
RadHard Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
The RH1020 Logic Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
QML Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Radiation Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
Sequential Module Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Timing Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
84-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
172-Pin CQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
International Traffic in Arms Regulations (ITAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
v3.1
iii
Radiation-Hardened FPGAs
Radiation-Hardened FPGAs
General Description
line by expensive and destructive testing. QML also
ensures continuous process improvement, a focus on
enhanced quality and reliability, and shortened product
introduction and cycle time.
Actel Corporation, the leader in antifuse-based field
programmable gate arrays (FPGAs), offers fully
guaranteed RadHard versions of the A1280 and A1020
devices with gate densities of 8,000 and 2,000 gate array
gates, respectively.
Actel Corporation has also achieved QML certification.
All RH1020 and RH1280 devices will be shipped with a
"QML" marking, signifying that the devices and
processes have been reviewed and approved by DESC for
QML status.
The RH1020 and RH1280 devices are processed in 0.8 µ,
two-level metal epitaxial bulk CMOS technology. The
devices are based on the Actel patented channeled array
architecture, and employ Actel’s PLICE antifuse
technology. This architecture offers gate array flexibility,
high performance, and fast design implementation
through user programming.
Development Tool Support
The RadHard family of FPGAs is fully supported by both
Actel Libero® Integrated Design Environment (IDE) and
Designer FPGA development software. Actel Libero IDE is
a design management environment, seamlessly
integrating design tools while guiding the user through
the design flow, managing all design and log files, and
passing necessary design data among tools. Additionally,
Libero IDE allows users to integrate both schematic and
HDL synthesis into a single flow and verify the entire
design in a single environment. Libero IDE includes
Synplify® for Actel from Synplicity®, ViewDraw® for
Actel from Mentor Graphics®, ModelSim® HDL Simulator
from Mentor Graphics, WaveFormer Lite™ from
SynaptiCAD™, and Designer software from Actel. Refer
to the Libero IDE flow diagram for more information
(located on the Actel website).
Actel devices also provide unique on-chip diagnostic
probe capabilities, allowing convenient testing and
debugging. On-chip clock drivers with hard-wired
distribution networks provide efficient clock distribution
with minimum skew. A security fuse may be
programmed to disable all further programming, and to
protect the design from being copied or reverse
engineered.
The RH1020 and RH1280 are available as fully qualified
QML devices. Unlike traditional ASIC devices, the design
does not have to be finalized six months prior to
receiving the devices. Customers can make design
modifications and program new devices within hours.
These devices are fabricated, assembled, and tested at
the Lockheed-Martin Space and Electronics facility in
Manassas, Virginia on an optimized radiation-hardened
CMOS process.
Actel Designer software is a place-and-route tool and
provides a comprehensive suite of backend support tools
for FPGA development. The Designer software includes
timing-driven place-and-route, and a world-class
integrated static timing analyzer and constraints editor.
With the Designer software, a user can select and lock
package pins while only minimally impacting the results
of place-and-route. Additionally, the back-annotation
flow is compatible with all the major simulators and the
simulation results can be cross-probed with Silicon
Explorer II, Actel’s integrated verification and logic
analysis tool. Another tool included in the Designer
software is the ACTgen macro builder, which easily
creates popular and commonly used logic functions for
implementation in your schematic or HDL design. Actel's
Designer software is compatible with the most popular
FPGA design entry and verification tools from companies
such as Mentor Graphics, Synplicity, Synopsys, and
Cadence Design Systems. The Designer software is
available for both the Windows and UNIX operating
systems.
Radiation Survivability
In addition to all electrical limits, all radiation
characteristics are tested and guaranteed, reducing
overall system-level risks. With total dose hardness of
300 krad (Si), latch-up immunity, and a tested single
event upset (SEU) of less than 1x10–6 errors/bit-day, these
are the only RadHard, high-density field programmable
products available today.
QML Qualification
Lockheed Martin Space and Electronics in Manassas,
Virginia has achieved full QML certification, assuring that
quality management, procedures, processes, and controls
are in place from wafer fabrication through final test.
QML qualification means that quality is built into the
production process rather than verified at the end of the
v3.1
1-1
Radiation-Hardened FPGAs
Applications
where
S0 = A0 × B0
The RH1020 and RH1280 devices are targeted for use in
military and space applications subject to radiation
effects.
1. Accumulated Total Dose Effects
With the significant increase in Earth-orbiting
satellite launches and the ever-decreasing time-tolaunch design cycles, the RH1020 and RH1280 devices
offer the best combination of total dose radiation
hardness and quick design implementation necessary
for this increasingly competitive industry. In addition,
the high total dose capability allows the use of these
devices for deep space probes, which encounter other
planetary bodies where the total dose radiation
effects are more pronounced.
S1 = A1 + B1
A0
B0
S0
D00
D01
Y
D10
D11
A1
B1
S1
Figure 1-1 • C-Module Implementation
2. Single Event Effects (SEE)
Many space applications are more concerned with the
number of single event upsets and potential for latchup in space. The RH1020 and RH1280 devices are
latch-up immune, guaranteeing that no latch-up
failures will occur. Single event upsets can occur in
these devices as with all semiconductor products, but
the rate of upset is low, as shown in Table 1-2 on
page 1-6.
3. High Dose Rate Survivability
An additional radiation concern is high dose rate
survivability. Solar flares and sudden nuclear events
can cause immediate high levels of radiation. The
RadHard devices are appropriate for use in these
types of applications, including missile systems,
ground-based communication systems, and orbiting
satellites.
Flip-flops can also be created using two C-modules. The
single event upset (SEU) characteristics differ between an
S-module flip-flop and a flip-flop created using two
C-modules. For details see the Radiation Specifications
table on Table 1-2 on page 1-6 and the Design
Techniques for RadHard Field Programmable Gate Arrays
application note.
The RH1020 Logic Module
RadHard Architecture
The RH1020 and RH1280 architecture is composed of
fine-grained building blocks that produce fast and
efficient logic designs. All the devices are composed of
logic modules, routing resources, clock networks, and I/O
modules, which are the building blocks for fast logic
designs.
Logic Modules
RH1280 devices contain two types of logic modules,
combinatorial (C-modules) and sequential (S-modules).
RH1020 devices contain only C-modules.
The C-module, shown in Figure 1-1, implements the
following function:
Y = !S1 × !S0 × D00 + !S1 × S0 × D01 + S1 × !S0
× D10 + S1 × S0 × D11
EQ 1-1
1 -2
The S-module, shown in Figure 1-2 on page 1-3, is
designed to implement high-speed sequential functions
within a single logic module. The S-module implements
the same combinatorial logic function as the C-module
while adding a sequential element. The sequential
element can be configured as either a D-flip-flop or a
transparent latch. To increase flexibility, the S-module
register can be bypassed so it implements purely
combinatorial logic.
v3.1
The RH1020 logic module is an 8-input, one-output logic
circuit chosen for the wide range of functions it
implements and for its efficient use of interconnect
routing resources (Figure 1-3 on page 1-3).
The logic module can implement the four basic logic
functions (NAND, AND, OR, and NOR) in gates of two,
three, or four inputs. Each function may have many
versions, with different combinations of active-low
inputs. The logic module can also implement a variety of
D-latches, exclusivity functions, AND-ORs, and OR-ANDs.
No dedicated hardwired latches or flip-flops are required
in the array, since latches and flip-flops may be
constructed from logic modules wherever needed in the
application.
Radiation-Hardened FPGAs
D00
D01
Y
D10
D11
S1
D
S0
Q
D00
D01
OUT
D10
D11
S1
CLR
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
D
Y
S0
Q
OUT
GATE
Up to 7-Input Function Plus Latch
D00
D0
D01
Y
D1
S
D
Q
OUT
Y
OUT
D10
D11
S1
GATE
CLR
Up to 4-Input Function Plus Latch with Clear
S0
Up to 8-Input Function (same as C-Module)
Figure 1-2 • S-Module Implementation
EN
From Array
Q
D
PAD
G/CLK*
To Array
Q
D
G/CLK*
Note: *Can be configured as a Latch or D Flip-Flop (using
C-Module).
Figure 1-4 • I/O Module
Figure 1-3 • RH1020 Logic Module
I/O Modules
I/O modules provide the interface between the device
pins and the logic array. A variety of user functions,
determined by a library macro selection, can be
implemented in the I/O modules (refer to the Antifuse
Macro Library Guide for more information). I/O modules
contain a tristate buffer, and input and output latches
which can be configured for input, output, or
bidirectional pins (Figure 1-4).
v3.1
1-3
Radiation-Hardened FPGAs
RadHard devices contain flexible I/O structures in that each
output pin has a dedicated output enable control. The I/O
module can be used to latch input and/or output data,
providing a fast set-up time. In addition, the Actel Designer
software tools can build a D-flip-flop, using a C-module, to
register input and/or output signals.
Actel Designer development tools provide a design
library of I/O macros that can implement all I/O
configurations supported by the RadHard FPGAs.
Routing Structure
The RadHard device architecture uses vertical and
horizontal routing tracks to interconnect the various
logic and I/O modules. These routing tracks are metal
interconnects that may either be of continuous length or
broken into segments. Varying segment lengths allow
over 90 percent of the circuit interconnects to be made
with only two antifuse connections. Segments can be
joined together at the ends, using antifuses to increase
their length up to the full length of the track. All
interconnects can be accomplished with a maximum of
four antifuses.
Antifuse Structures
An antifuse is a "normally open" structure as opposed to
the normally closed fuse structure used in PROMs or
PALs. The use of antifuses to implement a programmable
logic device results in highly testable structures, as well
as efficient programming algorithms. The structure is
highly testable because there are no pre-existing
connections, enabling temporary connections to be
made using pass transistors. These temporary
connections can isolate individual antifuses to be
programmed, as well as isolate individual circuit
structures to be tested. This can be done both before and
after programming. For example, all metal tracks can be
tested for continuity and shorts between adjacent tracks,
and the functionality of all logic modules can be verified.
Segmented
Horizontal
Routing
Tracks
Logic
Modules
Antifuses
Horizontal Routing
Horizontal channels are located between the rows of
modules, and are composed of several routing tracks.
The horizontal routing tracks within the channel are
divided into one or more segments. The minimum
horizontal segment length is the width of a module-pair,
and the maximum horizontal segment length is the full
length of the channel. Any segment that spans more
than one-third the row length is considered a long
horizontal segment. A typical channel is shown in
Figure 1-5. Non-dedicated horizontal routing tracks are
used to route signal nets. Dedicated routing tracks are
used for the global clock networks and for power and
ground tie-off tracks.
Figure 1-5 • Routing Structure
Vertical Routing
Design Techniques for RadHard Field Programmable
Gate Arrays
Another set of routing tracks run vertically through the
module. There are three types of vertical tracks, input,
output, and long, that can be divided into one or more
segments. Each segment in an input track is dedicated to
the input of a particular module. Each segment in an
output track is dedicated to the output of a particular
module. Long segments are uncommitted and can be
assigned during routing. Each output segment spans
four channels (two above and two below), except near
the top and bottom of the array where edge effects
occur. Long vertical tracks contain either one or two
segments. An example of vertical routing tracks and
segments is shown in Figure 1-5.
1 -4
v3.1
Vertical Routing Tracks
Related Documents
Application Notes
http://www.actel.com/documents/Des_Tech_RH_AN.pdf
Analysis of SDI/DCLK Issue for RH1020 and RT1020
http://www.actel.com/documents/SDI_DCLK_AN.pdf
Simultaneously Switching Noise and Signal Integrity
http://www.actel.com/documents/SSN_AN.pdf
User’s Guides
Antifuse Macro Library Guide
http://www.actel.com/documents/libguide_UG.pdf
Radiation-Hardened FPGAs
QML Flow
Test Inspection
Method
Wafer Lot Acceptance
LMFS Procedure MAN-STC-Q014
Serialization
Required – 100%
Die Adhesion Test
2027 (Stud Pull)
Bond Pull Test
2011 (Wirebond)
Internal Visual
2010, Condition A
Temperature Cycle
1010, Condition C, 50 Cycles
Constant Acceleration
2001, Condition D or E, Y1 Orientation Only
Particle Impact Noise Detection (PIND)
2020, Condition A
X-Ray Radiography
2012
Pre Burn-In Electrical Parameters (T0)
Per Device Specification
Dynamic Burn-In
1015, 240 Hour Minimum, 125°C
Interim Electrical Parameters (T1)
Per Device Specification
Percent Defective Allowable (PDA)
LMFS Procedure MAN-STC-Q016
Static Burn-In
1015, 144 Hour Minimum, 125°C Minimum
Final Electrical Parameters (T2)
Per Device Specification
Percent Defective Allowable (PDA)
LMFS Procedure MAN-STC-Q016
Seal – Fine/Gross Leak
1014
External Visual (as required)
2009
Absolute Maximum Ratings
Table 1-1 • Free Air Temperature Range
Symbol
Parameter
Voltage2,3,4,5
VCC
DC Supply
VI
Input Voltage
VO
Output Voltage
IIO
TSTG
I/O Source/Sink
Current6
2
Storage Temperature
Limits
Units
–0.5 to +7.0
V
–0.5 to VCC +0.5
V
–0.5 to VCC +0.5
V
±20
mA
–65 to +150
°C
Notes:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
2. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Devices should not be operated
outside the recommended operating conditions.
3. VPP = VCC , except during device operation.
4. VSV = VCC , except during device operation.
5. VKS = GND , except during device operation.
6. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC +
0.5 V or less than GND – 0.5V, the internal protection diode will be forward-biased and can draw excessive current.
v3.1
1-5
Radiation-Hardened FPGAs
Recommended Operating Conditions
Parameter
Temperature Range1
Military
Units
–55 to +125
°C
±10
%VCC
2
Power Supply Tolerance
Notes:
1. Case temperature (TC) is used.
2. All power supplies must be in the recommended operating range.
Electrical Specifications
Symbol
Test Conditions
Min.
3.7
VOH1
(IOH = –4 mA)
1, 2, 3
VOL1
(IOL = 4 mA)
1, 2, 3
VIH
VIL
Input Transition Time
Limits
Group A
Subgroups
Max.
Units
V
0.4
V
1, 2, 3
2.2
VCC + 0.3
V
1, 2, 3
–0.3
0.8
V
—
500
ns
4
20
pF
tR, tF2
CIO, I/O Capacitance2
IIH, IIL
VIN = VCC or GND
VCC = 5.5 V
1, 2, 3
–10
10
µA
IOZL, IOZH
VOUT = VCC or GND
VCC = 5.5 V
1, 2, 3
–10
10
µA
25
mA
ICC Standby3
1, 2, 3
Notes:
1. Only one output tested at a time. VCC = min.
2. Not tested, for information only.
3. All outputs unloaded. All inputs = VCC or GND.
Radiation Specifications
Table 1-2 • Radiation Specifications1, 2
Symbol
RTD
Characteristics
Conditions
Min.
Total Dose
Max.
Units
300 k
Rad (Si)
Single Event Latch-Up
–55°C ≤ Tcase ≤ 125°C
0
Fails/Device-Day
SEU1
3
Single Event Upset for S-modules
–55°C ≤ Tcase ≤ 125°C
1E-6
Upsets/Bit-Day
SEU2
3
Single Event Upset for C-modules
–55°C ≤ Tcase ≤ 125°C
1E-7
Upsets/Bit-Day
SEU33
Single Event Fuse Rupture
–55°C ≤ Tcase ≤ 125°C
<1
FIT (Fails/Device/1E9 Hrs)
RNF
Neutron Fluence
SEL
>1 E+12
N/cm2
Notes:
1. Measured at room temperature unless otherwise stated.
2. Device electrical characteristics are guaranteed for post-irradiation levels at worst-case conditions.
3. 10% worst-case particle environment, geosynchronous orbit, 0.025" of aluminum shielding. Specification set using the CREME
code upset rate calculation method with a 2 µ epi thickness.
1 -6
v3.1
Radiation-Hardened FPGAs
Package Thermal Characteristics
The device junction to case thermal characteristics is θjc,
and the junction to ambient air characteristics is θja. The
thermal characteristics for θja are listed with
two different air flow rates, as shown in Table 1-3.
Maximum junction temperature is 150°C.
A sample calculation of the maximum power dissipation
for an 84-pin ceramic quad flat pack at commercial
temperature is shown in EQ 1-2.
150°C – 70°C
Max.
Junction Temperature ( °C ) – Max. Commercial Temperature ( °C )------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------= ------------------------------------ = 2.0 W
40°C/W
θ ja (°C/W)
EQ 1-2
Table 1-3 • Thermal Characteristics
θja
Pin Count
θjc
Still Air
1.0 m/s
200 ft. / min.
Ceramic Quad Flat Pack
84
2.0
40.0
33.0
30.0
°C/W
Ceramic Quad Flat Pack
172
2.0
28.0
23.1
21.0
°C/W
Package Type
2.5 m/s
500 ft. / min.
Units
Note: θjc for CQFP packages refers to the thermal resistance between the junction and the bottom of the package.
Power Dissipation
greater reduction in board-level power dissipation can
be achieved.
General Power Equation
The power due to standby current is typically a small
component of the overall power. Standby power is
calculated below for military, worst case conditions.
P = [ICCstandby + ICCactive] × VCC + IOL × VOL ×
N + IOH × (VCC – VOH) × M
ICC
EQ 1-3
where
ICCstandby is the current flowing when no inputs or
outputs are changing.
VCC
Power
25 mA 5.5 V
138 mW (max)
1 mA
5.5 mW (typ)
5.5 V
Active Power Components
ICCactive is the current flowing due to CMOS
switching.
Power dissipation in CMOS devices is usually dominated
by the active (dynamic) power dissipation. This
component is frequency-dependent and a function of
the logic and the external I/O. Active power dissipation
results from charging internal chip capacitances of the
interconnect, unprogrammed antifuses, module inputs,
and module outputs, plus external capacitance due to PC
board traces and load device inputs. An additional
component of the active power dissipation is the
totempole current in CMOS transistor pairs. The net
effect can be associated with an equivalent capacitance
that can be combined with frequency and voltage to
represent active power dissipation.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to
VOL.
M equals the number of outputs driving TTL loads to
VOH.
Accurate values for N and M are difficult to determine
because they depend on the family type, design details,
and on the system I/O. The power can be divided into
two components: static and active.
The power dissipated by a CMOS circuit can be expressed
by EQ 1-4:
Static Power Components
Power (uW) = CEQ × VCC2 × F
Actel FPGAs have small static power components that
result in lower power dissipation than PALs or PLDs. By
integrating multiple PALs/PLDs into one FPGA, an even
EQ 1-4
v3.1
1-7
Radiation-Hardened FPGAs
where
CEQ
VCC
F
= Equivalent capacitance in pF
= Power supply in volts (V)
= Switching frequency in MHz
Equivalent Capacitance
Equivalent capacitance is calculated by measuring ICC
active at a specified frequency and voltage for each
circuit component of interest. Measurements have been
made over a range of frequencies at a fixed value of VCC.
Equivalent capacitance is frequency-independent so the
results may be used over a wide range of operating
conditions. Equivalent capacitance values follow.
CEQ Values for Actel FPGAs
RH1020 RH1280
Modules (CEQM)
3.7
5.2
Input Buffers (CEQI)
22.1
11.6
Output Buffers (CEQO)
31.2
23.8
4.6
3.5
Routed Array Clock Buffer Loads (CEQCR)
Power = VCC2 × [(m × CEQM × fm)modules + (n × CEQI
× fn)inputs + (p × (CEQO+ CL) × fp)outputs + 0.5 ×
(q1 ×
CEQCR × fq1)routed_Clk1 + (r1 × fq1)routed_Clk1 + 0.5
×
(q2 × CEQCR × fq2)routed_Clk2 + (r2 ×
fq2)routed_Clk2]
where
q2
=
r1
=
r2
=
CEQM =
CEQI =
CEQO =
1 -8
Device Type
r1
routed_Clk1
r2
routed_Clk2
RH1020
RH1280
69
168
N/A
168
To determine the switching frequency for a design, you
must have a detailed understanding of the data input
values to the circuit. The following guidelines are meant
to represent worst-case scenarios, so they can be
generally used to predict the upper limits of power
dissipation. These guidelines are as follow:
Logic Modules (m)
= 80% of Modules
Inputs Switching (n)
= # Inputs/4
Outputs Switching (p)
= # Outputs/4
First Routed Array Clock Loads = 40% of
(q1)
Sequential
Modules
EQ 1-5
=
=
=
=
Fixed Capacitance Values for Actel FPGAs
(pF)
Determining Average Switching
Frequency
To calculate the active power dissipated from the
complete design, the switching frequency of each part of
the logic must be known. EQ 1-5 shows a piece-wise
linear summation over all components.
m
n
p
q1
CEQCR = Equivalent capacitance of routed array clock
in pF
CL
= Output lead capacitance in pF
fm
= Average logic module switching rate in MHz
fn
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
fp
= Average first routed array clock rate in MHz
fq1
fq2
= Average second routed array clock rate in
MHz (RH1280 only)
Number of logic modules switching at fm
Number of input buffers switching at fn
Number of output buffers switching at fp
Number of clock loads on the first routed
array clock
Number of clock loads on the second routed
array clock (RH1280 only)
Fixed capacitance due to first routed array
clock
Fixed capacitance due to second routed array
clock (RH1280 only)
Equivalent capacitance of logic modules in pF
Equivalent capacitance of input buffers in pF
Equivalent capacitance of output buffers in pF
Second Routed Array Clock Loads = 40% of
Sequential
(q2) (RH1280 only)
Modules
Load Capacitance (CL)
= 35 pF
Average Logic Module Switching = F/10
Rate (fm)
Average Input Switching Rate = F/5
(fn)
Average Output Switching Rate = F/10
(fp)
Average First Routed Array Clock = F
Rate (fq1)
Average Second Routed Array = F/2
Clock Rate (fq2) (RH1280 only)
v3.1
Radiation-Hardened FPGAs
Timing Models
Internal Delays
Input Delay
I/O Module
tINYL = 4.2 ns
tIRD2 = 1.9 ns
tIRD1 = 1.2 ns
tIRD4 = 4.2 ns
tIRD8 = 8.9 ns
ARRAY
CLOCK
tCKH = 7.6 ns
Predicted
Routing
Delays
I/O Module
Logic Module
tPD = 3.9 ns
tCO = 3.9 ns
Output Delay
tRD1 = 1.2 ns
tRD2 = 1.9 ns
tRD4 = 4.2 ns
tRD8 = 8.9 ns
tDLH = 9.1 ns
tENHZ = 13.5 ns
FO = 128
FMAX = 55 MHz
Figure 1-6 • RH1020 Timing Model
Input Delays
Output Delays
I/O Module
tINYL = 2.3 ns
tIRD2 = 7.5 ns†
Internal Delays
Combinatorial
Logic Module
I/O Module
Predicted
Routing
Delays
tDLH = 8.7 ns
D
Q
tRD1 = 2.7 ns
tRH2 = 3.4 ns
tRD4 = 4.8 ns
tRD8 = 9.0 ns
tPD = 4.7 ns
I/O Module
G
Combinatorial
Logic
included
in tSUD
ARRAY
CLOCKS
D
Q
D
Q
tRD1 = 2.7 ns
tENHZ = 9.7 ns
G
tSUD = 0.7 ns
tHD = 0.0 ns
tCKH = 11.2 ns
tDLH = 8.7 ns
Sequential
Logic Module
t
INH = 0.0 ns
t
INSU = 0.6 ns
t
INGL = 5.3 ns
tCO = 4.7 ns
tOUTH = 0.0 ns
tOUTSU = 0.6 ns
tGLH = 7.6 ns
FO = 384
FMAX = 95 MHz
tLCO = 17.7 ns (64 loads, pad-pad)
Note: † Input module predicted routing delay.
Figure 1-7 • RH1280 Timing Model
v3.1
1-9
Radiation-Hardened FPGAs
Parameter Measurement
Output Buffer Delays
E
D
In
50%
E
50%
VOH
PAD
VOL
1.5V
1.5V
PAD
PAD
TRIBUFF
To AC Test Loads (shown below)
E
50%
50%
V
1.5V
tENLZ
tENZL
tDHL
50%
VOH
1.5V
PAD
GND
10%
VOL
tDLH
50%
tENZH
90%
tENHZ
Figure 1-8 • Output Buffer Delays
AC Test Loads
Load 1
(Used to Measure Propagation Delay)
Load 2
(Used to Measure Rising/Falling Edges)
VCC
To the Output Under Test
GND
R to VCC for tPLZ / tPZL
R to GND for tPHZ / tPZH
R = 1 kΩ
35 pF
To the Output Under Test
35 pF
Figure 1-9 • AC Test Loads
Input Buffer Delays
S
A
B
PAD
Y
INBUF
S, A or B
50% 50%
Y
3V
PAD
0V
1.5V 1.5V
VC C
Y
GND
Y
tINYL
Figure 1-11 • Module Delays
Figure 1-10 • Input Buffer Delays
Module Delays
1 -1 0
v3.1
50%
50%
tPLH
50%
tPHL
50%
50%
tINYH
Y
tPHL
50%
tPLH
Radiation-Hardened FPGAs
Sequential Module Timing Characteristics
Flip-Flops and Latches
PRE
D
E
CLK
Y
CLR
(Positive Edge Triggered)
tHD
D1
tA
tWC LKA
tSUD
G, CLK
t
WCLKI
tSUENA
t
H EN A
E
tC O
Q
tR S
PRE, CLR
tWASYN
Note: D represents all data functions involving A, B, and S for multiplexed flip-flops.
Figure 1-12 • Flip-Flops and Latches
DATA
PAD
IBDL
G
CLK
PAD
CLKBUF
DATA
tINH
G
tINSU
tH EXT
CLK
tSU EXT
Figure 1-13 • Input Buffer Latches
v3.1
1-11
Radiation-Hardened FPGAs
D
PAD
OBDLHS
G
D
tOUTSU
G
tOUTH
Figure 1-14 • Output Buffer Latches
1 -1 2
v3.1
Radiation-Hardened FPGAs
Timing Characteristics
Table 1-4 • RH1020 Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C, RTD = 300 krad (Si))
Parameter
Description
Min.
Max.
Units
Logic Module Propagation Delays
tPD1
Single Module
3.9
ns
tPD2
Dual Module Macros
9.2
ns
tCO
Sequential Clk to Q
3.9
ns
tGO
Latch G to Q
3.9
ns
tRS
Flip-Flop (Latch) Reset to Q
3.9
ns
Logic Module Predicted Routing
Delays1
tRD1
FO=1 Routing Delay
1.2
ns
tRD2
FO=2 Routing Delay
1.9
ns
tRD3
FO=3 Routing Delay
2.8
ns
tRD4
FO=4 Routing Delay
4.2
ns
tRD8
FO=8 Routing Delay
8.9
ns
Logic Module Sequential Timing
2
tSUD
Flip-Flop (Latch) Data Input Set-Up
7.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
7.5
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
9.2
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
9.2
ns
tA
Flip-Flop Clock Input Period
19.2
ns
fMAX
Flip-Flop (Latch) Clock Frequency
50
MHz
4.2
ns
4.2
ns
Input Module Propagation Delays
tINYH
Pad to Y High
tINYL
Pad to Y Low
Input Module Predicted Routing
Delays1, 3
tIRD1
FO=1 Routing Delay
1.2
ns
tIRD2
FO=2 Routing Delay
1.9
ns
tIRD3
FO=3 Routing Delay
2.8
ns
tIRD4
FO=4 Routing Delay
4.2
ns
tIRD8
FO=8 Routing Delay
8.9
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
2. Set-up times assume fanout of 3. Further testing information can be obtained from the DirectTime Analyzer utility.
3. Optimization techniques may further reduce delays by 0 to 4 ns.
4. The hold time for the DFME1A macro may be greater than 0 ns. Use the Designer v3.0 (or later) Timer to check the hold time for
this macro.
v3.1
1-13
Radiation-Hardened FPGAs
Table 1-5 • RH1020 Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C, RTD = 300 krad (Si))
Parameter
Description
Min.
Max.
Units
Global Clock Network
tCKH
Input Low to High
FO = 16
FO = 128
6.6
7.6
ns
tCKL
Input High to Low
FO = 16
FO = 128
8.7
9.5
ns
tPWH
Minimum Pulse Width High
FO = 16
FO = 128
8.8
9.2
ns
tPWL
Minimum Pulse Width Low
FO = 16
FO = 128
1.6
2.4
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
tP
Minimum Period
FO = 16
FO = 128
fMAX
Maximum Frequency
FO = 16
FO = 128
1.6
2.5
17.9
19.2
ns
ns
55
50
MHz
TTL Output Module Timing1
tDLH
Data to Pad High
9.1
ns
tDHL
Data to Pad Low
10.2
ns
tENZH
Enable Pad Z to High
8.9
ns
tENZL
Enable Pad Z to Low
10.7
ns
tENHZ
Enable Pad High to Z
13.5
ns
tENLZ
Enable Pad Low to Z
12.2
ns
dTLH
Delta Low to High
0.08
ns/pF
dTHL
Delta High to Low
0.11
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
10.7
ns
tDHL
Data to Pad Low
8.7
ns
tENZH
Enable Pad Z to High
8.1
ns
tENZL
Enable Pad Z to Low
11.2
ns
tENHZ
Enable Pad High to Z
13.5
ns
tENLZ
Enable Pad Low to Z
12.2
ns
dTLH
Delta Low to High
0.14
ns/pF
dTHL
Delta High to Low
0.08
ns/pF
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Noise and Signal Integrity application note.
1 -1 4
v3.1
Radiation-Hardened FPGAs
Table 1-6 • RH1280 Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C, RTD = 300 krad (Si))
Parameter
Description
Min.
Max.
Units
1
Logic Module Propagation Delays
tPD1
Single Module
4.7
ns
tCO
Sequential Clk to Q
4.7
ns
tGO
Latch G to Q
4.7
ns
tRS
Flip-Flop (Latch) Reset to Q
4.7
ns
2
Logic Module Predicted Routing Delays
tRD1
FO=1 Routing Delay
2.7
ns
tRD2
FO=2 Routing Delay
3.4
ns
tRD3
FO=3 Routing Delay
4.1
ns
tRD4
FO=4 Routing Delay
4.8
ns
tRD8
FO=8 Routing Delay
9.0
ns
Sequential Timing Characteristics
3, 4
tSUD
Flip-Flop (Latch) Data Input Set-Up
0.7
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Set-Up
1.4
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
6.6
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
6.6
ns
tA
Flip-Flop Clock Input Period
13.5
ns
tINH
Input Buffer Latch Hold
0.0
ns
tINSU
Input Buffer Latch Set-Up
0.6
ns
tOUTH
Output Buffer Latch Hold
0.0
ns
tOUTSU
Output Buffer Latch Set-Up
0.6
ns
fMAX
Flip-Flop (Latch) Clock Frequency
95
MHz
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the DirectTime Analyzer utility.
4. Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal set-up (hold) time.
v3.1
1-15
Radiation-Hardened FPGAs
Table 1-7 • RH1280 Timing Characteristics
(Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C, RTD = 300 krad (Si))
Parameter
Description
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad to Y High
1.9
ns
tINYL
Pad to Y Low
2.3
ns
tINGH
G to Y High
4.1
ns
tINGL
G to Y Low
5.3
ns
Input Module Predicted Routing Delays*
tIRD1
FO=1 Routing Delay
6.8
ns
tIRD2
FO=2 Routing Delay
7.5
ns
tIRD3
FO=3 Routing Delay
8.2
ns
tIRD4
FO=4 Routing Delay
8.9
ns
tIRD8
FO=8 Routing Delay
11.7
ns
Global Clock Network
tCKH
Input Low to High
FO = 32
FO = 384
9.6
11.2
ns
tCKL
Input High to Low
FO = 32
FO = 384
9.6
11.2
ns
tPWH
Minimum Pulse Width High
FO = 32
FO = 384
5.8
6.2
ns
tPWL
Minimum Pulse Width Low
FO = 32
FO = 384
5.8
6.2
ns
tCKSW
Maximum Skew
FO = 32
FO = 384
tSUEXT
Input Latch External Set-Up
FO = 32
FO = 384
0.0
0.0
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 384
4.6
5.8
ns
tP
Minimum Period
FO = 32
FO = 384
11.8
13.0
ns
fMAX
Maximum Frequency
FO = 32
FO = 384
1.1
1.1
105
95
ns
MHz
Note: *Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may
further reduce delays by 0 to 4 ns.
1 -1 6
v3.1
Radiation-Hardened FPGAs
Table 1-8 • RH1280 Timing Characteristics
(Worst-Case Military Conditions, V CC = 4.5 V, T J = 1 25°C, RT D = 30 0 krad (S i))
Parameter
Description
TTL Output Module Timing
Min.
Max.
Units
1
tDLH
Data to Pad High
6.8
ns
tDHL
Data to Pad Low
7.6
ns
tENZH
Enable Pad Z to High
6.8
ns
tENZL
Enable Pad Z to Low
7.6
ns
tENHZ
Enable Pad High to Z
9.7
ns
tENLZ
Enable Pad Low to Z
9.7
ns
tGLH
G to Pad High
7.6
ns
tGHL
G to Pad Low
8.9
ns
tLCO
I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading
17.7
ns
tACO
Array Clock-Out (Pad-to-Pad), 64 Clock Loading
25.0
ns
dTLH
Capacitive Loading, Low to High
0.07
ns/pF
dTHL
Capacitive Loading, High to Low
0.09
ns/pF
1
CMOS Output Module Timing
tDLH
Data to Pad High
8.7
ns
tDHL
Data to Pad Low
6.4
ns
tENZH
Enable Pad Z to High
6.8
ns
tENZL
Enable Pad Z to Low
7.6
ns
tENHZ
Enable Pad High to Z
9.7
ns
tENLZ
Enable Pad Low to Z
9.7
ns
tGLH
G to Pad High
7.6
ns
tGHL
G to Pad Low
8.9
ns
tLCO
I/O Latch Clock-Out (Pad-to-Pad), 64 Clock Loading
20.1
ns
tACO
Array Clock-Out (Pad-to-Pad), 64 Clock Loading
29.5
ns
dTLH
Capacitive Loading, Low to High
0.09
ns/pF
dTHL
Capacitive Loading, High to Low
0.08
ns/pF
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Noise and Signal Integrity application note.
v3.1
1-17
Radiation-Hardened FPGAs
Pin Description
CLKA
Clock A (Input)
NC
TTL clock input for clock distribution networks. The clock
input is buffered prior to clocking the logic modules. This
pin can also be used as an I/O.
CLKB
Clock B (Input)
Not applicable for RH1020. TTL clock input for clock
distribution networks. The clock input is buffered prior
to clocking the logic modules. This pin can also be used
as an I/O.
DCLK1
Diagnostic Clock (Input)
TTL clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is
LOW. If the Program fuse is not programmed and DCLK is
undefined, it is configured as an inactive input. In this
case, tie the DCLK pin to ground. If the Program fuse is
programmed and DCLK is undefined, it will become an
active LOW output.The Program fuse must be
programmed if the DCLK pin is used as an output or a
bidirectional pin.
GND
Ground
LOW supply voltage.
I/O
Input/Output (Input, Output)
The I/O pin functions as an input, output, three-state, or
bidirectional buffer. Input and output levels are
compatible with standard TTL and CMOS specifications.
Unused I/O pins are automatically driven LOW by the
Designer software.
MODE
Mode (Input)
The MODE pin controls the use of multi-function pins
(DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the
special functions are active. When the MODE pin is LOW,
the pins function as I/Os. To provide debugging
capability, the MODE pin should be terminated to GND
through a 10 kΩ resistor so that the MODE pin can be
pulled HIGH when required.
No Connection
This pin is not connected to circuitry within the device.
PRA, I/O
Probe A (Output)
The Probe A pin is used to output data from any userdefined design node within the device. This independent
diagnostic pin can be used in conjunction with the Probe
B pin to allow real-time diagnostic output of any signal
path within the device. The Probe A pin can be used as a
user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled
to protect programmed design confidentiality. PRA is
accessible when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.
PRB, I/O
Probe B (Output)
The Probe B pin is used to output data from any userdefined design node within the device. This independent
diagnostic pin can be used in conjunction with the Probe
A pin to allow real-time diagnostic output of any signal
path within the device. The Probe B pin can be used as a
user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled
to protect programmed design confidentiality. PRB is
accessible when the MODE pin is HIGH. This pin functions
as an I/O when the MODE pin is LOW.
SDI1
Serial Data Input (Input)
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
If the Program fuse is not programmed and SDI is
undefined, it is configured as an inactive input. In this
case, tie the SDI pin to ground. If the Program fuse is
programmed and SDI is undefined, it will become an
active LOW output.The Program fuse must be
programmed if the SDI pin is used as an output or a
bidirectional pin.
VCC
5.0V Supply Voltage
HIGH supply voltage.
1. Please refer to the Actel Technical Brief Analysis of SDI/DCLK Issue for RH1020 and RT1020.
1 -1 8
v3.1
Radiation-Hardened FPGAs
Package Pin Assignments
84-Pin CQFP
Pin #1
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
84-Pin
CQFP
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Figure 2-1 • 84-Pin CQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v3.1
2-1
Radiation-Hardened FPGAs
84-Pin CQFP
84-Pin CQFP
84-Pin CQFP
Pin
Number
RH1020
Function
Pin
Number
RH1020
Function
Pin
Number
RH1020
Function
1
NC
36
I/O
71
GND
2
I/O
37
I/O
72
I/O
3
I/O
38
I/O
73
I/O
4
I/O
39
I/O
74
I/O
5
I/O
40
I/O
75
I/O
6
I/O
41
I/O
76
I/O
7
GND
42
I/O
77
VCC
8
GND
43
I/O
78
I/O
9
I/O
44
I/O
79
I/O
10
I/O
45
I/O
80
I/O
11
I/O
46
I/O
81
I/O
12
I/O
47
I/O
82
I/O
13
I/O
48
I/O
83
I/O
14
VCC
49
GND
84
I/O
15
VCC
50
GND
16
I/O
51
I/O
17
I/O
52
I/O
18
I/O
53
CLKA, I/O
19
I/O
54
I/O
20
I/O
55
MODE
21
I/O
56
VCC
22
VCC
57
VCC
23
I/O
58
I/O
24
I/O
59
I/O
25
I/O
60
I/O
26
I/O
61
SDI, I/O
27
I/O
62
DCLK, I/O
28
I/O
63
PRA, I/O
29
GND
64
PRB, I/O
30
I/O
65
I/O
31
I/O
66
I/O
32
I/O
67
I/O
33
I/O
68
I/O
34
I/O
69
I/O
35
VCC
70
I/O
2 -2
v3.1
Radiation-Hardened FPGAs
172-Pin CQFP
172 171 170 169 168 167 166 165 164
137 136 135 134 133 132 131 130
Pin #1
Index
1
129
2
128
3
127
4
126
5
125
6
124
7
123
8
122
172-Pin
CQFP
35
95
36
94
37
93
38
92
39
91
40
90
41
89
42
88
43
87
44 45 46 47 48 49 50 51 52
79 80 81 82 83 84 85 86
Figure 2-2 • 172-Pin CQFP (Top View)
Note
For Package Manufacturing and Environmental information, visit the Package Resource center at
http://www.actel.com/products/rescenter/package/index.html.
v3.1
2-3
Radiation-Hardened FPGAs
172-Pin CQFP
172-Pin CQFP
172-Pin CQFP
172-Pin CQFP
Pin Number
RH1280A
Function
Pin Number
RH1280A
Function
Pin Number
RH1280A
Function
Pin Number
RH1280A
Function
1
MODE
36
I/O
71
I/O
106
GND
2
I/O
37
GND
72
I/O
107
VCC
3
I/O
38
I/O
73
I/O
108
GND
4
I/O
39
I/O
74
I/O
109
VCC
5
I/O
40
I/O
75
GND
110
VCC
6
I/O
41
I/O
76
I/O
111
I/O
7
GND
42
I/O
77
I/O
112
I/O
8
I/O
43
I/O
78
I/O
113
VCC
9
I/O
44
I/O
79
I/O
114
I/O
10
I/O
45
I/O
80
VCC
115
I/O
11
I/O
46
I/O
81
I/O
116
I/O
12
VCC
47
I/O
82
I/O
117
I/O
13
I/O
48
I/O
83
I/O
118
GND
14
I/O
49
I/O
84
I/O
119
I/O
15
I/O
50
VCC
85
I/O
120
I/O
16
I/O
51
I/O
86
I/O
121
I/O
17
GND
52
I/O
87
I/O
122
I/O
18
I/O
53
I/O
88
I/O
123
GND
19
I/O
54
I/O
89
I/O
124
I/O
20
I/O
55
GND
90
I/O
125
I/O
21
I/O
56
I/O
91
I/O
126
I/O
22
GND
57
I/O
92
I/O
127
I/O
23
VCC
58
I/O
93
I/O
128
I/O
24
VCC
59
I/O
94
I/O
129
I/O
25
I/O
60
I/O
95
I/O
130
I/O
26
I/O
61
I/O
96
I/O
131
SDI, I/O
27
VCC
62
I/O
97
I/O
132
I/O
28
I/O
63
I/O
98
GND
133
I/O
29
I/O
64
I/O
99
I/O
134
I/O
30
I/O
65
GND
100
I/O
135
I/O
31
I/O
66
VCC
101
I/O
136
VCC
32
GND
67
I/O
102
I/O
137
I/O
33
I/O
68
I/O
103
GND
138
I/O
34
I/O
69
I/O
104
I/O
139
I/O
35
I/O
70
I/O
105
I/O
140
I/O
2 -4
v3.1
Radiation-Hardened FPGAs
172-Pin CQFP
Pin Number
RH1280A
Function
141
GND
142
I/O
143
I/O
144
I/O
145
I/O
146
I/O
147
I/O
148
PRA, I/O
149
I/O
150
CLKA, I/O
151
VCC
152
GND
153
I/O
154
CLKB, I/O
155
I/O
156
PRB, I/O
157
I/O
158
I/O
159
I/O
160
I/O
161
GND
162
I/O
163
I/O
164
I/O
165
I/O
166
VCC
167
I/O
168
I/O
169
I/O
170
I/O
171
DCLK, I/O
172
I/O
v3.1
2-5
Radiation-Hardened FPGAs
Datasheet Information
List of Changes
The following table lists critical changes that were made in the current version of the document.
Previous Version Changes in Current Version (v3 . 1)
v3.0
Page
"Development Tool Support" section was updated.
1-1
Table 1-1 was updated.
1-5
Table 1-2 was updated.
1-6
Table 1-3 was updated.
1-7
The "DCLK Diagnostic Clock (Input)" section was updated.
1-18
The "SDI1 Serial Data Input (Input)" section was updated.
1-18
Datasheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet
Supplement." The definitions of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product
information. This brief gives an overview of specific device and family information.
Advanced
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and
for specifications that do not differ between the two families.
International Traffic in Arms Regulations (ITAR)
The product described in this datasheet are subject to the International Traffic in Arms Regulations (ITAR). They
require an approved export license prior to export from the United States. An export includes release of product or
disclosure of technology to a foreign national inside or outside the United States.
v3.1
3-1
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
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