VISHAY DG641DY

DG641, DG642, DG643
Vishay Siliconix
Low On-Resistance Wideband/Video Switches
DESCRIPTION
FEATURES
The DG641, DG642, DG643 are high performance
monolithic video switches designed for switching wide
bandwidth analog and digital signals. DG641 is a quad
SPST, DG642 is a single SPDT, and DG643 is a dual SPDT
function. These devices have exceptionally low
on-resistances (5 typ-DG642), low capacitance and high
current handling capability.
•
•
•
•
•
•
Wide bandwidth: 500 MHz
Low crosstalk at 5 MHz: - 85 dB
Low RDS(on): 5 , DG642
TTL logic compatible
Fast switching: tON 50 ns
Single supply compatibility
• High current: 100 mA, DG642
BENEFITS
To achieve TTL compatibility, low channel capacitances and
fast switching times, the DG641, DG642, DG643 are built on
the Vishay Siliconix proprietary D/CMOS process. Each
switch conducts equally well in both directions when on, and
blocks up to 14 Vp-p when off. An epitaxial layer prevents
latchup.
•
•
•
•
•
•
High precision
Improved frequency response
Low insertion loss
Improved system performance
Reduced board space
Low power consumption
APPLICATIONS
•
•
•
•
•
•
•
•
RF and video switching
RGB switching
Video routing
Cellular communications
ATE
Radar/FLIR systems
Satellite receivers
Programmable filters
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Dual-In-Line and SOIC
IN1
Dual-In-Line and SOIC
16 IN2
1
IN1
1
16
IN2
D1
2
15
D2
Dual-In-Line and SOIC
D1
2
15 D2
S1
3
14 S2
S1
1
8
IN
GND
3
14
GND
V-
4
13 V+
D1
2
7
V+
S1
4
13
S2
V-
3
6
D2
V-
5
12
V+
GND
4
5
S2
S4
6
11
S3
GND
7
10
GND
D4
8
9
D3
DG641
GND
5
12 GND
S4
6
11 S3
D4
7
10 D3
IN4
8
9
DG642
Top View
IN3
DG643
Top View
Top View
TRUTH TABLE (DG641)
Logic
0
1
Switch
OFF
ON
Logic “0” 0.8 V
Logic “1”  2.4 V
Document Number: 70058
S11-0154-Rev. F, 31-Jan-11
TRUTH TABLE (DG642)
Logic
0
1
Logic “0” 0.8 V
Logic “1”  2.4 V
SW1
OFF
ON
SW2
ON
OFF
TRUTH TABLE (DG643)
Logic
0
1
SW1, SW2
OFF
ON
SW3, SW4
ON
OFF
Logic “0” 0.8 V
Logic “1”2.4 V
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1
DG641, DG642, DG643
Vishay Siliconix
ORDERING INFORMATION
Temp. Range
Package
Part Number
DG641
- 40 °C to 85 °C
16-Pin Plastic DIP
DG641DJ
16-Pin Narrow SOIC
DG641DY
DG642
- 40 °C to 85 °C
8-Pin Plastic DIP
DG642DJ
8-Pin Narrow SOIC
DG642DY
DG643
- 40 °C to 85 °C
16-Pin Plastic DIP
DG643DJ
16-Pin Narrow SOIC
DG643DY
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Parameter
Symbol
V+ to V-
Limit
Unit
- 0.3 to 21
V+ to GND
- 0.3 to 21
V- to GND
- 19 to + 0.3
(V-) - 0.3 V to (V+) + 0.3 V
or 20 mA, whichever occurs first
(V-) - 0.3 V to (V+) + 14 V
or 20 mA, whichever occurs first
20
Digital Inputs
VS, VD
Continuous Current (Any terminal except S or D)
Continuous Current S or D
Current, S or D
(Pulsed at 1 ms, 10 % duty cycle max)
DG641, DG643
75
DG642
100
DG641, DG643
200
DG642
mA
300
Storage Temperature
- 65 to 125
Power Dissipation (Package)b
V
8-Pin Plastic DIP and Narrow SOICc
300
16-Pin Plastic DIPd
470
16-Pin Narrow SOICe
600
°C
mW
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC board.
c. Derate 7.6 mW/°C above 75 °C.
d. Derate 6 mW/°C above 75 °C.
e. Derate 80 mW/°C above 75 °C.
SCHEMATIC DIAGRAM (Typical Channel)
V+
GND
5V
Reg
S
IN
D
V-
Figure 1.
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Document Number: 70058
S11-0154-Rev. F, 31-Jan-11
DG641, DG642, DG643
Vishay Siliconix
SPECIFICATIONS (for DG641 and DG643)
Parameter
Analog Switch
Symbol
Analog Signal Ranged
VANALOG
Drain-Source On-Resistance
RDS(on) Match
RDS(on)
RDS(on)
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V- = - 3 V
VINH = 2.4 V, VINL = 0.8 Ve
Limits
- 40 °C to 85 °C
Temp.a
Min.b
V- = - 5 V, V+ = 12 V
Full
-5
8
V- = GND V, V+ = 12 V
Full
Room
Full
Room
Room
Full
Room
Full
Room
Full
0
- 10
- 100
- 10
- 100
- 10
- 100
8
15
20
2
10
100
10
100
10
100
2.4
IS = - 10 mA, VD = 0 V
Source Off Leakage Current
IS(off)
VS = 0 V, VD = 10 V
Drain Off Leakage Current
ID(off)
VS = 10 V, VD = 0 V
Channel On Leakage Current
ID(on)
VS = V D = 0 V
Typ.c
8
1
- 0.02
- 0.02
- 0.1
Max.b
Unit
V

nA
Digital Control
Input Voltage High
VINH
Full
Input Voltage Low
VINL
IIN
VIN = GND or V+
Full
Room
Full
On State Input Capacitanced
CS(on)
VS = V D = 0 V
Off State Output Capacitanced
CS(off)
VS = 0 V
Off State Input Capacitanced
CD(off)
BW
Input Current
0.05
0.8
1
20
Room
10
20
Room
4
12
VD = 0 V
Room
4
12
RL = 50 see figure 6
Room
Room
Full
Room
Full
500
50
-1
- 20
V
µA
Dynamic Characteristics
Bandwidth
Turn On Time
tON
Turn Off Time
tOFF
Charge Injection
Q
Off Isolation
OIRR
All Hostie Crosstalk
XTALK
RL = 1 kCL = 35 pF
see figure 2
28
CL = 1000 pF, VD = 0 V
see figure 3
RIN = 75 RL = 75 
f = 5 MHz, see figure 4
RIN = 10 , RL = 75 
f = 5 MHz, see figure 5
Room
- 19
Room
- 60
Room
- 87
3.5
VIN = 0 V or VIN = 5 V
Room
Full
Room
Full
pF
MHz
70
140
50
85
ns
pC
dB
Power Supplies
Positive Supply Current
I+
Negative Supply Current
I-
-6
-9
6
9
-3
mA
Notes:
a. Room = 25 °C, Full = as determined by the operating temperature suffix.
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
d. Guaranteed by design, not subject to production test.
e. VIN = input voltage to perform proper function.
Document Number: 70058
S11-0154-Rev. F, 31-Jan-11
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DG641, DG642, DG643
Vishay Siliconix
SPECIFICATIONS (for DG642)
Parameter
Analog Switch
Symbol
Analog Signal Ranged
VANALOG
Drain-Source On-Resistance
RDS(on) Match
RDS(on)
RDS(on)
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V- = - 3 V
VINH = 2.4 V, VINL = 0.8 Ve
Limits
- 40 °C to 85 °C
Temp.a
Min.b
V- = - 5 V, V+ = 12 V
Full
-5
8
V- = GND V, V+ = 12 V
Full
Room
Full
Room
Room
Full
Room
Full
Room
Full
0
- 10
- 200
- 10
- 200
- 10
- 200
8
8
9
1
10
200
10
200
10
200
2.4
IS = - 10 mA, VD = 0 V
Source Off Leakage Current
IS(off)
VS = 0 V, VD = 10 V
Drain Off Leakage Current
ID(off)
VS = 10 V, VD = 0 V
Channel On Leakage Current
ID(on)
VS = V D = 0 V
Typ.c
5
0.5
- 0.04
- 0.04
- 0.2
Max.b
Unit
V

nA
Digital Control
Input Voltage High
VINH
Full
Input Voltage Low
VINL
Input Current
IIN
VIN = GND or V+
Full
Room
Full
-1
- 20
0.05
0.8
1
20
40
V
µA
Dynamic Characteristics
On State Input Capacitanced
CS(on)
VS = V D = 0 V
Room
19
Off State Input Capacitanced
CS(off)
VD = 0 V
Room
8
20
Off State Output Capacitanced
CD(off)
VS = 0 V
Room
8
20
BW
RL = 50 see figure 6
Room
Room
Full
Room
Full
500
60
Bandwidth
Turn On Time
tON
Turn Off Time
tOFF
Charge Injection
Q
Off Isolation
All Hostie Crosstalk
XTALK(AH)
RL = 1 kCL = 35 pF
see figure 2
40
CL = 1000 pF, VD = 0 V
see figure 3
RIN = 75 RL = 75 
f = 5 MHz, see figure 4
RIN = 10 , RL = 75 
f = 5 MHz, see figure 5
Room
- 40
Room
- 63
Room
- 85
3.5
VIN = 0 V or VIN = 5 V
Room
Full
Room
Full
pF
MHz
100
160
60
100
ns
pC
dB
Power Supplies
Positive Supply Current
I+
Negative Supply Current
I-
-6
-9
6
9
-3
mA
Notes:
a. Room = 25 °C, Full = as determined by the operating temperature suffix.
b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. Guaranteed by design, not subject to production test.
e. VIN = input voltage to perform proper function.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 70058
S11-0154-Rev. F, 31-Jan-11
DG641, DG642, DG643
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
100 nA
6
5
10 nA
4
I+
I S(off)
2
1
I D(off) ,
Current (mA)
3
IGND
0
1 nA
100 pA
-1
10 pA
-2
I-
-3
1 pA
-4
-5
- 55
- 35
- 15
5
25
45
65
85 105
0.1 pA
- 55
125
0
- 25
25
Temperature (°C)
75
100
125
9
11
Leakages vs. Temperature
Supply Current vs. Temperature
20
40
V+ = 15 V
V- = - 3 V
R DS(on) - Drain-Source On-Resistance ()
R DS(on) - Drain-Source On-Resistance ()
50
Temperature (°C)
30
125 °C
20
25 °C
- 55 °C
10
V+ = 15 V
V- = - 3 V
15
125 °C
10
25 °C
- 55 °C
5
0
0
-3
-1
1
3
5
7
9
-3
11
-1
1
3
5
7
VD - Drain Voltage (V)
VD - Drain V oltage (V)
DG641, DG643
RDS(on) vs. Drain Voltage
DG642
RDS(on) vs. Drain Voltage
120
22
20
100
V+ = 15 V, V- = - 15 V
VL = 5 V, V IN = 3 V Pulse
tON
t ON, t OFF (ns)
C (pF)
18
16
14
DG642
12
80
tOFF
60
40
10
20
DG641, DG643
8
6
0
2
4
6
8
(VD) - (V-)
On Capacitance
Document Number: 70058
S11-0154-Rev. F, 31-Jan-11
10
12
0
- 55 - 40 - 20
0
20
40
60
80
100
120
Temperature (°C)
Off Isolation
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DG641, DG642, DG643
Vishay Siliconix
TYPICAL CHARACTERISTICS (TA = 25 °C, unless otherwise noted)
140
80
120
100
tON
V- = 0 V
VL = 5 V
VIN = 3 V
DG419
Source 1
80
(dB)
t ON, t OFF (ns)
70
DG417, DG418, DG419
Source 2
60
60
40
50
tOFF
V+ = 15 V
V- = - 15 V
VL = 5 V
20
0
40
± 10
± 11
± 12
± 13
± 14
± 15
± 16
100
10 k
1k
Supply Voltage (V)
100 k
1M
10 M
100 M
f - Frequency (Hz)
All Hostile Crosstalk
Charge Injection vs. VD
90
20
80
60
t (ns)
tON
50
40
30
tOFF
20
18
V+ - Positive Supply Voltage (V)
70
16
Operating
Voltage
Area
14
12
10
0
- 55
- 25
0
25
50
75
100
10
125
0
-1
-2
Temperature (°C)
-3
-4
-5
-6
V- - Negative Supply (V)
Switching Times vs. Temperature
Operating Supply Voltage Range
TEST CIRCUITS
+ 15 V
3V
tr < 20 ns
tf < 20 ns
3V
V+
Logic
Input
D
S
50 %
VO
IN
3V
GND
V-
RL
1 k
CL
35 pF
90 %
Switch
Output
90 %
0
tON
-3V
tOFF
Figure 2. Switching Time
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Document Number: 70058
S11-0154-Rev. F, 31-Jan-11
DG641, DG642, DG643
Vishay Siliconix
TEST CIRCUITS
+ 15 V
Rg
S
D
VO
IN
Vg
VO
VO
V+
CL
1000 pF
3V
INX
ON
ON
OFF
V-
GND
V O = measured voltage error due to charge injection
The charge injection in coulombs is Q = CL x VO
-3V
Figure 3. Charge Injection
+ 15 V
C
V+
S
VS
D
VO
Rg = 50 
RL
IN
0 V, 2.4 V
GND
V-
C
-3V
Off Isolation = 20 log
VS
VO
Figure 4. Off Isolation
DG641
RIN
10 
DG642
S1
D1
S2
D2
S3
D3
S4
VOUT
RL
75 
RIN
10 
D1
VOUT
S2
D2
RL
75 
RL
RL
D4
RL
Signal
Generator
75 
RL
Signal
Generator
75 
S1
V
"0"
(b)
V
"1"
XTALK(AH) = 20 log10
(a)
VOUT
V
Figure 5. All Hostile Crosstalk - XTALK(AH)
Document Number: 70058
S11-0154-Rev. F, 31-Jan-11
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7
DG641, DG642, DG643
Vishay Siliconix
TEST CIRCUITS
+ 15 V
V+
S
Signal
Generator
50 
D
VOUT
V-
RL
50 
-3V
Figure 6. Bandwidth
APPLICATIONS
2.
The value of on capacitance [CS(on)] may be reduced.
A property known as ‘the body-effect’ on the DMOS
switch devices causes various parametric effects to
occur. One of these effects is the reduction in CS(on)
for an increasing V body-source. Note however that
to increase V- normally requires V+ to be reduced
(since V+ to V- = 21 V max.). A reduction in V+
causes an increase in rDS(on), hence a compromise
has to be achieved. It is also useful to note that tests
indicate that optimum video linearity performance
(e.g., differential phase and gain) occurs when V- is
around - 3 V.
3.
V- eliminates the need to bias the analog signal using
potential dividers and large coupling capacitors.
Device Description
The DG641, DG642, DG643 switches offer true bidirectional
switching of high frequency analog or digital signals with
minimum signal crosstalk, low insertion loss, and negligible
non-linearity distortion and group delay.
Built on the Siliconix D/CMOS process, these switches
provide excellent off-isolation with a bandwidth of around
500 MHz. The silicon-gate D/CMOS processing also yields
fast switching speeds.
An on-chip regulator circuit maintains TTL input compatibility
over the whole operating supply voltage range shown,
easing control logic interfacing.
Circuit layout is facilitated by the interchangeability of source
and drain terminals.
Frequency Response
A single switch on-channel exhibits both resistance [RDS(on)]
and capacitance [CS(on)]. This RC combination has an
attenuation effect on the analog signal - which is frequency
dependent (like an RC low-pass filter). The - 3 dB bandwidth
of the DG641, DG642, DG643 is typically 500 MHz (into
50 ).
Power Supplies
Power supply flexibility is a useful feature of the DG641,
DG642, DG643 series. It can be operated from a single
positive supply (V+) if required (V- connected to ground).
Decoupling
It is an established rf design practice to incorporate sufficient
bypass capacitors in the circuit to decouple the power
supplies to all active devices in the circuit. The dynamic
performance of the DG641, DG642, DG643 series is
adversely affected by poor decoupling of power supply pins.
Also, of even more significance, since the substrate of the
device is connected to the negative supply, adequate
decoupling of this pin is essential. Suitable decoupling
capacitors are 1- to 10 µF tantalum bead, plus 10- to 100-nF
ceramic or polyester.
Rules:
1.
Note that the analog signal must not exceed V- by more than
- 0.3 V to prevent forward biasing the substrate p-n junction.
The use of a V- supply has a number of advantages:
Decoupling capacitors should be incorporated on all
power supply pins (V+, V-). (see figure 7).
2.
They should be mounted as close as possible to the
device pins.
1.
3.
Capacitors should be of a suitable type with good high
frequency characteristics - tantalum bead and/or
ceramic disc types are adequate.
It allows flexibility in analog signal handling, i.e., with
V- = - 5 V and V+ = 12 V; up to ± 5 V ac signals can
be controlled.
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Document Number: 70058
S11-0154-Rev. F, 31-Jan-11
DG641, DG642, DG643
Vishay Siliconix
APPLICATIONS
Board Layout
+ 15 V
PCB layout rules for good high frequency performance must
also be observed to achieve the performance boasted by
these analog switches. Some tips for minimizing stray effects
are:
+
C1
C2
V+
S1
S2
D1
Use extensive ground planes on double sided PCB,
separating adjacent signal paths. Multilayer PCB is
even better.
2.
Keep signal paths as short as practically possible,
with all channel paths of near equal length.
3.
Careful arrangement of ground connections is also
very important. Star connected system grounds
eliminate signal current, flowing through ground path
parasitic resistance, from coupling between
channels.
D2
DG64X
S3
1.
D3
S4
D4
GNDs
V-
C1
C1 = 10 µF Tantalum
C2 = 0.1 µF Ceramic
C2
+
-3V
Figure 7. Supply Decoupling
Figure 8 shows a 4-channel video multiplexer using a
DG641.
In Figure 9, two coax cables terminated on 75  bring two
video signals to the DG642 switch. The two drains tied
together lower the on-state capacitance. An Si582 video
amplifier drives a double terminated 75  cable. The double
terminated coax cable eliminates line reflections.
+ 15 V
V+
CH1
CH2
Si582
75 
+
CH3
75 
A=2
75 
CH4
-
75 
DIS
250 
DG641
V-
75 
250 
-3V
TTL Channel Select
Figure 8. 4 by 1 Video Multiplexing Using the DG641
Document Number: 70058
S11-0154-Rev. F, 31-Jan-11
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9
DG641, DG642, DG643
Vishay Siliconix
APPLICATIONS
+ 15 V
V+
CH1
CH2
S1
D1
S2
D2
Si582
+
VOUT
75 
A=2
75 
75 
RL
75 
DIS
DG642
250 
V-
250 
TTL Channel Select
-3V
Figure 9. 2-Channel Video Selector Using the DG642
IN2
fc SELECT
S2
D2
C1
S3
D3
C2
1/
2
CH1
CH2
CH SELECT
D1
S1
D4
S4
DG643
R3
R1
-
IN1
LF401
1/
2
VOUT
+
DG643
R2
fc

1
2 R 3C x
Figure 10. Active Low Pass Filter with Selectable Inputs and Break Frequencies
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?70058.
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10
Document Number: 70058
S11-0154-Rev. F, 31-Jan-11
Package Information
Vishay Siliconix
SOIC (NARROW): 8-LEAD
JEDEC Part Number: MS-012
8
6
7
5
E
1
3
2
H
4
S
h x 45
D
C
0.25 mm (Gage Plane)
A
e
B
All Leads
q
A1
L
0.004"
MILLIMETERS
INCHES
DIM
Min
Max
Min
Max
A
1.35
1.75
0.053
0.069
A1
0.10
0.20
0.004
0.008
B
0.35
0.51
0.014
0.020
C
0.19
0.25
0.0075
0.010
D
4.80
5.00
0.189
0.196
E
3.80
4.00
0.150
e
0.101 mm
1.27 BSC
0.157
0.050 BSC
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.50
0.93
0.020
0.037
q
0°
8°
0°
8°
S
0.44
0.64
0.018
0.026
ECN: C-06527-Rev. I, 11-Sep-06
DWG: 5498
Document Number: 71192
11-Sep-06
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1
Package Information
Vishay Siliconix
SOIC (NARROW):
16ĆLEAD
JEDEC Part Number: MS-012
MILLIMETERS
16
15
14
13
12
11
10
Dim
A
A1
B
C
D
E
e
H
L
Ĭ
9
E
1
2
3
4
5
6
7
8
INCHES
Min
Max
Min
Max
1.35
1.75
0.053
0.069
0.10
0.20
0.004
0.008
0.38
0.51
0.015
0.020
0.18
0.23
0.007
0.009
9.80
10.00
0.385
0.393
3.80
4.00
0.149
0.157
1.27 BSC
0.050 BSC
5.80
6.20
0.228
0.244
0.50
0.93
0.020
0.037
0_
8_
0_
8_
ECN: S-03946—Rev. F, 09-Jul-01
DWG: 5300
H
D
C
All Leads
e
Document Number: 71194
02-Jul-01
B
A1
L
Ĭ
0.101 mm
0.004 IN
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1
Package Information
Vishay Siliconix
PDIP: 8ĆLEAD
8
7
6
5
E1
1
2
Dim
A
A1
B
B1
C
D
E
E1
e1
eA
L
Q1
S
3
E
4
D
S
Q1
A
MILLIMETERS
Min
Max
INCHES
Min
Max
3.81
5.08
0.150
0.200
0.38
1.27
0.015
0.050
0.38
0.51
0.015
0.020
0.89
1.65
0.035
0.065
0.20
0.30
0.008
0.012
9.02
10.92
0.355
0.430
7.62
8.26
0.300
0.325
5.59
7.11
0.220
0.280
2.29
2.79
0.090
0.110
7.37
7.87
0.290
0.310
2.79
3.81
0.110
0.150
1.27
2.03
0.050
0.080
0.76
1.65
0.030
0.065
ECN: S-03946—Rev. E, 09-Jul-01
DWG: 5478
A1
15°
MAX
e1
B1
Document Number: 71259
05-Jul-01
L
B
C
NOTE: End leads may be half leads.
eA
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1
Package Information
Vishay Siliconix
PDIP: 16ĆLEAD
16
15
14
13
12
11
10
9
E
E1
1
2
3
4
5
6
7
8
D
S
Q1
A
A1
L
15°
MAX
C
B1
e1
Dim
A
A1
B
B1
C
D
E
E1
e1
eA
L
Q1
S
B
eA
MILLIMETERS
Min
Max
INCHES
Min
Max
3.81
5.08
0.150
0.200
0.38
1.27
0.015
0.050
0.38
0.51
0.015
0.020
0.89
1.65
0.035
0.065
0.20
0.30
0.008
0.012
18.93
21.33
0.745
0.840
7.62
8.26
0.300
0.325
5.59
7.11
0.220
0.280
2.29
2.79
0.090
0.110
7.37
7.87
0.290
0.310
2.79
3.81
0.110
0.150
1.27
2.03
0.050
0.080
0.38
1.52
.015
0.060
ECN: S-03946—Rev. D, 09-Jul-01
DWG: 5482
Document Number: 71261
06-Jul-01
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1
VISHAY SILICONIX
TrenchFET® Power MOSFETs
Application Note 808
Mounting LITTLE FOOT®, SO-8 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use
integrated circuit and small-signal packages which have
been been modified to provide the heat transfer capabilities
required by power devices. Leadframe materials and
design, molding compounds, and die attach materials have
been changed, while the footprint of the packages remains
the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/ppg?72286), for the
basis of the pad design for a LITTLE FOOT SO-8 power
MOSFET. In converting this recommended minimum pad
to the pad set for a power MOSFET, designers must make
two connections: an electrical connection and a thermal
connection, to draw heat away from the package.
0.288
7.3
0.050
1.27
0.196
5.0
0.027
0.69
0.078
1.98
0.2
5.07
Figure 1. Single MOSFET SO-8 Pad
Pattern With Copper Spreading
Document Number: 70740
Revision: 18-Jun-07
0.050
1.27
0.088
2.25
0.088
2.25
0.027
0.69
0.078
1.98
0.2
5.07
Figure 2. Dual MOSFET SO-8 Pad Pattern
With Copper Spreading
The minimum recommended pad patterns for the
single-MOSFET SO-8 with copper spreading (Figure 1) and
dual-MOSFET SO-8 with copper spreading (Figure 2) show
the starting point for utilizing the board area available for the
heat-spreading copper. To create this pattern, a plane of
copper overlies the drain pins. The copper plane connects
the drain pins electrically, but more importantly provides
planar copper to draw heat from the drain leads and start the
process of spreading the heat so it can be dissipated into the
ambient air. These patterns use all the available area
underneath the body for this purpose.
Since surface-mounted packages are small, and reflow
soldering is the most common way in which these are
affixed to the PC board, “thermal” connections from the
planar copper to the pads have not been used. Even if
additional planar copper area is used, there should be no
problems in the soldering process. The actual solder
connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the
drain pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces.
The absolute minimum power trace width must be
determined by the amount of current it has to carry. For
thermal reasons, this minimum width should be at least
0.020 inches. The use of wide traces connected to the drain
plane provides a low impedance path for heat to move away
from the device.
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1
APPLICATION NOTE
In the case of the SO-8 package, the thermal connections
are very simple. Pins 5, 6, 7, and 8 are the drain of the
MOSFET for a single MOSFET package and are connected
together. In a dual package, pins 5 and 6 are one drain, and
pins 7 and 8 are the other drain. For a small-signal device or
integrated circuit, typical connections would be made with
traces that are 0.020 inches wide. Since the drain pins serve
the additional function of providing the thermal connection
to the package, this level of connection is inadequate. The
total cross section of the copper may be adequate to carry
the current required for the application, but it presents a
large thermal impedance. Also, heat spreads in a circular
fashion from the heat source. In this case the drain pins are
the heat sources when looking at heat spread on the PC
board.
0.288
7.3
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-8
0.172
(4.369)
0.028
0.022
0.050
(0.559)
(1.270)
0.152
(3.861)
0.047
(1.194)
0.246
(6.248)
(0.711)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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22
Document Number: 72606
Revision: 21-Jan-08
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR SO-16
RECOMMENDED MINIMUM PADS FOR SO-16
0.372
(9.449)
0.152
0.022
0.050
0.028
(0.559)
(1.270)
(0.711)
(3.861)
0.246
(6.248)
0.047
(1.194)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
APPLICATION NOTE
Return to Index
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24
Document Number: 72608
Revision: 21-Jan-08
Legal Disclaimer Notice
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular
purpose, non-infringement and merchantability.
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular
product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,
including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree
to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and
damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay
or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to
obtain written terms and conditions regarding products designed for such applications.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 11-Mar-11
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1