VISHAY DG407DN-T1-E3

DG406/407
Vishay Siliconix
16-Ch/Dual 8-Ch High-Performance CMOS Analog Multiplexers
DESCRIPTION
FEATURES
The DG406 is a 16-channel single-ended analog multiplexer
designed to connect one of sixteen inputs to a common
output as determined by a 4-bit binary address. The DG407
selects one of eight differential inputs to a common
differential output. Break-before-make switching action
protects against momentary shorting of inputs.
An on channel conducts current equally well in both
directions. In the off state each channel blocks voltages up
to the power supply rails. An enable (EN) function allows the
user to reset the multiplexer/demultiplexer to all switches off
for stacking several devices. All control inputs, address (Ax)
and enable (EN) are TTL compatible over the full specified
operating temperature range.
Applications for the DG406/407 include high speed data
acquisition, audio signal switching and routing, ATE
systems, and avionics. High performance and low power
dissipation make them ideal for battery operated and remote
instrumentation applications. For additional application
information order Faxback document numbers 70601 and
70604.
Designed in the 44 V silicon-gate CMOS process, the
absolute maximum voltage rating is extended to 44 volts,
allowing operation with ± 20 V supplies. Additionally single
(12 V) supply operation is allowed. An epitaxial layer
prevents latchup.
•
•
•
•
•
•
Low On-Resistance - rDS(on): 50 Ω
Low Charge Injection - Q: 15 pC
Fast Transition Time - tTRANS: 200 ns
Low Power: 0.2 mW
Single Supply Capability
44 V Supply Max Rating
Pb-free
Available
RoHS*
COMPLIANT
BENEFITS
•
•
•
•
•
•
Higher Accuracy
Reduced Glitching
Improved Data Throughput
Reduced Power Consumption
Increased Ruggedness
Wide Supply Ranges: ± 5 V to ± 20 V
APPLICATIONS
•
•
•
•
•
•
•
Data Acquisition Systems
Audio Signal Routing
Medical Instrumentation
ATE Systems
Battery Powered Systems
High-Rel Systems
Single Supply Systems
For applications information please request FaxBack
documents 70601 and 70604.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
DG406
DG407
Dual-In-Line and SOIC Wide-Body
V+
NC
NC
Dual-In-Line and SOIC Wide-Body
28
D
V+
1
28
Da
2
27
V-
Db
2
27
V-
3
26
S8
NC
3
26
S8a
S8b
4
25
S7a
1
S16
4
25
S7
S15
5
24
S6
S7b
5
24
S6a
23
S5
S6b
6
23
S5a
7
22
S4a
21
S3a
20
S2a
S14
6
S13
7
22
S4
S5b
S12
8
21
S3
S4b
8
9
S11
9
20
S2
S3b
S10
10
19
S1
S2b
10
19
S1a
18
EN
S1b
11
18
EN
17
A0
GND
12
17
A0
13
16
A1
14
15
A2
S9
11
GND
12
Decoders/Drivers
NC
13
16
A1
NC
A3
14
15
A2
NC
Top View
2
Decoders/Drivers
Top View
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 70061
S-71009–Rev. I, 14-May-07
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1
DG406/407
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
5
25
S7
S7b
S14
6
24
S6
S13
7
23
S5
Da
V-
S15
V+
D
28 27 26
Db
V+
1
NC
NC
2
S 8b
NC
3
S8
S 16
4
S 8a
PLCC and LCC
DG407
4
3
2
1
28 27 26
V-
PLCC and LCC
DG406
5
25
S7a
S6b
6
24
S6a
S5b
7
23
S5a
S4b
8
22
S4a
S12
8
22
S4
S11
9
21
S3
S3b
9
21
S3a
S10
10
20
S2
S2b
10
20
S2a
S9
11
19
S1
S1b
11
19
S1a
EN
A0
A1
A2
NC
NC
GND
EN
A0
NC
A1
12 13 14 15 16 17 18
A2
12 13 14 15 16 17 18
A3
Decoders/Drivers
GND
Decoders/Drivers
Top View
Top View
TRUTH TABLE - DG406
TRUTH TABLE - DG407
A3
A2
A1
A0
EN
On Switch
A2
A1
A0
EN
On Switch Pair
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
None
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
None
1
2
3
4
5
6
7
8
Logic "0" = VAL ≤ 0.8 V
Logic "1" = VAH ≥ 2.4 V
X = Do not Care
ORDERING INFORMATION - DG406
ORDERING INFORMATION - DG407
Temp Range
Temp Range
- 40 to 85 °C
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Package
Part Number
28-Pin Plastic DIP
DG406DJ
DG406DJ-E3
28-Pin PLCC
DG406DN
DG406DN-T1-E3
28-Pin Widebody SOIC
DG406DW
DG406DW-E3
- 40 to 85 °C
Package
Part Number
28-Pin Plastic DIP
DG407DJ
DG407DJ-E3
28-Pin PLCC
DG407DN
DG407DN-T1-E3
28-Pin Widebody SOIC
DG407DW
DG407DW-E3
Document Number: 70061
S-71009–Rev. I, 14-May-07
DG406/407
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltages Referenced to V-
V+
GND
Digital Inputsa, VS, VD
Current (Any Terminal)
Peak Current, S or D (Pulsed at 1 ms, 10 % Duty Cycle Max)
Storage Temperature
Power Dissipation (Package)b
Limit
44
25
(V-) - 2 V to (V+) + 2 V
or 20 mA, whichever occurs first
30
100
(AK, AZ Suffix)
- 65 to 150
(DJ, DN Suffix)
- 65 to 125
Unit
V
mA
°C
28-Pin Plastic DIPb
625
28-Pin CerDIPd
1.2
W
28-Pin Plastic PLCCc
450
mW
LCC-28e
28-Pin Widebody SOIC
1.35
W
450
mW
mW
Notes:
a. Signals on SX, DX or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 6 mW/°C above 75°C.
d. Derate 12 mW/°C above 75°C.
e. Derate 13.5 mW/°C above 75°C .
Document Number: 70061
S-71009–Rev. I, 14-May-07
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DG406/407
Vishay Siliconix
SPECIFICATIONSa
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V- = - 15 V
VAL = 0.8 V, VAH = 2.4 Vf
Tempb
rDS(on)
VD = ± 10 V, IS = - 10 mA
Sequence Each Switch On
Room
Full
50
ΔrDS(on)
VD = ± 10 V
Room
5
Parameter
Analog Switch
Symbol
Analog Signal Rangee
Drain-Source
On-Resistance
VANALOG
rDS(on) Matching Between Channelsg
Source Off Leakage Current
Drain Off Leakage Current
Full
IS(off)
ID(off)
VEN = 0 V
VD = ± 10 V
VS = ± 10 V
DG406
DG407
Drain On Leakage Current
ID(on)
Typc
VS = VD = ± 10
Sequence Each
Switch On
DG406
DG407
Room
Full
Room
Full
Room
Full
Room
Full
Room
Full
A Suffix
- 55 to 125 °C
D Suffix
- 40 to 85 °C
Mind
Maxd
Mind
15
- 15
- 15
0.01
0.04
0.04
0.04
0.04
100
125
Maxd
Unit
15
V
100
125
Ω
%
- 0.5
- 50
-1
- 200
-1
- 100
-1
- 200
-1
- 100
0.5
50
1
200
1
100
1
200
1
100
- 0.5
-5
-1
- 40
-1
- 20
-1
- 40
-1
- 20
0.5
5
1
40
1
20
1
40
1
20
nA
Digital Control
Logic High Input Voltage
VINH
Full
Logic Low Input Voltage
VINL
Full
Logic High Input Current
IAH
VA = 2.4 V, 15 V
Full
-1
1
-1
1
Logic Low Input Current
IAL
VEN = 0 V, 2.4 V, VA = 0 V
Full
-1
1
-1
1
Logic Input Capacitance
Cin
f = 1 MHz
Room
7
Transition Time
tTRANS
See Figure 2
200
Break-Before-Make Interval
tOPEN
See Figure 4
Enable Turn-On Time
tON(EN)
Enable Turn-Off Time
tOFF(EN)
Room
Full
Room
Full
Room
Full
Room
Full
Room
15
pC
Room
- 69
dB
2.4
2.4
0.8
0.8
V
µA
pF
Dynamic Characteristics
See Figure 3
Charge Injection
Q
Off Isolationh
OIRR
Source Off Capacitance
CS(off)
Drain Off Capacitance
Drain On Capacitance
CD(off)
CD(on)
VS = 0 V, CL = 1 nF, RS = 0 Ω
VEN = 0 V, RL = 1 kΩ
f = 100 kHz
VEN = 0 V, VS = 0 V, f = 1 MHz
VEN = 0 V
VD = 0 V
f = 1 MHz
50
350
450
25
10
150
Room
8
130
DG407
Room
65
DG406
Room
140
DG407
Room
70
Room
Full
Room
Full
Room
Full
Room
Full
13
25
10
200
400
150
300
70
Room
350
450
200
400
150
300
ns
pF
Power Supplies
Positive Supply Current
I+
Negative Supply Current
I-
Positive Supply Current
I+
Negative Supply Current
I-
VEN = VA = 0 or 5 V
VEN = 2.4 V, VA = 0 V
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- 0.01
30
75
-1
- 10
50
- 0.01
30
75
-1
- 10
500
900
- 20
- 20
500
700
µA
- 20
- 20
Document Number: 70061
S-71009–Rev. I, 14-May-07
DG406/407
Vishay Siliconix
SPECIFICATIONSa (FOR SINGLE SUPPLY)
Test Conditions
Unless Otherwise Specified
V+ = 12 V, V- = 0 V
Parameter
Analog Switch
Symbol
Analog Signal Rangee
Drain-Source
On-Resistance
VANALOG
rDS(on)
rDS(on) Matching Between Channelsg ΔrDS(on)
Source Off Leakage Current
IS(off)
Drain Off Leakage Current
ID(off)
Drain On Leakage Current
ID(on)
VAL = 0.8 V, VAH = 2.4 Vf
Tempb
Typc
Full
VD = 3 V, 10 V, IS = - 1 mA
Sequence Each Switch On
VEN = 0 V
VD = 10 V or 0.5 V
VS = 0.5 V or 10 V
VS = VD = ± 10
Sequence Each
Switch On
Room
A Suffix
- 55 to 125 °C
D Suffix
- 40 to 85 °C
Mind
Maxd
Mind
Maxd
Unit
0
12
0
12
V
120
Ω
90
Room
5
Room
0.01
DG406
Room
0.04
DG407
Room
0.04
DG406
Room
0.04
DG407
Room
0.04
120
%
nA
Dynamic Characteristics
Switching Time of Multiplexer
tOPEN
VS1 = 8 V, VS8 = 0 V, VIN = 2.4 V
Room
300
450
450
Enable Turn-On Time
tON(EN)
Room
250
600
600
Enable Turn-Off Time
tOFF(EN)
VINH = 2.4 V, VINL = 0 V
VS1 = 5 V
Room
150
300
300
Q
CL = 1 nF, VS = 6 V, RS = 0
Room
20
Room
Full
Room
Full
13
VEN = 0 V or 5 V, VA = 0 V or 5 V
Charge Injection
ns
pC
Power Supplies
Positive Supply Current
Negative Supply Current
I+
I-
- 0.01
30
75
- 20
- 20
30
75
- 20
- 20
µA
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
g. ΔrDS(on) = rDS(on) MAX - rDS(on) MIN.
h. Worst case isolation occurs on Channel 4 due to proximity to the drain pin.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Document Number: 70061
S-71009–Rev. I, 14-May-07
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DG406/407
Vishay Siliconix
TYPICAL CHARACTERISTICS TA = 25 °C, unless otherwise noted
80
160
120
r DS(on) – On-Resistance (Ω)
r DS(on) – On-Resistance (Ω)
70
± 5V
80
±8V
± 10 V
± 12 V
± 15 V
40
± 20 V
125 °C
60
85 °C
50
25 °C
40
0°C
30
- 40 °C
20
- 55 °C
10
0
- 15
0
- 20
- 12
-4
4
VD – Drain Voltage (V)
12
V+ = 15 V
V- = - 15 V
20
- 10
-5
0
5
VD – Drain Voltage (V)
10
15
rDS(on) vs. VD and Temperature
rDS(on) vs. VD and Supply
120
V+ = 7.5 V
80
200
I D, I S – Current (pA)
r DS(on) – On-Resistance (Ω)
V+ = 15 V
V- = - 15 V
VS = - VD for ID(off)
VD = VS(open) for ID(on)
V- = 0 V
240
160
10 V
120
12 V
15 V
80
20 V
22 V
40
IS(off)
0
DG406 ID(on), ID(off)
- 40
DG407 ID(on), ID(off)
- 80
40
- 120
- 15
0
0
4
8
12
VD – Drain Voltage (V)
16
20
15
350
100 nA
V+ = 15 V
V- = - 15 V
VD = "14 V
300
tTRANS
250
1 nA
ID(on), ID(off)
Time (ns)
I D, I S – Current
-5
0
5
10
VS , VD – Source Drain Voltage (V)
ID , IS Leakage Currents vs. Analog Voltage
rDS(on) vs. VD and Supply
10 nA
- 10
100 pA
200
tON(EN)
150
IS(off)
10 pA
100
tOFF(EN)
1 pA
50
0.1 pA
- 55 - 35 - 15
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6
0
5
25
45
65
85
105
125
±5
± 10
± 15
Temperature (°C)
VSUPPLY – Supply Voltage (V)
ID , IS Leakages vs. Temperature
Switching Times vs. Bipolar Supplies
± 20
Document Number: 70061
S-71009–Rev. I, 14-May-07
DG406/407
Vishay Siliconix
TYPICAL CHARACTERISTICS TA = 25 °C, unless otherwise noted
70
700
600
60
500
50
tTRANS
400
Q (pC)
Time (ns)
V- = 0 V
300
40
V+ = 12 V,
V- = 0 V
30
tON(EN)
200
V+ = 15 V,
V- = - 15 V
20
100
10
tOFF(EN)
0
5
10
15
0
- 15
20
- 10
-5
0
5
15
VS – Source Voltage (V)
V+ – Supply Voltage (V)
Switching Times vs. Single Supply
Charge Injection vs. Analog Voltage
- 140
10
EN = 5 V
AX = 0 or 5 V
8
- 120
I+
6
- 100
4
I – Current (mA)
ISOL (dB)
10
- 80
- 60
2
0
IGND
-2
-4
- 40
I-6
- 20
-8
0
- 10
100
1k
10 k
100 k
1M
10 M
10
10 k
100 k
1M
10 M
Off-Isolation vs. Frequency
Supply Currents vs. Switching Frequency
3
V+ = 15 V
V- = - 15 V
2
220
tTRANS
V TH (V)
Time (ns)
1k
f – Frequency (Hz)
300
260
100
f – Frequency (Hz)
tON(EN)
180
1
140
100
tOFF(EN)
0
60
- 55 - 35 - 15
5
25
45
65
85
105
125
0
5
10
15
Temperature (°C)
VSUPPLY – Supply Voltage (V)
tON/tOFF vs. Temperature
Switching Threshold vs. Supply Voltage
Document Number: 70061
S-71009–Rev. I, 14-May-07
20
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DG406/407
Vishay Siliconix
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+
VREF
GND
D
A0
V+
Level
Shift
AX
V-
Decode/
Drive
S1
V+
EN
Sn
V-
Figure 1.
TEST CIRCUITS
+ 15 V
+ 2.4 V
V+
EN
A2
A1
± 10 V
S1
A3
S2 - S 15
DG406
S16
A0
± 10 V
VO
D
GND
Logic
Input
V-
tr < 20 ns
tf < 20 ns
3V
50 %
0V
50 Ω
35 pF
300 Ω
- 15 V
VS1
90 %
Switch
Output
+ 15 V
+ 2.4 V
V+
EN
A2
VO
S1b
0V
90 %
± 10 V
VS8
*
DG407
S8b
A1
A0
tTRANS
± 10 V
S1 ON
Db
GND
tTRANS
S8 ON
VO
V-
50 Ω
300 Ω
35 pF
- 15 V
* = S1a – S8a, S2b S± 7b, Da
Figure 2. Transition Time
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Document Number: 70061
S-71009–Rev. I, 14-May-07
DG406/407
Vishay Siliconix
TEST CIRCUITS
+ 15 V
V+
A3
-5V
S1
A2
S2 - S 16
A1
DG406
A0
VO
D
EN
GND
V300 Ω
50 Ω
Logic
Input
35 pF
- 15 V
tr < 20 ns
tf < 20 ns
3V
50 %
0V
tON(EN)
+ 15 V
V+
A2
S1b
S1a - S 8a
S2b - S 8b
A1
A0
tOFF(EN)
0V
Switch
Output
-5V
VO
90 %
90 %
VO
DG407
Da and Db
EN
GND
VO
V-
35 pF
50 Ω
300 Ω
- 15 V
Figure 3. Enable Switching Time
+ 15 V
Logic
Input
V+
EN
+ 2.4 V
All S and Da
A3
A2
A1
+5V
tr < 20 ns
tf < 20 ns
3V
50 %
0V
DG406
DG407
A0
GND
50 Ω
VS
VO
D,D b
80 %
Switch
Output
V300 Ω
35 pF
VO
- 15 V
0V
tOPEN
Figure 4. Break-Before-Make Interval
Document Number: 70061
S-71009–Rev. I, 14-May-07
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DG406/407
Vishay Siliconix
APPLICATIONS HINTS
Sampling speed is limited by two consecutive events: the
transition time of the multiplexer, and the settling time of the
sampled signal at the output.
tTRANS is given on the data sheet. Settling time at the load
depends on several parameters: rDS(on) of the multiplexer,
source impedance, multiplexer and load capacitances,
charge injection of the multiplexer and accuracy desired.
The settling time for the multiplexer alone can be derived
from the model shown in Figure 5. Assuming a low
impedance signal source like that presented by an op amp or
a buffer amplifier, the settling time of the RC network for a
given accuracy is equal to nτ:
The maximum sampling frequency of the multiplexer is:
1
f s = ---------------------------------------------------------N ( t SETTLING + t TRANS )
(1)
where N = number of channels to scan
tSETTLING = nτ = n x rDS(on) x CD(on)
For the DG406 then, at room temp and for 12-bit accuracy,
using the maximum limits:
1
f s = ------------------------------------------------------------------------------------------------------12
-12
16 ( 9 × 100 Ω × 10 F ) + 300 × 10 s
(2)
or
% ACCURACY
# BITS
N
0.25
8
6
0.012
12
9
0.0017
15
11
rDS(on)
VOUT
RS = 0
CD(on)
Figure 5. Simplified Model of One Multiplexer Channel
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fs = 694 kHz
(3)
From the sampling theorem, to properly recover the original
signal, the sampling frequency should be more than twice
the maximum component frequency of the original signal.
This assumes perfect bandlimiting. In a real application
sampling at three to four times the filter cutoff frequency is a
good practice.
Therefore from equation 2 above:
1
f c = --- × f s = 173 kHz
4
(4)
From this we can see that the DG406 can be used to sample
16 different signals whose maximum component frequency
can be as high as 173 kHz. If for example, two channels are
used to double sample the same incoming signal then its
cutoff frequency can be doubled.
Document Number: 70061
S-71009–Rev. I, 14-May-07
DG406/407
Vishay Siliconix
APPLICATIONS HINTS
The block diagram shown in Figure 6 illustrates a typical data
acquisition front end suitable for low-level analog signals.
Differential multiplexing of small signals is preferred since
this method helps to reject any common mode noise. This is
especially important when the sensors are located at a
distance and it may eliminate the need for individual
To
Sensor 1
To
Sensor 8
Analog
Multiplexer
amplifiers. A low rDS(on), low leakage multiplexer like the
DG407 helps to reduce measurement errors. The low power
dissipation of the DG407 minimizes on-chip thermal
gradients which can cause errors due to temperature
mismatch along the parasitic thermocouple paths. Please
refer to Application Note AN203 for additional information.
Inst
Amp
DG407
S/H
12-Bit
A/D
Converter
Controller
Figure 6. Measuring low-level analog signals is more accurate when using a differential multiplexing technique.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability
data, see http://www.vishay.com/ppg?70061.
Document Number: 70061
S-71009–Rev. I, 14-May-07
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Document Number: 91000
Revision: 18-Jul-08
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