Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture • • • • • • • – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-Volatile Program and Data Memories – 4K Bytes of In-System Programmable Program Memory Flash – 64 Bytes of In-System Programmable EEPROM – 256 Bytes of Internal SRAM – Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data retention: 20 years at 85°C/ 100 years at 85°C(1) – Programming Lock for Software Security Peripheral Features – Two 8-Bit Timer/Counters with two PWM Channels, Each – Programmable Watchdog Timer with Separate On-chip Oscillator – On-Chip Analog Comparator – 10-bit ADC 4 Single-Ended Channels – Universal Serial Interface – Boost Converter Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Pin Change Interrupt on 16 Pins – Low Power Idle, ADC Noise Reduction and Power-Down Modes – Enhanced Power-On Reset Circuit – Programmable Brown-Out Detection Circuit – Internal Calibrated Oscillator – Temperature Sensor On Chip I/O and Packages – Available in 20-Pin SOIC and 20-Pin QFN/MLF – 16 Programmable I/O Lines Operating Voltage: – 0.7 – 1.8V (via On-Chip Boost Converter) – 1.8 – 5.5V (Boost Converter Bypassed) Speed Grade – Using On-Chip Boost Converter 0 – 4 MHz – External Power Supply 0 – 4 MHz @ 1.8 – 5.5V 0 – 8 MHz @ 2.7 – 5.5V Low Power Consumption – Active Mode, 1 MHz System Clock (Without Boost Converter) 400 µA @ 3V – Power-Down Mode (Without Boost Converter) 150 nA @ 3V Note: 1. See “Data Retention” on page 6 for details. 8-bit Microcontroller with 4K Bytes In-System Programmable Flash and Boost Converter ATtiny43U Preliminary Summary Rev. 8048BS–AVR–03/09 1. Pin Configurations Figure 1-1. Pinout of ATtiny43U SOIC (T0/PCINT8) PB0 (OC0A/PCINT9) PB1 (OC0B/PCINT10) PB2 (T1/CLKO/PCINT11) PB3 (DI/OC1A/PCINT12) PB4 (DO/OC1B/PCINT13) PB5 (USCK/SCL/PCINT14) PB6 (INT0/PCINT15) PB7 VCC GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA7 (RESET/dW/PCINT7) PA6 (CLKI/PCINT6) PA5 (AIN1/PCINT5) PA4 (AIN0/PCINT4) PA3 (ADC3/PCINT3) PA2 (ADC2/PCINT2) PA1 (ADC1/PCINT1) PA0 (ADC0/PCINT0) VBAT LSW PB0 (T0/PCINT8) PA7 (RESET/dW/PCINT7) PA6 (CLKI) PA5 (AIN1/PCINT5) 20 19 18 17 16 PB1 (OC0A/PCINT9) QFN/MLF Top View (OC0B/PCINT9) PB2 (T1/CLKO/PCINT11) PB3 (DI/OC1A/PCINT12) PB4 (DO/OC1B/PCINT13) PB5 PA4 (AIN0/PCINT4) PA3 (ADC3/PCINT3) PA2 (ADC2/PCINT2) PA1 (ADC1/PCINT1) PA0 (ADC0/PCINT0) NOTE: Bottom pad should be Soldered to ground. 1.1 1.1.1 VCC GND LSW VBAT (INT0/PCINT15) PB7 6 7 8 9 10 (USCK/SCL/PCINT14) PB6 15 14 13 12 11 1 2 3 4 5 Pin Descriptions VCC Supply voltage. 1.1.2 GND Ground. 1.1.3 2 Port A (PA7:PA0) Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source ATtiny43U 8048BS–AVR–03/09 capability except PA7 which has the RESET capability. To use pin PA7 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has an alternate functions as analog inputs for the ADC, analog comparator, timer/counter, SPI and pin change interrupt as described in “Alternate Port Functions” on page 67. 1.1.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 20-4 on page 158. Shorter pulses are not guaranteed to generate a reset. 1.1.5 Port B (PB7:PB0) Port B is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features as listed in Section 11.3 “Alternate Port Functions” on page 67. 1.1.6 LSW Boost converter external inductor connection. Connect to ground when boost converter is disabled permanently. 1.1.7 VBAT Battery supply voltage. Connect to ground when boost converter is disabled permanently. 3 8048BS–AVR–03/09 2. Overview The ATtiny43U is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny43U achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. Figure 2-1. Block Diagram VCC VBAT LSW RESET POWER SUPERVISION BOOST CONVERTER INTERNAL OSCILLATOR CALIBRATED OSCILLATOR WATCHDOG TIMER TIMING AND CONTROL POR BOD RESET GND PROGRAMMING LOGIC PROGRAM COUNTER PROGRAM FLASH STACK POINTER INSTRUCTION REGISTER SRAM INSTRUCTION DECODER GENERAL PURPOSE REGISTERS CONTROL LINES X Y Z MCU CONTROL REGISTER MCU STATUS REGISTER TIMER/ COUNTER0 TIMER/ COUNTER1 INTERRUPT UNIT ANALOG COMPARATOR ON-CHIP DEBUG ALU EEPROM VOLTAGE REFERENCE ISP INTERFACE STATUS REGISTER USI ADC DATA REGISTER PORT A DIRECTION REG. PORT A DATA REGISTER PORT B DIRECTION REG. PORT B DRIVERS PORT A DRIVERS PORT B PA7:0 PB7:0 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting 4 ATtiny43U 8048BS–AVR–03/09 architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny43U provides the following features: 4K byte of In-System Programmable Flash, 64 bytes EEPROM, 256 bytes SRAM, 16 general purpose I/O lines, 32 general purpose working registers, two 8-bit Timer/Counters with two PWM channels, Internal and External Interrupts, a 4-channel 10-bit ADC, Universal Serial Interface, a programmable Watchdog Timer with internal Oscillator, internal calibrated oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. A special feature of ATtiny43U is the built-in boost voltage converter, which provides 3V supply voltage from an external, low voltage. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny43U AVR is supported by a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 5 8048BS–AVR–03/09 3. About 3.1 Resources A comprehensive set of development tools, drivers and application notes, and datasheets are available for download on http://www.atmel.com/avr. 3.2 Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 3.4 Disclaimer Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized. 6 ATtiny43U 8048BS–AVR–03/09 4. Register Summary Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x3F (0x5F) SREG T H S V N Z C Page 8 – – – – – SP8 Page 12 SP6 SP1 SP0 0x3E (0x5E) SPH I – 0x3D (0x5D) SPL SP7 0x3C (0x5C) OCR0B – SP5 SP4 SP3 SP2 Timer/Counter0 – Output Compare Register B Page 12 Page 95 0x3B (0x5B) GIMSK – INT0 PCIE1 PCIE0 – – – – Page 60 0x3A (0x5A) GIFR – INTF0 PCIF1 PCIF0 – – – – Page 60 0x39 (0x59) TIMSK0 – – – – – OCIE0B OCIE0A TOIE0 Page 95 0x38 (0x58) TIFR0 – – – – – OCF0B OCF0A TOV0 Page 96 0x37 (0x57) SPMCSR – – – CTPB RFLB PGWRT Timer/Counter0 – Output Compare Register A PGERS SPMEN Page 137 BODS PUD SE SM1 0x36 (0x56) OCR0A 0x35 (0x55) MCUCR Page 95 SM0 BODSE ISC01 ISC00 Page 34, Page 59, Page 78 0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF Page 54 0x33 (0x53) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 Page 93 0x32 (0x52) TCNT0 0x31 (0x51) OSCCAL CAL2 CAL1 CAL0 Page 28 Page 90 Timer/Counter0 CAL7 CAL6 CAL5 CAL4 CAL3 Page 94 0x30 (0x50) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – WGM01 WGM00 0x2F (0x4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – WGM11 WGM10 Page 90 0x2E (0x4E) TCCR1B FOC1A FOC1B – – WGM12 CS11 CS10 Page 93 CS12 0x2D (0x4D) TCNT1 Timer/Counter1 Page 95 0x2C (0x4C) OCR1A Timer/Counter1 – Output Compare Register A Page 95 0x2B (0x4B) OCR1B Timer/Counter1 – Output Compare Register B Page 95 0x2A (0x4A) Reserved – 0x29 (0x49) Reserved – 0x28 (0x48) Reserved – 0x27 (0x47) DWDR DWDR[7:0] 0x26 (0x46) CLKPR 0x25 (0x45) Reserved 0x24 (0x44) Reserved 0x23 (0x43) GTCCR 0x22 (0x42) Reserved 0x21 (0x41) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 Page 54 0x20 (0x40) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 Page 61 – – EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 0x1F (0x3F) Reserved 0x1E (0x3E) EEAR 0x1D (0x3D) EEDR CLKPCE – – – Page 132 CLKPS3 CLKPS2 CLKPS1 CLKPS0 Page 28 – – – PSR10 Page 99 – – TSM – – – – – EEPROM Data Register Page 20 Page 21 0x1C (0x3C) EECR – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE Page 21 0x1B (0x3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 Page 78 0x1A (0x3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 Page 78 0x19 (0x39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 Page 78 0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 Page 78 0x17 (0x37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 Page 78 0x16 (0x36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 Page 78 0x15 (0x35) GPIOR2 General Purpose I/O Register 2 Page 22 0x14 (0x34) GPIOR1 General Purpose I/O Register 1 Page 22 0x13 (0x33) GPIOR0 General Purpose I/O Register 0 0x12 (0x32) PCMSK0 0x11 (0x31) Reserved – 0x10 (0x30) USIBR USI Buffer Register Page 111 0x0F (0x2F) USIDR USI Data Register Page 112 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 Page 22 PCINT2 PCINT1 PCINT0 Page 61 0x0E (0x2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 Page 112 0x0D (0x2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC Page 112 0x0C (0x2C) TIMSK1 – – – – OCIE1B OCIE1A TOIE1 Page 96 0x0B (0x2B) TIFR1 – – – – – – OCF1B OCF1A TOV1 Page 96 0x0A (0x2A) Reserved 0x09 (0x29) Reserved 0x08 (0x28) ACSR ACD ACBG ACO ACI ACIE – ACIS1 ACIS0 Page 113 0x07 (0x27) ADMUX – REFS – – – MUX2 MUX1 MUX0 Page 126 0x06 (0x26) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 0x05 (0x25) ADCH 0x04 (0x24) ADCL 0x03 (0x23) ADCSRB 0x02 (0x22) Reserved 0x01 (0x21) DIDR0 0x00 (0x20) PRR – – ADC Data Register High Byte ADC Data Register Low Byte BS ACME – ADLAR AIN1D AIN0D PRE0 – – Page 127 Page 128 Page 128 ADTS2 ADTS1 ADTS0 Pages 47, 113, 129 ADC3D ADC2D PRTIM1 PRTIM0 ADC1D ADC0D Page 114, Page 130 PRUSI PRADC Page 35 – PRE2 PRE1 7 8048BS–AVR–03/09 Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. 3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only. 8 ATtiny43U 8048BS–AVR–03/09 5. Instruction Set Summary Mnemonics Operands Description Operation Flags #Clocks ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1 ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2 SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1 SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1 SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1 SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1 SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2 AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1 ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1 OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1 ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1 EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1 1 COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1 NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1 SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1 CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1 INC Rd Increment Rd ← Rd + 1 Z,N,V 1 DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1 TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1 CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1 SER Rd Set Register Rd ← 0xFF None 1 2 BRANCH INSTRUCTIONS RJMP k IJMP RCALL k Relative Jump PC ← PC + k + 1 None Indirect Jump to (Z) PC ← Z None 2 Relative Subroutine Call PC ← PC + k + 1 None 3 3 ICALL Indirect Call to (Z) PC ← Z None RET Subroutine Return PC ← STACK None 4 RETI Interrupt Return PC ← STACK I 4 CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1 CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1 CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3 1/2/3 1 SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3 SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3 SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3 BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2 BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2 BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2 BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2 BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2 BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2 BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2 BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2 BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2 BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2 BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2 BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2 BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2 BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2 BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2 BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2 BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2 BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2 BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2 BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2 BIT AND BIT-TEST INSTRUCTIONS SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2 CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2 LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1 LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1 ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1 9 8048BS–AVR–03/09 Mnemonics Operands Description Operation Flags #Clocks ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1 ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1 SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1 BSET s Flag Set SREG(s) ← 1 SREG(s) 1 BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1 BST Rr, b Bit Store from Register to T T ← Rr(b) T 1 BLD Rd, b Bit load from T to Register Rd(b) ← T None 1 SEC Set Carry C←1 C 1 CLC Clear Carry C←0 C 1 SEN Set Negative Flag N←1 N 1 CLN Clear Negative Flag N←0 N 1 SEZ Set Zero Flag Z←1 Z 1 CLZ Clear Zero Flag Z←0 Z 1 SEI Global Interrupt Enable I←1 I 1 CLI Global Interrupt Disable I←0 I 1 SES Set Signed Test Flag S←1 S 1 CLS Clear Signed Test Flag S←0 S 1 SEV Set Twos Complement Overflow. V←1 V 1 CLV Clear Twos Complement Overflow V←0 V 1 SET Set T in SREG T←1 T 1 CLT Clear T in SREG T←0 T 1 SEH CLH Set Half Carry Flag in SREG Clear Half Carry Flag in SREG H←1 H←0 H H 1 Rd ← Rr Rd+1:Rd ← Rr+1:Rr None 1 None 1 1 1 DATA TRANSFER INSTRUCTIONS MOV Rd, Rr Move Between Registers MOVW Rd, Rr Copy Register Word LDI Rd, K Load Immediate Rd ← K None LD Rd, X Load Indirect Rd ← (X) None 2 LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2 2 LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None LD Rd, Y Load Indirect Rd ← (Y) None 2 LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2 2 LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2 LD Rd, Z Load Indirect Rd ← (Z) None 2 LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2 LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2 LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2 LDS Rd, k Load Direct from SRAM Rd ← (k) None 2 ST X, Rr Store Indirect (X) ← Rr None 2 ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2 ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2 ST Y, Rr Store Indirect (Y) ← Rr None 2 ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2 ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2 STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2 ST Z, Rr Store Indirect (Z) ← Rr None 2 ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2 ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2 STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2 STS k, Rr Store Direct to SRAM (k) ← Rr None 2 Load Program Memory R0 ← (Z) None 3 LPM LPM Rd, Z Load Program Memory Rd ← (Z) None 3 LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3 Store Program Memory (z) ← R1:R0 None IN Rd, P In Port Rd ← P None OUT P, Rr Out Port P ← Rr None 1 PUSH Rr Push Register on Stack STACK ← Rr None 2 POP Rd Pop Register from Stack Rd ← STACK None 2 SPM 1 MCU CONTROL INSTRUCTIONS NOP No Operation None 1 SLEEP Sleep (see specific descr. for Sleep function) None 1 WDR BREAK Watchdog Reset Break (see specific descr. for WDR/Timer) For On-chip Debug Only None None 1 N/A 10 ATtiny43U 8048BS–AVR–03/09 6. Ordering Information 6.1 ATtiny43U Speed (MHz) Power Supply 8 1.8 - 5.5V (3) Notes: Ordering Code (1) Package (2) ATtiny43U-MU ATtiny43U-SU 20M1 20S2 Operational Range Industrial (-40°C to 85°C) 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. 2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. 3. Supply voltage on VCC pin, boost converter disregarded. When boost converter is active the device can be operated from voltages sources lower than indicated here. See table “Characteristics of Boost Converter. T = -20°C ... +85°C, unless otherwise noted” on page 159 for more information. Package Type 20M1 20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF) 20S2 20-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 11 8048BS–AVR–03/09 7. Packaging Information 7.1 20M1 D 1 Pin 1 ID 2 SIDE VIEW E 3 TOP VIEW A2 D2 A1 A 0.08 1 2 Pin #1 Notch (0.20 R) 3 COMMON DIMENSIONS (Unit of Measure = mm) E2 b L e BOTTOM VIEW SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 – 0.01 0.05 A2 b D D2 E2 L 0.23 0.30 4.00 BSC 2.45 2.60 2.75 4.00 BSC 2.45 e Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5. NOTE 0.20 REF 0.18 E Note: C 2.60 2.75 0.50 BSC 0.35 0.40 0.55 10/27/04 R 12 2325 Orchard Parkway San Jose, CA 95131 TITLE 20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm, 2.6 mm Exposed Pad, Micro Lead Frame Package (MLF) DRAWING NO. 20M1 REV. A ATtiny43U 8048BS–AVR–03/09 7.2 20S2 13 8048BS–AVR–03/09 8. Errata The revision letter in this section refers to the revision of the ATtiny43U device. 8.1 8.1.1 ATtiny43U Rev. C • Increased Probability of Boost Converter Entering Active Low Current Mode 1. Increased Probability of Boost Converter Entering Active Low Current Mode The boost converter may enter and stay in Active Low Current Mode at supply voltages and load currents higher than those specified. This is due to high switching currents in bonding wires of the SOIC package. Devices packaged in MLF are not affected. Problem Fix / Workaround Add a 1.5nF capacitor between pins LSW and GND of the SOIC package. Also, increase the value of the by-pass capacitor between pins VCC and GND to at least 30µF. Alternatively, use the device in MLF, without modifications. 8.1.2 Rev. B Not sampled. 8.1.3 Rev. A Not sampled. 14 ATtiny43U 8048BS–AVR–03/09 9. Datasheet Revision History 9.1 Rev. 8048B-03/09 1. 9.2 Updated Data retention bullet in “Features” on page 1. Rev. 8048A-02/09 1. Initial revision. 15 8048BS–AVR–03/09 Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Technical Support [email protected] Sales Contact www.atmel.com/contacts Product Contact Web Site www.atmel.com Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 8048BS–AVR–03/09