240pin DDR3 SDRAM Unbuffered DIMMs
DDR3 SDRAM Unbuffered DIMMs
Based on 1Gb B version
HMT164U6BFR6C
HMT112U6BFR8C
HMT112U7BFR8C
HMT125U6BFR8C
HMT125U7BFR8C
** Contents are subject to change without prior notice.
Rev. 0.1 / Apr 2009
1
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
Revision History
Revision No.
History
Draft Date
Remark
0.01
Initial draft for internal review
Dec. 2008
Preliminary
0.02
Added IDD Specification
Feb. 2009
Preliminary
0.1
Updated IDD Specification
Apr. 2009
Rev. 0.1 / Apr 2009
2
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
Table of Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Features
1.1.2 Ordering Information
1.2 Speed Grade & Key Parameters
1.3 Address Table
2. Pin Architecture
2.1 Pin Definition
2.2 Input/Output Functional Description
2.3 Pin Assignment
3. Functional Block Diagram
3.1 512MB, 64Mx64 Module(1Rank of x16)
3.2 1GB, 128Mx64 Module(1Rank of x8)
3.3 1GB, 128Mx72 ECC Module(1Rank of x8)
3.4 2GB, 256Mx64 Module(2Rank of x8)
3.5 2GB, 256Mx72 ECC Module(2Rank of x8)
4. Address Mirroring Feature
4.1 DRAM Pin Wiring for Mirroring
5. Absolute Maximum Ratings
5.1 Absolute Maximum DC Ratings
5.2 Operating Temperature Range
6. AC & DC Operating Conditions
6.1 Recommended DC Operating Conditions
6.2 DC & AC Logic Input Levels
6.2.1 For Single-ended Signals
6.2.2 For Differential Signals
6.2.3 Differential Input Cross Point
6.3 Slew Rate Definition
6.3.1 For Ended Input Signals
6.3.2 For Differential Input Signals
6.4 DC & AC Output Buffer Levels
6.4.1 Single Ended DC & AC Output Levels
6.4.2 Differential DC & AC Output Levels
6.4.3 Single Ended Output Slew Rate
6.4.4 Differential Ended Output Slew Rate
6.5 Overshoot/Undershoot Specification
6.6 Input/Output Capacitance & AC Parametrics
6.7 IDD Specifications & Measurement Conditions
7. Electrical Characteristics and AC Timing
7.1 Refresh Parameters by Device Density
7.2 DDR3 Standard speed bins and AC para
8. DIMM Outline Diagram
8.1 512MB, 64Mx64 Module(1Rankx16)
8.2 1GB, 128Mx64 Module(1Rank of x8)
8.3 1GB, 128Mx72 ECC Module(1Rank of x8)
8.4 2GB, 256Mx64 Module(2Rank of x8)
8.5 2GB, 256Mx72 ECC Module(2Rank of x8)
Rev. 0.1 / Apr 2009
3
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
1. Description
This Hynix unbuffered Dual In-Line Memory Module(DIMM) series consists of 1Gb B version. DDR3 SDRAMs in Fine
Ball Grid Array(FBGA) packages on a 240 pin glass-epoxy substrate. This DDR3 Unbuffered DIMM series based on 1Gb
B ver. provide a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable
for easy interchange and addition.
1.1 Device Features & Ordering Information
1.1.1 Features
• VDD=VDDQ=1.5V
• VDDSPD=3.3V to 3.6V
• Fully differential clock inputs (CK, /CK) operation
• Differential Data Strobe (DQS, /DQS)
• On chip DLL align DQ, DQS and /DQS transition with
CK transition
• DM masks write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges of
the clock
• Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11)
supported
• Programmable burst length 4/8 with both nibble
sequential and interleave mode
• BL switch on the fly
• 8banks
• 8K refresh cycles /64ms
• DDR3 SDRAM Package: JEDEC standard 78ball
FBGA(x4/x8), 96ball FBGA(x16) with support balls
• Driver strength selected by EMRS
• Dynamic On Die Termination supported
• Asynchronous RESET pin supported
• ZQ calibration supported
• TDQS (Termination Data Strobe) supported (x8 only)
• Programmable additive latency 0, CL-1, and CL-2 sup
ported
• Write Levelization supported
• Programmable CAS Write latency (CWL) = 5, 6, 7, 8
• On Die Thermal Sensor supported (JEDEC optional)
Rev. 0.1 / Apr 2009
• Auto Self Refresh supported
4
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
1.1.2 Ordering Information
Part Name
Density
Org.
# of
DRAMs
# of
ranks
Materials
ECC
TS
HMT164U6BFR6C - G7/H9
512MB
64Mx64
4
1
Halogen-free
None
No
HMT112U6BFR8C - G7/H9
1GB
128Mx64
8
1
Halogen-free
None
No
HMT112U7BFR8C - G7/H9
1GB
128Mx72
9
1
Halogen-free
ECC
Yes
HMT125U6BFR8C - G7/H9
2GB
256Mx64
16
2
Halogen-free
None
No
HMT125U7BFR8C - G7/H9
2GB
256Mx72
18
2
Halogen-free
ECC
Yes
Rev. 0.1 / Apr 2009
5
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
1.2 Speed Grade & Key Parameters
MT/S
1066
DDR3-1333
Grade
-G7
-H9
tCK(min)
1.875
1.5
ns
CAS Latency
7
9
tCK
tRCD(min)
13.125
13.5
ns
tRP(min)
13.125
13.5
ns
tRAS(min)
37.5
36
ns
tRC(min)
50.625
49.5
ns
CL-tRCD-tRP
7-7-7
9-9-9
tCK
Unit
1.3 Address Table
512MB
1GB
1GB
2GB
2GB
Organization
64M x 64
128M x 64
128M x 72
256M x 64
256M x 72
Refresh Method
8K/64ms
8K/64ms
8K/64ms
8K/64ms
8K/64ms
Row Address
A0-A12
A0-A13
A0-A13
A0-A13
A0-A13
Column Address
A0-A9
A0-A9
A0-A9
A0-A9
A0-A9
Bank Address
BA0-BA2
BA0-BA2
BA0-BA2
BA0-BA2
BA0-BA2
Page Size
2KB
1KB
1KB
1KB
1KB
# of Rank
1
1
1
2
2
# of Device
4
8
9
16
18
Rev. 0.1 / Apr 2009
6
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
2. Pin Architecture
2.1 Pin Definition
Pin Name
Description
Pin Name
Description
I2C serial bus clock for EEPROM
A0–A13
SDRAM address bus
SCL
BA0–BA2
SDRAM bank select
SDA
I2C serial bus data line for EEPROM
SA0–SA2
I2C slave address select for EEPROM
RAS
SDRAM row address strobe
CAS
SDRAM column address strobe
WE
SDRAM write enable
VDDQ*
DIMM Rank Select Lines
VREFDQ
SDRAM I/O reference supply
VREFCA
SDRAM command/address reference
supply
S0–S1
CKE0–CKE1
SDRAM clock enable lines
ODT0–ODT1
On-die termination control lines
DQ0–DQ63
CB0–CB7
DIMM memory data bus
DIMM ECC check bits
VDD*
VSS
VDDSPD
NC
SDRAM core power supply
SDRAM I/O Driver power supply
Power supply return (ground)
Serial EEPROM positive power supply
Spare pins (no connect)
DQS0–DQS8
SDRAM data strobes
(positive line of differential pair)
TEST
Memory bus analysis tools
(unused on memory DIMMS)
DQS0–DQS8
SDRAM data strobes
(negative line of differential pair)
RESET
Set DRAMs to Known State
DM0–DM8
SDRAM data masks/high data strobes
(x8-based x72 DIMMs)
VTT
SDRAM I/O termination supply
CK0–CK1
SDRAM clocks
(positive line of differential pair)
RFU
Reserved for future use
CK0–CK1
SDRAM clocks
(negative line of differential pair)
-
-
*The VDD and VDDQ pins are tied common to a single power-plane on these designs
Rev. 0.1 / Apr 2009
7
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
2.2 Input/Output Functional Description
Symbol
Type
Polarity
Function
CK0–CK1
CK0–CK1
SSTL
Differential
crossing
CK and CK are differential clock inputs. All the DDR3 SDRAM addr/cntl
inputs are sampled on the crossing of positive edge of CK and negative
edge of CK. Output (read) data is reference to the crossing of CK and CK
(Both directions of crossing).
CKE0–CKE1
SSTL
Active High
Activates the SDRAM CK signal when high and deactivates the CK signal
when low. By deactivating the clocks, CKE low initiates the Power Down
mode, or the Self Refresh mode.
S0–S1
SSTL
Active Low
Enables the associated SDRAM command decoder when low and disables
the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. This
signal provides for external rank selection on systems with multiple ranks.
RAS, CAS, WE
SSTL
Active Low
RAS, CAS, and WE (ALONG WITH S) define the command being entered.
ODT0–ODT1
SSTL
Active High
When high, termination resistance is enabled for all DQ, DQS, DQS and DM
pins, assuming this function is enabled in the Mode Register 1 (MR1).
VREFDQ
Supply
Reference voltage for SSTL15 I/O inputs.
VREFCA
Supply
Reference voltage for SSTL 15 command/address inputs.
VDDQ
Supply
Power supply for the DDR3 SDRAM output buffers to provide improved
noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ
shares the same power plane as VDD pins.
BA0–BA2
SSTL
—
Selects which SDRAM bank of eight is activated.
During a Bank Activate command cycle, Address input defines the row
address (RA0–RA15).
A0–A13
SSTL
—
DQ0–DQ63,
CB0–CB7
SSTL
—
DM0–DM8
SSTL
VDD, VSS
Supply
Rev. 0.1 / Apr 2009
Active High
During a Read or Write command cycle, Address input defines the column
address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high,
autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1, BA2 to control which
bank(s) to precharge. If AP is high, all banks will be precharged regardless
of the state of BA0, BA1 or BA2. If AP is low, BA0, BA1 and BA2 are used to
define which bank to precharge. A12(BC) is sampled during READ and
WRITE commands to determine if burst chop (on-the-fly) will be performed (HIGH, no burst chop; LOW, burst chopped).
Data and Check Bit Input/Output pins.
DM is an input mask signal for write data. Input data is masked when DM
is sampled High coincident with that input data during a write access. DM
is sampled on both edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading.
Power and ground for the DDR3 SDRAM input buffers, and core logic. VDD
and VDDQ pins are tied to VDD/VDDQ planes on these modules.
8
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
Symbol
Type
Polarity
DQS0–DQS8
DQS0–DQS8
SSTL
Differential
crossing
Function
Data strobe for input and output data.
SA0–SA2
—
These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range.
SDA
—
This bidirectional pin is used to transfer data into or out of the SPD
EEPROM. An external resistor may be connected from the SDA bus line to
VDDSPD to act as a pullup on the system board.
SCL
—
This signal is used to clock data into and out of the SPD EEPROM. An
external resistor may be connected from the SCL bus time to VDDSPD to act
as a pullup on the system board.
VDDSPD
Power supply for SPD EEPROM. This supply is separate from the VDD/VDDQ
power plane. EEPROM supply is operable from 3.0V to 3.6V.
Supply
2.3 Pin Assignment
Front Side(left 1–60)
Pin
x64
# Non-ECC
x72
ECC
Back Side(right 121–180)
Front Side(left 61–120) Back Side(right 181–240)
Pin
x64
# Non-ECC
x72
ECC
Pin
#
x64
Non-ECC
x72
ECC
Pin
#
x64
Non-ECC
x72
ECC
VSS
VSS
61
A2
A2
181
A1
A1
1
VREFDQ
2
VSS
VSS
122
DQ4
DQ4
62
VDD
VDD
182
VDD
VDD
3
DQ0
DQ0
123
DQ5
DQ5
63
CK1
CK1
183
VDD
VDD
4
DQ1
DQ1
124
VSS
VSS
64
CK1
CK1
184
CK0
CK0
5
VSS
VSS
125
DM0
DM0
65
VDD
VDD
185
CK0
CK0
6
DQS0
DQS0
126
NC
NC
66
VDD
VDD
186
VDD
VDD
7
DQS0
DQS0
127
VSS
VSS
67
VREFCA
VREFCA
187
NC
NC
8
VSS
VSS
128
DQ6
DQ6
68
NC
NC
188
A0
A0
9
DQ2
DQ2
129
DQ7
DQ7
69
VDD
VDD
189
VDD
VDD
BA12
VREFDQ 121
10
DQ3
DQ3
130
VSS
VSS
70
A10
A10
190
BA12
11
VSS
VSS
131
DQ12
DQ12
71
BA02
BA02
191
VDD
VDD
12
DQ8
DQ8
132
DQ13
DQ13
72
VDD
VDD
192
RAS
RAS
13
DQ9
DQ9
133
VSS
VSS
73
WE
WE
193
S0
S0
14
VSS
VSS
134
DM1
DM1
74
CAS
CAS
194
VDD
VDD
15
DQS1
DQS1
135
NC
NC
75
VDD
VDD
195
ODT0
ODT0
16
DQS1
DQS1
136
VSS
VSS
76
S1
S1
196
A13
A13
NC = No Connect; RFU = Reserved Future Use
1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.
2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more
information on mirrored addresses.
Rev. 0.1 / Apr 2009
9
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
Front Side(left 1–60)
Back Side(right 121–180)
Front Side(left 61–120) Back Side(right 181–240)
Pin
x64
# Non-ECC
x72
ECC
Pin
x64
# Non-ECC
x72
ECC
Pin
#
x64
Non-ECC
x72
ECC
Pin
#
x64
Non-ECC
x72
ECC
17
VSS
VSS
137
DQ14
DQ14
77
ODT1
ODT1
197
VDD
VDD
18
DQ10
DQ10
138
DQ15
DQ15
78
VDD
VDD
198
NC
NC
19
DQ11
DQ11
139
VSS
VSS
79
NC
NC
199
VSS
VSS
20
VSS
VSS
140
DQ20
DQ20
80
VSS
VSS
200
DQ36
DQ36
21
DQ16
DQ16
141
DQ21
DQ21
81
DQ32
DQ32
201
DQ37
DQ37
22
DQ17
DQ17
142
VSS
VSS
82
DQ33
DQ33
202
VSS
VSS
23
VSS
VSS
143
DM2
DM2
83
VSS
VSS
203
DM4
DM4
24
DQS2
DQS2
144
NC
NC
84
DQS4
DQS4
204
NC
NC
25
DQS2
DQS2
145
VSS
VSS
85
DQS4
DQS4
205
VSS
VSS
26
VSS
VSS
146
DQ22
DQ22
86
VSS
VSS
206
DQ38
DQ38
27
DQ18
DQ18
147
DQ23
DQ23
87
DQ34
DQ34
207
DQ39
DQ39
28
DQ19
DQ19
148
VSS
VSS
88
DQ35
DQ35
208
VSS
VSS
29
VSS
VSS
149
DQ28
DQ28
89
VSS
VSS
209
DQ44
DQ44
30
DQ24
DQ24
150
DQ29
DQ29
90
DQ40
DQ40
210
DQ45
DQ45
31
DQ25
DQ25
151
VSS
VSS
91
DQ41
DQ41
211
VSS
VSS
32
VSS
VSS
152
DM3
DM3
92
VSS
VSS
212
DM5
DM5
33
DQS3
DQS3
153
NC
NC
93
DQS5
DQS5
213
NC
NC
34
DQS3
DQS3
154
VSS
VSS
94
DQS5
DQS5
214
VSS
VSS
35
VSS
VSS
155
DQ30
DQ30
95
VSS
VSS
215
DQ46
DQ46
36
DQ26
DQ26
156
DQ31
DQ31
96
DQ42
DQ42
216
DQ47
DQ47
37
DQ27
DQ27
157
VSS
VSS
97
DQ43
DQ43
217
VSS
VSS
38
VSS
VSS
158
NC
CB4
98
VSS
VSS
218
DQ52
DQ52
39
NC
CB0
159
NC
CB5
99
DQ48
DQ48
219
DQ53
DQ53
40
NC
CB1
160
VSS
VSS
100
DQ49
DQ49
220
VSS
VSS
41
VSS
VSS
161
DM8
DM8
101
VSS
VSS
221
DM6
DM6
42
NC
DQS8
162
NC
NC
102
DQS6
DQS6
222
NC
NC
43
NC
DQS8
163
VSS
VSS
103
DQS6
DQS6
223
VSS
VSS
44
VSS
VSS
164
NC
CB6
104
VSS
VSS
224
DQ54
DQ54
45
NC
CB2
165
NC
CB7
105
DQ50
DQ50
225
DQ55
DQ55
46
NC
CB3
166
VSS
VSS
106
DQ51
DQ51
226
VSS
VSS
47
VSS
VSS
167
NC
NC
107
VSS
VSS
227
DQ60
DQ60
NC = No Connect; RFU = Reserved Future Use
1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.
2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more
information on mirrored addresses.
Rev. 0.1 / Apr 2009
10
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
Front Side(left 1–60)
Pin
x64
# Non-ECC
48
x72
ECC
NC
NC
Back Side(right 121–180)
Front Side(left 61–120) Back Side(right 181–240)
Pin
x64
# Non-ECC
x72
ECC
Pin
#
x64
Non-ECC
x72
ECC
Pin
#
x64
Non-ECC
x72
ECC
168
Reset
108
DQ56
DQ56
228
DQ61
DQ61
109
DQ57
DQ57
229
VSS
VSS
Reset
KEY
KEY
49
NC
NC
169
CKE1/NC
CKE1/NC
110
VSS
VSS
230
DM7
DM7
50
CKE0
CKE0
170
VDD
VDD
111
DQS7
DQS7
231
NC
NC
51
VDD
VDD
171
NC
NC
112
DQS7
DQS7
232
VSS
VSS
52
BA2
BA2
172
NC
NC
113
VSS
VSS
233
DQ62
DQ62
53
NC
NC
173
VDD
VDD
114
DQ58
DQ58
234
DQ63
DQ63
54
VDD
VDD
174
A12
A12
115
DQ59
DQ59
235
VSS
VSS
55
All
All
175
A9
A9
116
VSS
VSS
236
VDDSPD
VDDSPD
56
A72
A72
176
VDD
VDD
117
SA0
SA0
237
SA1
SA1
57
VDD
VDD
177
A82
A82
118
SCL
SCL
238
SDA
SDA
58
A52
A52
178
A62
A62
119
SA2
SA2
239
VSS
VSS
59
A42
A42
179
VDD
VDD
120
VTT
VTT
240
VTT
VTT
60
VDD
VDD
180
A32
A32
NC = No Connect; RFU = Reserved Future Use
1. NC pins should not be connected to anything on the DIMM, including bussing within the NC group.
2. Address pins A3–A8 and BA0 and BA1 can be mirrored or not mirrored. Please refer to Section 4.1 for more
information on mirrored addresses.
Rev. 0.1 / Apr 2009
11
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
3. Functional Block Diagram
3.1 512MB, 64Mx64 Module(1Rank of x16)
S0
DQS0
DQS0
DM0
DQS1
DQS1
DM1
DQS2
DQS2
DM2
DQS3
DQS3
DM3
CS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
UDQS
CS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQS4
DQS4
DM4
D0
DQS5
DQS5
DM5
ZQ
CS
DQS6
DQS6
DM6
CSD1
DQS7
DQS7
DM7
ZQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
UDQS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
UDQS
CS
UDQS
UDM
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
Serial PD
SCL
BA0–BA2
A0–A14
BA0–BA2: SDRAMs D0–D3
A0–A14: SDRAMs D0–D3
RAS
RAS: SDRAMs D0–D3
CAS
CAS: SDRAMs D0–D3
CKE0
CKE: SDRAMs D0–D3
WE
ODT0
WE: SDRAMs D0–D3
CK0
CK0
RESET
Rev. 0.1 / Apr 2009
ODT: SDRAMs D0–D3
CK: SDRAMs D0–D3
CK: SDRAMs D0–D3
RESET:SDRAMs D0-D3
VDDSPD
SDA
WP
A0
A1
A2
SA0
SA1
SA2
CS
LDQS
LDQS
LDM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
SPD
VDD/VDDQ
D0–D3
VREFDQ
D0–D3
VSS
D0–D3
VREFCA
D0–D3
D2
ZQ
CS
CSD3
ZQ
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown.
3. DQ,DM,DQS,DQS resistors;Refer to associated topology diagram.
4. Refer to the appropriate clock wiring
topology under the DIMM wiring details
section of this document.
5. The pair CK1 and CK1# is terminated in
75ohm but is not used on the module.
6. A15 is not routed on the module.
7. For each DRAM, a unique ZQ resistor is
connected to ground.The ZQ resistor is
240ohm+-1%
8. One SPD exists per module.
12
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
3.2 1GB, 128Mx64 Module(1Rank of x8)
S0
DQS0
DQS0
DM0
DQS1
DQS1
DM1
DQS2
DQS2
DM2
DQS3
DQS3
DM3
DQS4
DQS4
DM4
DM CS DQS DQS
0
1
D0
2
3
4
5
6
ZQ
7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM CS DQS DQS
I/O 0
I/O 1
D1
I/O 2
I/O 3
I/O 4
I/O 5
ZQ
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS DQS DQS
I/O 0
I/O 1
D3
I/O 2
I/O 3
I/O 4
I/O 5
ZQ
I/O 6
I/O 7
DQS5
DQS5
DM5
DQS6
DQS6
DM6
DM CS DQS DQS
0
1
D2
2
3
4
5
6
7
ZQ
DQS7
DQS7
DM7
BA0–BA2: SDRAMs D0–D7
A0–A15
A0–A15: SDRAMs D0–D7
RAS
RAS: SDRAMs D0–D7
CAS
CAS: SDRAMs D0–D7
CKE0
CKE: SDRAMs D0–D7
WE
ODT0
WE: SDRAMs D0–D7
CK0
CK0
CK: SDRAMs D0–D7
CK: SDRAMs D0–D7
RESET
ODT: SDRAMs D0–D7
RESET:SDRAMs D0-D7
Rev. 0.1 / Apr 2009
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
Serial PD
SCL
BA0–BA2
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
VDDSPD
VDD/VDDQ
SDA
WP
A0
A1
A2
SA0
SA1
SA2
SPD
D0–D7
VREFDQ
D0–D7
VSS
D0–D7
VREFCA
D0–D7
D4
ZQ
D5
ZQ
D6
ZQ
D7
ZQ
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown.
3. DQ,DM,DQS/DQS resistors;Refer to
associated topology diagram.
4. Refer to the appropriate clock wiring
topology under the DIMM wiring details
section of this document.
5. Refer to Section 3.1 of this document for
details on address mirroring.
6. For each DRAM, a unique ZQ resistor is
connected to ground.The ZQ resistor is
240ohm+-1%
7. One SPD exists per module.
13
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
3.3 1GB, 128Mx72 Module(1Rank of x8)
S0
DQS0
DQS0
DM0
DQS1
DQS1
DM1
DQS2
DQS2
DM2
DQS3
DQS3
DM3
DQS8
DQS8
DM8
BA0–BA2
A0–A15
RAS
CAS
CKE0
WE
ODT0
CK0
CK0
RESET
DQS4
DQS4
DM4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
D0
ZQ
DQS5
DQS5
DM5
DQS DQS
D1
ZQ
DQS6
DQS6
DM6
DQS DQS
D2
ZQ
DQS7
DQS7
DM7
DQS DQS
D3
ZQ
D8
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
SPD(TS integrated)
SCL
EVENT
ZQ
BA0–BA2: SDRAMs D0–D8
A0–A15: SDRAMs D0–D8 VDDSPD
RAS: SDRAMs D0–D8
VDD/VDDQ
CAS: SDRAMs D0–D8
CKE: SDRAMs D0–D8
VREFDQ
WE: SDRAMs D0–D8
VSS
ODT: SDRAMs D0–D8
CK: SDRAMs D0–D8
V
REFCA
CK: SDRAMs D0–D8
RESET:SDRAMs D0-D8
Rev. 0.1 / Apr 2009
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
EVENT
SDA
A0
A1
A2
SA0
SA1
SA2
SPD
D0–D8
D0–D8
D0–D8
D0–D8
DQS DQS
D4
ZQ
D5
ZQ
DQS DQS
D6
ZQ
DQS DQS
D7
ZQ
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as
shown.
3. DQ,CB,DM,DQS/DQS resistors;Refer
to associated topology diagram.
4. Refer to the appropriate clock wiring
topology under the DIMM wiring
details section of this document.
5. For each DRAM, a unique ZQ resistor
is connected to ground.The ZQ resistor is 240ohm+-1%
6. One SPD exists per module.
14
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
3.4 2GB, 256Mx64 Module(2Rank of x8)
S1
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS DQS DQS
D0
ZQ
DQS1
DQS1
DM1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
D1
ZQ
DQS2
DQS2
DM2
DQS3
DQS3
DM3
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
ZQ
CS DQS DQS
D3
ZQ
DM CS DQS DQS
I/O 0
I/O 1
D8
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
ZQ
I/O 7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS DQS DQS
I/O 0
I/O 1
D4
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS DQS DQS
I/O 0
I/O 1
D12
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS DQS DQS
I/O 0
I/O 1
D5
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS DQS DQS
I/O 0
I/O 1
D13
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS DQS DQS
I/O 0
I/O 1
D6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS DQS DQS
I/O 0
I/O 1
D14
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS DQS DQS
I/O 0
I/O 1
D7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM CS DQS DQS
I/O 0
I/O 1
D15
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS5
DQS5
DM5
DM CS DQS DQS
I/O 0
I/O 1
D9
I/O 2
I/O 3
I/O 4
I/O 5
ZQ
I/O 6
I/O 7
DQS6
DQS6
DM6
DM CS DQS DQS
I/O 0
I/O 1
D10
I/O 2
I/O 3
I/O 4
I/O 5
ZQ
I/O 6
I/O 7
RESET
ZQ
ZQ
ZQ
DQS7
DQS7
DM7
DM CS DQS DQS
I/O 0
I/O 1
D11
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
ZQ
I/O 7
Serial PD
BA0–BA2
A0–A15
CKE1
CKE0
RAS
CAS
WE
ODT0
ODT1
CK0
CK0
CK1
CK1
ZQ
BA0–BA2: SDRAMs D0–D15 SCL
A0-A15: SDRAMs D0–D15
WP
CKE: SDRAMs D8–D15
A0
CKE: SDRAMs D0–D7
SA0
RAS: SDRAMs D0–D15
CAS: SDRAMs D0–D15
VDDSPD
WE: SDRAMs D0–D15
VDD/VDDQ
ODT: SDRAMs D0–D7
VREFDQ
ODT: SDRAMs D8–D15
CK: SDRAMs D0–D7
VSS
CK: SDRAMs D0–D7
VREFCA
CK: SDRAMs D8–D15
CK: SDRAMs D8–D15
SDA
A1
A2
SA1
SA2
SPD
D0–D15
D0–D15
D0–D15
D0–D15
ZQ
ZQ
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown.
3. DQ,DM,DQS,DQS resistors;Refer to
associated topology diagram.
4. Refer to Section 3.1 of this document for
details on address mirroring.
5. For each DRAM, a unique ZQ resistor is
connected to ground.The ZQ resistor is
240ohm+-1%
6. One SPD exists per module.
RESET:SDRAMs D0-D3
Rev. 0.1 / Apr 2009
15
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
3.5 2GB, 256Mx72 Module(2Rank of x8)
DQS1
DQS1
DM1
S1
S0
DQS0
DQS0
DM0
DQS4
DQS4
DM4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS DQS DQS
I/O 0
I/O 1
D0
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM CS DQS DQS
I/O 0
I/O 1
D2
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM CS DQS DQS
I/O 0
I/O 1
D3
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
DQS2
DQS2
DM2
DQS3
DQS3
DM3
D1
ZQ
ZQ
DQS5
DQS5
DM5
D10
ZQ
DQS6
DQS6
DM6
D11
ZQ
DQS7
DQS7
DM7
ZQ
DQS8
DQS8
DM8
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS DQS DQS
I/O 0
I/O 1
D5
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DM CS DQS DQS
I/O 0
I/O 1
D6
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS DQS DQS
I/O 0
I/O 1
D7
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
CS DQS DQS
D12
ZQ
ZQ
ZQ
VDDSPD
SPD(TS integrated)
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
ZQ
BA0-BA2: SDRAMs D0–D17
A0-A15: SDRAMs D0–D17
CKE: SDRAMs D0–D8
CKE: SDRAMs D9–D17
RAS: SDRAMs D0–D17
CAS: SDRAMs D0–D17
WE: SDRAMs D0–D17
Rev. 0.1 / Apr 2009
CS DQS DQS
ODT0
ODT1
CK0
CK0
CK1
CK1
RESET
D17
EVENT
EVENT
A0
SA0
SA1
A2
SA2
ZQ
ODT: SDRAMs D0–D8
ODT: SDRAMs D9–D17
CK: SDRAMs D0–D8
CK: SDRAMs D0–D8
CK: SDRAMs D9–D17
CK: SDRAMs D9–D17
RESET:SDRAMs D0-D17
ZQ
D14
ZQ
D15
ZQ
D16
ZQ
SPD
D0–D17
VREFDQ
D0–D17
Vss
D0–D17
VREFCA
D0–D17
SDA
A1
D13
VDD/VDDQ
SCL
DM CS DQS DQS
I/O 0
I/O 1
D8
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
BA0–BA2
A0–A15
CKE0
CKE1
RAS
CAS
WE
CS DQS DQS
D9
DM CS DQS DQS
I/O 0
I/O 1
D4
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS DQS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
Notes:
1. DQ-to-I/O wiring is shown as recommended but may be changed.
2. DQ/DQS/DQS/ODT/DM/CKE/S relationships must be maintained as shown.
3. DQ,CB,DM/DQS/DQS resistors;Refer to
associated topology diagram.
4. Refer to Section 3.1 of this document for
details on address mirroring.
5. For each DRAM, a unique ZQ resistor is
connected to ground.The ZQ resistor is
240ohm+-1%
6. One SPD exists per module.
16
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
4. Address Mirroring Feature
There is a via grid located under the SDRAMs for wiring the CA signals (address, bank address, command, and control
lines) to the SDRAM pins. The length of the traces from the via to the SDRAMs places limitations on the bandwidth of
the module. The shorter these traces, the higher the bandwidth. To extend the bandwidth of the CA bus for DDR3
modules, a scheme was defined to reduce the length of these traces.The pins on the SDRAM are defined in a manner
that allows for these short trace lengths. The CA bus pins in Columns 2 and 8, ignoring the mechanical support pins,
do not have any special functions (secondary functions). This allows the most flexibility with these pins. These are
address pins A3, A4, A5, A6, A7, A8 and bank address pins BA0 and BA1. Refer to Table . Rank 0 SDRAM pins are
wired straight, with no mismatch between the connector pin assignment and the SDRAM pin assignment. Some of the
Rank 1 SDRAM pins are cross wired as defined in the table. Pins not listed in the table are wired straight.
4.1 DRAM Pin Wiring for Mirroring
Connector Pin
SDRAM Pin
Rank 0
Rank 1
A3
A3
A4
A4
A4
A3
A5
A5
A6
A6
A6
A5
A7
A7
A8
A8
A8
A7
BA0
BA0
BA1
BA1
BA1
BA0
<Table 4.1: SDRAM Pin Wiring for Mirroring >
The table 4.1 illustrates the wiring in both the mirrored and non-mirrored case.
The lengths of the traces to the SDRAM pins, is obviously shorter. The via grid is smaller as well.
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No Mirroring
Mirroring
< Figure 4.1: Wiring Differences for Mirrored and Non-Mirrored Addresses >
Since the cross-wired pins have no secondary functions, there is no problem in normal operation. Any data written is
read the same way. There are limitations however. When writing to the internal registers with a "load mode" operation, the specific address is required. This requires the controller to know if the rank is mirrored or not. This requires a
few rules. Mirroring is done on 2 rank modules and can only be done on the second rank. There is not a requirement
that the second rank be mirrored. There is a bit assignment in the SPD that indicates whether the module has been
designed with the mirrored feature or not. See the DDR3 UDIMM SPD specification for these details. The controller
must read the SPD and have the capability of de-mirroring the address when accessing the second rank.
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5. ABSOLUTE MAXIMUM RATINGS
5.1 Absolute Maximum DC Ratings
Symbol
Parameter
VDD
VDDQ
VIN, VOUT
TSTG
Rating
Units
Notes
Voltage on VDD pin relative to Vss
- 0.4 V ~ 1.975 V
V
,3
Voltage on VDDQ pin relative to Vss
- 0.4 V ~ 1.975 V
V
,3
Voltage on any pin relative to Vss
- 0.4 V ~ 1.975 V
V
-55 to +100 ℃
℃
Storage Temperature
,2
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement
conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times;and VREF must be not greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
5.2 DRAM Component Operating Temperature Range
Symbol
TOPER
Parameter
Rating
Units
Notes
Normal Temperature Range
0 to 85
℃
,2
Extended Temperature Range
85 to 95
℃
1,3
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM.
For measurement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported.
During operation, the DRAM case temperature must be maintained between 0 - 85oC under all operating
conditions
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85°… and
95°… case temperature.
Full specifications are guaranteed in this range, but the following additional conditions apply:
a) Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs.
(This double refresh requirement may not apply for some devices.) It is also possible to specify a component
with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range. Please refer to supplier data sheet and/
or the DIMM SPD for option avail ability.
b) If Self-Refresh operation is required in the Extended Temperature Range, than it is mandatory to either use the
Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0band MR2 A7 = 1b) or
enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).
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6. AC & DC Operating Conditions
6.1 Recommended DC Operating Conditions
Symbol
Parameter
VDD
VDDQ
Rating
Units
Notes
1.575
V
1,2
1.575
V
1,2
Min.
Typ.
Max.
Supply Voltage
1.425
1.500
Supply Voltage for Output
1.425
1.500
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD abd VDDQ tied together.
6.2 DC & AC Logic Input Levels
6.2.1 DC & AC Logic Input Levels for Single-Ended Signals
DDR3-1066, DDR3-1333
Symbol
Parameter
Unit
Notes
-
V
1, 2
Vref - 0.100
V
1, 2
-
V
1, 2
Vref - 0.175
V
1, 2
Min
Max
Vref + 0.100
VIH(DC)
DC input logic high
VIL(DC)
DC input logic low
VIH(AC)
AC input logic high
VIL(AC)
AC input logic low
VRefDQ(DC)
Reference Voltage for
DQ, DM inputs
0.49 * VDD
0.51 * VDD
V
3, 4
VRefCA(DC)
Reference Voltage for
ADD, CMD inputs
0.49 * VDD
0.51 * VDD
V
3, 4
VTT
Termination voltage for
DQ, DQS outputs
VDDQ/2 - TBD
VDDQ/2 + TBD
V
Vref + 0.175
1. For DQ and DM, Vref = VrefDQ. For input ony pins except RESET#, Vref = VrefCA.
2. The “t.b.d.” entries might change based on overshoot and undershoot specification.
3. The ac peak noise on VRef may not allow VRef to deviate from VRef(DC) by more than +/-1% VDD
(for reference: approx. +/- 15 mV).
For reference: approx. VDD/2 +/- 15 mV.
The dc-tolerance limits and ac-noise limits for the reference voltages VRefCA and VRefDQ are illustrated in figure
6.2.1. It shows a valid reference voltage VRef(t) as a function of time. (VRef stands for VRefCA and VRefDQ likewise).VRef(DC) is the linear average of VRef(t) over a very long period of time (e.g. 1 sec). This average has to meet
the min/max requirements in Table 1. Furthermore VRef(t) may temporarily deviate from VRef(DC) by no more than
+/- 1% VDD.
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voltage
VDD
VRef(t)
VRef ac-noise
VRef(DC)max
VRef(DC)
VDD/2
VRef(DC)min
VSS
time
< Figure 6.2.1: Illustration of Vref(DC) tolerance and Vref AC-noise limits >
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on
VRef. "VRef " shall be understood as VRef(DC), as defined in Figure 6.2.1
This clarifies, that dc-variations of VRef affect the absolute voltage a signal has to reach to achieve a valid high or low
level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account
for VRef(DC) deviations from the optimum position within the data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VRef ac-noise. Timing and voltage effects due to ac-noise on VRef up to the specified limit (+/-1% of VDD)
are included in DRAM timings and their associated deratings.
6.2.2 DC & AC Logic Input Levels for Differential Signals
Symbol
Parameter
VIHdiff
Differential input logic high
VILdiff
Differential input logic low
DDR3-1066, DDR3-1333
Unit
Notes
-
V
1
- 0.200
V
1
Min
Max
+ 0.200
Note1:
Refer to “Overshoot and Undershoot Specification section 6.5 on 26 page
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6.2.3 Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each
cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the requirements in Table 6.2.3
The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to
the midlevel between of VDD and VSS.
VDD
CK#, DQS#
VIX
VDD/2
VIX
VIX
CK, DQS
VSS
< Figure 6.2.3 Vix Definition >
DDR3-1066, DDR3-1333
Symbol
VIX
Parameter
Differential Input Cross Point
Voltage relative to VDD/2
Unit
Min
Max
- 150
+ 150
Notes
mV
< Table 6.2.3: Cross point voltage for differential input signals (CK, DQS) >
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6.3 Slew Rate Definitions
6.3.1 For Single Ended Input Signals
- Input Slew Rate for Input Setup Time (tIS) and Data Setup Time (tDS)
Setup (tIS and tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VRef
and the first crossing of VIH(AC)min. Setup (tIS and tDS) nominal slew rate for a falling signal is defined as the slew
rate between the last crossing of VRef and the first crossing of VIL(AC)max.
- Input Slew Rate for Input Hold Time (tIH) and Data Hold Time (tDH)
Hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and
the first crossing of VRef. Hold (tIH and tDH) nominal slew rate for a falling signal is defined as the slew rate
between the last crossing of VIH(DC)min and the first crossing of VRef.
Measured
Description
Input slew rate for rising edge
Min
Max
Vref
VIH(AC)min
Input slew rate for falling edge
Vref
VIL(AC)max
Input slew rate for rising edge
VIL(DC)max
Vref
Input slew rate for falling edge
VIH(DC)min
Vref
Defined by
Applicable for
VIH(AC)min-Vref
Delta TRS
Vref-VIL(AC)max
Setup
(tIS, tDS)
Delta TFS
Vref-VIL(DC)max
Delta TFH
VIH(DC)min-Vref
Hold
(tIH, tDH)
Delta TRH
< Table 6.3.1: Single-Ended Input Slew Rate Definition >
Part A: Set up
Single Ended input Voltage(DQ,ADD, CMD)
Delta TRS
vIH(AC)min
vIH(DC)min
vRefDQ or
vRefCA
vIL(DC)max
vIL(AC)max
Delta TFS
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P a rt B : H o ld
Single Ended input Voltage(DQ,ADD, CMD)
D e lta T R H
v IH (A C )m in
v IH (D C )m in
v R e fD Q o r
v R e fC A
v IL (D C )m a x
v IL (A C )m a x
D e lta T F H
< Figure 6.3.1: Input Nominal Slew Rate Definition for Single-Ended Signals >
6.3.2 Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown in below Table
and Figure .
Description
Differential input slew rate for rising edge
(CK-CK and DQS-DQS)
Differential input slew rate for falling edge
(CK-CK and DQS-DQS)
Measured
Min
Max
VILdiffmax
VIHdiffmin
VIHdiffmin
VILdiffmax
Defined by
VIHdiffmin-VILdiffmax
DeltaTRdiff
VIHdiffmin-VILdiffmax
DeltaTFdiff
Note:
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
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Differential Input Voltage (i.e. DQS-DQS; CK-CK)
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
D e lta
T R d iff
vIH d iffm in
0
vILd iffm a x
D e lta
T F d iff
< Figure 6.3.2: Differential Input Slew Rate Definition for DQS,DQS# and CK,CK# >
6.4 DC & AC Output Buffer Levels
6.4.1 Single Ended DC & AC Output Levels
Below table shows the output levels used for measurements of single ended signals.
Symbol
VOH(DC)
VOM(DC)
VOL(DC)
VOH(AC)
VOL(AC)
Parameter
DC output high measurement level
(for IV curve linearity)
DC output mid measurement level
(for IV curve linearity)
DC output low measurement level
(for IV curve linearity)
AC output high measurement level
(for output SR)
DDR3-1066, 1333
Unit
0.8 x VDDQ
V
0.5 x VDDQ
V
0.2 x VDDQ
V
VTT + 0.1 x VDDQ
V
Notes
1
AC output low measurement level
VTT - 0.1 x VDDQ
V
1
(for output SR)
1. The swing of ± 0.1 x VDDQ is based on approximately 50% of the static single ended output high or low swing
with a driver impedance of 40Ω and an effective test load of 25Ω to VTT = VDDQ / 2.
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6.4.2 Differential DC & AC Output Levels
Below table shows the output levels used for measurements of differential signals.
Symbol
VOHdiff
(AC)
Parameter
DDR3-1066, 1333
Unit
Notes
+ 0.2 x VDDQ
V
1
AC differential output high
measurement level (for output SR)
VOLdiff
(AC)
AC differential output low
- 0.2 x VDDQ
V
1
measurement level (for output SR)
1. The swing of °æ 0.2 x VDDQ is based on approximately 50% of the static differential output high
or low swingwith a driver impedance of 40ߟ and an effective test load of 25ߟ to VTT = VDDQ/2 at each of
the differential output
6.4.3 Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and
measured between VOL(AC) and VOH(AC) for single ended signals as shown in below Table and Figure 6.4.3.
Description
Measured
From
To
Single ended output slew rate for rising edge
VOL(AC)
VOH(AC)
Single ended output slew rate for falling edge
VOH(AC)
VOL(AC)
Defined by
VOH(AC)-VOL(AC)
DeltaTRse
VOH(AC)-VOL(AC)
DeltaTFse
Note:
Output slew rate is verified by design and characterization, and may not be subject to production test.
Single Ended Output Voltage(l.e.DQ)
D e lt a T R s e
vO H (A C )
V∏
vO L(A C )
D e lt a T F s e
< Figure 6.4.3: Single Ended Output Slew Rate Definition >
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Parameter
Symbol
Single-ended Output Slew Rate
SRQse
DDR3-1066
DDR3-1333
Min
Max
Min
Max
2.5
5
2.5
5
Units
V/ns
*** Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
For Ron = RZQ/7 setting
< Table 6.4.3: Output Slew Rate (single-ended) >
6.4.4 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in below Table and Figure 6.4.4
Description
Measured
Defined by
From
To
Differential output slew rate for rising edge
VOLdiff(AC)
VOHdiff(AC)
Differential output slew rate for falling edge
VOHdiff(AC)
VOLdiff(AC)
VOHdiff(AC)-VOLdiff(AC)
DeltaTRdiff
VOHdiff(AC)-VOLdiff(AC)
DeltaTFdiff
Note: Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output Voltage(i.e. DQS-DQS)
D e lta
T R d iff
v O H d iff(A C )
O
v O L d iff(A C )
D e lta
T F d iff
< Figure 6.4.4: Differential Output Slew Rate Definition >
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DDR3-1066
Parameter
Differential Output Slew Rate
Symbol
SRQdiff
DDR3-1333
Min
Max
Min
Max
5
10
5
10
Units
V/ns
***Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
diff: Differential Signals
For Ron = RZQ/7 setting
< Table 6.6.4: Differential Output Slew Rate >
6.5 Overshoot and Undershoot Specifications
6.5.1 Address and Control Overshoot and Undershoot Specifications
Description
Maximum peak amplitude allowed for
overshoot area (see Figure)
Maximum peak amplitude allowed for
undershoot area (see Figure)
Maximum overshoot area above VDD
(See Figure)
Maximum undershoot area below VSS
(See Figure)
Specification
DDR3-1066
DDR3-1333
0.4V
0.4V
0.4V
0.4V
0.5 V-ns
0.4 V-ns
0.5 V-ns
0.4 V-ns
< Table 6.5.1: AC Overshoot/Undershoot Specification for Address and Control Pins >
< Figure 6.5.1: Address and Control Overshoot and Undershoot Definition >
Maximum Amplitude
Overshoot Area
Volts
(V)
VDD
VSS
Undershoot Area
Maximum Amplitude
Time (ns)
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6.5.2 Clock,Data,Strobe and Mask Overshoot and Undershoot Specifications
Specification
Description
Maximum peak amplitude allowed for
overshoot area (see Figure)
Maximum peak amplitude allowed for
undershoot area (see Figure)
Maximum overshoot area above VDDQ
(See Figure)
Maximum undershoot area below VSSQ
(See Figure)
DDR3-1066
DDR3-1333
0.4V
0.4V
0.4V
0.4V
0.19 V-ns
0.15 V-ns
0.19 V-ns
0.15 V-ns
< Table 6.5.2: AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask >
M a x im u m A m p litu d e
O v e rsh o o t A re a
V o lts
(V )
VDDQ
VSSQ
U n d e rsh o o t A re a
M a x im u m A m p litu d e
T im e (n s)
C lo c k , D a ta S tro b e a n d M a sk O v e rsh o o t a n d U n d e rsh o o t D e fin itio n
< Figure 6.5.2: Clock, Data, Strobe and Mask Overshoot and Undershoot Definition >
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6.6 Pin Capacitance
Parameter
Symbol
Input/output capacitance
(DQ, DM, DQS, DQS#, TDQS, TDQS#)
DDR3-1066
DDR3-1333
Units Notes
Min
Max
Min
Max
CIO
1.5
3.0
1.5
2.5
pF
1,2,3
Input capacitance, CK and CK#
CCK
TBD
1.6
TBD
TBD
pF
2,3,5
Input capacitance delta
CK and CK#
CDCK
0
0.15
TBD
TBD
pF
2,3,4
CI
TBD
1.5
TBD
TBD
pF
2,3,6
CDDQS
0
0.20
TBD
TBD
pF
2,3,12
CDI_CTRL
-0.5
0.3
TBD
TBD
pF
2,3,7,8
-0.5
0.5
TBD
TBD
pF
2,3,9,1
0
-0.5
0.3
TBD
TBD
pF
2,3,11
Input capacitance
(All other input-only pins)
Input capacitance delta, DQS
and DQS#
Input capacitance delta
(All CTRL input-only pins)
Input capacitance delta
(All ADD/CMD input-only pins)
CDI_ADD_C
Input/output capacitance delta
(DQ, DM, DQS, DQS#)
MD
CDIO
Notes:
1. TDQS/TDQS# are not necessarily input function but since TDQS is sharing DM pin and the parasitic
characterization of TDQS/TDQS# should be close as much as possible, Cio&Cdio requirement is applied
(recommend deleting note or changing to “Although the DM, TDQS and TDQS# pins have different functions,
the loading matches DQ and DQS.”)
2. This parameter is not subject to production test. It is verified by design and characterization. Input capacitance is
measured according to JEP147(“PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK
ANALYZER(VNA)”) with VDD, VDDQ, VSS,VSSQ applied and all other pins floating (except the pin under test, CKE,
RESET# and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off.
3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here
4. Absolute value of CCK-CCK#.
5. The minimum CCK will be equal to the minimum CI.
6. Input only pins include: ODT, CS, CKE, A0-A15, BA0-BA2, RAS#, CAS#, WE#.
7. CTRL pins defined as ODT, CS and CKE.
8. CDI_CTRL=CI(CNTL) - 0.5 * CI(CLK) + CI(CLK#))
9. ADD pins defined as A0-A15, BA0-BA2 and CMD pins are defined as RAS#, CAS# and WE#.
10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK#))
11. CDIO=CIO(DQ) - 0.5*(CIO(DQS)+CIO(DQS#))
12. Absolute value of CIO(DQS) - CIO(DQS#)
6.7 IDD Specifications(TCASE: 0 to 95oC)
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512MB, 64M x 64 U-DIMM: HMT164U6BFR6C
Symbol
DDR3 1066
DDR3 1333
Unit
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD6TC
IDD7
400
500
200
200
40
140
200
280
140
780
780
720
40
48
48
840
420
520
220
220
40
140
220
300
160
860
860
720
40
48
48
1040
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
1GB, 128M x 64 U-DIMM: HMT112U6BFR8C
Symbol
DDR3 1066
DDR3 1333
Unit
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD6TC
IDD7
600
680
400
400
80
200
400
480
240
960
960
1360
80
96
96
1280
640
760
440
440
80
240
440
520
240
1080
1080
1360
80
96
96
1600
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Rev. 0.1 / Apr 2009
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1GB, 128M x 72 U-DIMM: HMT112U7BFR8C
Symbol
DDR3 1066
DDR3 1333
Unit
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD6TC
IDD7
675
765
450
450
90
225
450
540
270
1080
1080
1530
90
108
108
1440
720
855
495
495
90
270
495
585
270
1215
1215
1530
90
108
108
1800
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
2GB, 256M x 64 U-DIMM: HMT125U6BFR8C
Symbol
DDR3 1066
DDR3 1333
Unit
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD6TC
IDD7
1000
1080
800
800
160
400
800
960
480
1360
1360
1760
160
192
192
1680
1080
1200
880
880
160
480
880
1040
480
1520
1520
1800
160
192
192
2040
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Rev. 0.1 / Apr 2009
32
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
2GB, 256M x 72 U-DIMM: HMT125U7BFR8C
Symbol
DDR3 1066
DDR3 1333
Unit
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD6TC
IDD7
1125
1215
900
900
180
450
900
1080
540
1530
1530
1980
180
216
216
1890
1215
1350
990
990
180
540
990
1170
540
1710
1710
2025
180
216
216
2295
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Rev. 0.1 / Apr 2009
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HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
6.7 IDD Measurement Conditionss
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 1. shows the
setup and test load for IDD and IDDQ measurements.
•
IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W,
IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the
DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
•
IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of
the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to
support correlation of simulated IO power to actual IO power as outlined in Figure 2. In DRAM module application,
IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
•
”0” and “LOW” is defined as VIN <= VILAC(max).
•
”1” and “HIGH” is defined as VIN >= VIHAC(max).
•
“FLOATING” is defined as inputs are VREF - VDD/2.
•
Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1 on Page 26.
•
Basic IDD and IDDQ Measurement Conditions are described in Table 2 on page 26.
•
Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 on page 30 through Table 10 on
page 36.
•
IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0B (Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
•
Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual
IDD or IDDQ measurement is started.
•
Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
•
Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
Rev. 0.1 / Apr 2009
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HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
IDDQ (optional)
IDD
VDD
VDDQ
RESET
CK/CK
DDR3
SDRAM
CKE
CS
RAS, CAS, WE
A, BA
ODT
ZQ
VSS
DQS, DQS
DQ, DM,
TDQS, TDQS
RTT = 25 Ohm
VDDQ/2
VSSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above]
Application specific
memory channel
environment
Channel
IO Power
Simulation
IDDQ
Test Load
IDDQ
Simulation
IDDQ
Simulation
Correction
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported
by IDDQ Measurement
Rev. 0.1 / Apr 2009
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HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
DDR3-800
DDR3-1066
5-5-5
7-7-7
tCK
2.5
1.875
ns
CL
5
7
nCK
nRCD
5
7
nCK
nRC
20
27
nCK
nRAS
15
20
nCK
Symbol
Unit
5
7
nCK
x4/x8
16
20
nCK
x16
20
27
nCK
x4/x8
4
4
nCK
x16
4
6
nCK
nRFC -512Mb
36
48
nCK
nRFC-1 Gb
44
59
nCK
nRFC- 2 Gb
64
86
nCK
nRFC- 4 Gb
120
160
nCK
nRFC- 8 Gb
140
187
nCK
nRP
nFAW
nRRD
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: High
IDD0
between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3 on
page 30; Data IO: FLOATING; DM: stable at 0; Bank Activity: Cycling with one bank active at a time:
0,0,1,1,2,2,... (see Table 3 on page 30); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
stable at 0; Pattern Details: see Table 3 on page 30
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS:
IDD1
High between ACT, RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling
according to Table 4 on page 31; DM: stable at 0; Bank Activity: Cycling with on bank active at a time:
0,0,1,1,2,2,... (see Table 4 on page 31); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
stable at 0; Pattern Details: see Table 4 page 31
Rev. 0.1 / Apr 2009
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HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command,
IDD2N
Address, Bank Address Inputs: partially toggling according to Table 5 on page 32; Data IO: FLOATING;
DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT
Signal: stable at 0; Pattern Details: see Table 5 on page 32
Precharge Standby ODT Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command,
IDD2NT Address, Bank Address Inputs: partially toggling according to Table 6 on page 32; Data IO: FLOATING;
DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT
Signal: toggling according to Table 6 on page 32; Pattern Details: see Table 6 on page 32
IDDQ2NT Precharge Standby ODT IDDQ Current
(optional Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current
)
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command,
IDD2P0
Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power
Down Mode: Slow Exitc)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command,
IDD2P1
Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Precharge Power
Down Mode: Fast Exitc)
Precharge Quiet Standby Current
IDD2Q
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks
closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
IDDQ4R Operating Burst Read IDDQ Current
(optional Same definition like for IDD4R, however measuring IDDQ current instead of IDD current
)
Rev. 0.1 / Apr 2009
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HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command,
IDD3N
Address, Bank Address Inputs: partially toggling according to Table 5 on page 32; Data IO: FLOATING;
DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT
Signal: stable at 0; Pattern Details: see Table 5 on page 32
Active Power-Down Current
IDD3P
CKE: Low; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM: stable at 0; Bank Activity: all banks
open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: High between RD;
Command, Address, Bank Address Inputs: partially toggling according to Table 7 on page 33; Data IO:
IDD4R
seamless read data burst with different data between one burst and the next one according to Table 7 on
page 33; DM: stable at 0; Bank Activity: all banks open, RD commands cycling through banks:
0,0,1,1,2,2,...(see Table 7 on page 33); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
stable at 0; Pattern Details: see Table 7 on page 33
Operating Burst Write Current
CKE: High; External clock: On; tCK, CL: see Table 1 on page 26; BL: 8a); AL: 0; CS: High between WR;
Command, Address, Bank Address Inputs: partially toggling according to Table 8 on page 34; Data IO:
IDD4W
seamless read data burst with different data between one burst and the next one according to Table 8 on
page 34; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks:
0,0,1,1,2,2,...(see Table 8 on page 34); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
stable at HIGH; Pattern Details: see Table 8 on page 34
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1 on page 26; BL: 8a); AL: 0; CS: High between
IDD5B
REF; Command, Address, Bank Address Inputs: partially toggling according to Table 9 on page 35; Data
IO: FLOATING; DM: stable at 0; Bank Activity: REF command every nREF (see Table 9 on page 35); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 9 on
page 35
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HMT125U6(7)BFR8C
Self-Refresh Current: Normal Temperature Range
TCASE: 0 - 85 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Normale);
IDD6
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 26; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING
Self-Refresh Current: Extended Temperature Range (optional)f)
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Disabledd);Self-Refresh Temperature Range (SRT): Extend-
IDD6ET
ede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 26; BL: 8a); AL: 0; CS,
Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Extended
Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal:
FLOATING
Auto Self-Refresh Current (optional)f)
TCASE: 0 - 95 oC; Auto Self-Refresh (ASR): Enabledd);Self-Refresh Temperature Range (SRT): Normale);
IDD6TC
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1 on page 26; BL: 8a); AL: 0; CS, Command, Address, Bank Address Inputs, Data IO: FLOATING; DM: stable at 0; Bank Activity: Auto SelfRefresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1 on page 26; BL:
8a); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially tog-
IDD7
gling according to Table 10 on page 36; Data IO: read data burst with different data between one burst and
the next one according to Table 10 on page 36; DM: stable at 0; Bank Activity: two times interleaved
cycling through banks (0, 1,...7) with different addressing, wee Table 10 on page 36; Output Buffer and
RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 10 on page 36
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B
b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B;
RTT_Wr enable: set MR2 A[10,9] = 10B
c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit
d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature
e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range
f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported
by DDR3 SDRAM device
Rev. 0.1 / Apr 2009
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HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
0
ACT
0
0
1
1
0
0
00
0
0
0
0
-
1,2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
D, D
1
1
1
1
0
0
00
0
0
0
0
-
0
0
0
-
0
F
0
-
0
-
0
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 3 - IDD0 Measurement-Loop Patterna)
3,4
...
nRAS
...
Static High
toggling
1*nRC+0
...
1*nRC+nRAS
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
repeat pattern 1...4 until nRC - 1, truncate if necessary
ACT
0
0
1
1
0
00
00
0
repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
0
...
repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
1
2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
F
a) DM must be driven LOW all the time. DQS, DQS are FLOATING.
b) DQ signals are FLOATING.
Rev. 0.1 / Apr 2009
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HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
0
A[2:0]
A[6:3]
A[9:7]
A[10]
A[15:11]
BA[2:0]
ODT
WE
CAS
RAS
CS
ACT
0
0
1
1
0
0
00
0
0
0
0
-
1,2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
3,4
D, D
1
1
1
1
0
0
00
0
0
0
0
-
0
0
0
0000000
0
0
0
0
-
nRCD
...
nRAS
...
Static High
Datab)
0
...
toggling
Command
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 4 - IDD1 Measurement-Loop Patterna)
repeat pattern 1...4 until nRCD - 1, truncate if necessary
RD
0
1
0
1
0
0
00
0
repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
repeat pattern 1...4 until nRC - 1, truncate if necessary
1*nRC+0
ACT
0
0
1
1
0
0
00
0
0
F
0
-
1*nRC+1,2
D, D
1
0
0
0
0
0
00
0
0
F
0
-
D, D
1
1
1
1
0
0
00
0
0
F
0
-
1*nRC+3,4
...
1*nRC+nRCD
...
1*nRC+nRAS
repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
RD
0
1
0
1
0
0
00
0
0
F
0
0011001
1
repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
PRE
0
0
1
0
0
0
00
0
0
F
...
repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary
1
2*nRC
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
4*nRC
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
6*nRC
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
8*nRC
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
10*nRC
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
12*nRC
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
14*nRC
repeat Sub-Loop 0, use BA[2:0] = 7 instead
0
-
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.1 / Apr 2009
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HMT125U6(7)BFR8C
0
Static High
A[2:0]
A[6:3]
A[9:7]
A[10]
A[15:11]
BA[2:0]
ODT
WE
CAS
RAS
CS
Datab)
0
D
1
0
0
0
0
0
0
0
0
0
0
-
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2
D
1
1
1
1
0
0
0
0
0
F
0
-
D
1
1
1
1
0
0
0
0
0
F
0
-
3
toggling
Command
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 5 - IDD2N and IDD3N Measurement-Loop Patterna)
1
4-7
repeat Sub-Loop 0, use BA[2:0] = 1 instead
2
8-11
repeat Sub-Loop 0, use BA[2:0] = 2 instead
3
12-15
repeat Sub-Loop 0, use BA[2:0] = 3 instead
4
16-19
repeat Sub-Loop 0, use BA[2:0] = 4 instead
5
20-23
repeat Sub-Loop 0, use BA[2:0] = 5 instead
6
24-17
repeat Sub-Loop 0, use BA[2:0] = 6 instead
7
28-31
repeat Sub-Loop 0, use BA[2:0] = 7 instead
a) DM must be driven LOW all the time. DQS, DQS are FLOATING.
b) DQ signals are FLOATING.
Command
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
Datab)
0
D
1
0
0
0
0
0
0
0
0
0
0
-
1
D
1
0
0
0
0
0
0
0
0
0
0
-
2
D
1
1
1
1
0
0
0
0
0
F
0
-
0
0000000
0
0
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Patterna)
Static High
toggling
3
D
1
1
1
1
0
0
0
1
4-7
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1
2
8-11
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
3
12-15
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3
4
16-19
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4
5
20-23
repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5
6
24-17
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6
7
28-31
repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7
0
0
F
a) DM must be driven LOW all the time. DQS, DQS are FLOATING.
b) DQ signals are FLOATING.
Rev. 0.1 / Apr 2009
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HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
Static High
toggling
1
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
Command
0
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 7 - IDD4R and IDDQ24RMeasurement-Loop Patterna)
Datab)
RD
0
1
0
1
0
0
00
0
0
0
0
000000
00
D
1
0
0
0
0
0
00
0
0
0
0
-
2,3
D,D
1
1
1
1
0
0
00
0
0
0
0
-
4
RD
0
1
0
1
0
0
00
0
0
F
0
001100
11
5
D
1
0
0
0
0
0
00
0
0
F
0
-
D,D
1
1
1
1
0
0
00
0
0
F
0
-
6,7
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.1 / Apr 2009
43
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
Static High
toggling
1
CS
RAS
CAS
WE
ODT
BA[2:0]
A[15:11]
A[10]
A[9:7]
A[6:3]
A[2:0]
0
Command
0
Cycle
Number
Sub-Loop
CKE
CK, CK
Table 8 - IDD4W Measurement-Loop Patterna)
Datab)
WR
0
1
0
0
1
0
00
0
0
0
0
000000
00
D
1
0
0
0
1
0
00
0
0
0
0
-
2,3
D,D
1
1
1
1
1
0
00
0
0
0
0
-
4
WR
0
1
0
0
1
0
00
0
0
F
0
001100
11
5
D
1
0
0
0
1
0
00
0
0
F
0
-
D,D
1
1
1
1
1
0
00
0
0
F
0
-
6,7
1
8-15
repeat Sub-Loop 0, but BA[2:0] = 1
2
16-23
repeat Sub-Loop 0, but BA[2:0] = 2
3
24-31
repeat Sub-Loop 0, but BA[2:0] = 3
4
32-39
repeat Sub-Loop 0, but BA[2:0] = 4
5
40-47
repeat Sub-Loop 0, but BA[2:0] = 5
6
48-55
repeat Sub-Loop 0, but BA[2:0] = 6
7
56-63
repeat Sub-Loop 0, but BA[2:0] = 7
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise FLOATING.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.1 / Apr 2009
44
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
A[2:0]
A[6:3]
A[9:7]
A[10]
A[15:11]
BA[2:0]
ODT
WE
CAS
RAS
CS
Command
Cycle
Number
Sub-Loop
CKE
Datab)
0
0
REF
0
0
0
1
0
0
0
0
0
0
0
-
1
1.2
D, D
1
0
0
0
0
0
00
0
0
0
0
-
3,4
D, D
1
1
1
1
0
0
00
0
0
F
0
-
Static High
toggling
CK, CK
Table 9 - IDD5B Measurement-Loop Patterna)
2
5...8
repeat cycles 1...4, but BA[2:0] = 1
9...12
repeat cycles 1...4, but BA[2:0] = 2
13...16
repeat cycles 1...4, but BA[2:0] = 3
17...20
repeat cycles 1...4, but BA[2:0] = 4
21...24
repeat cycles 1...4, but BA[2:0] = 5
25...28
repeat cycles 1...4, but BA[2:0] = 6
29...32
repeat cycles 1...4, but BA[2:0] = 7
33...nRFC-1
repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
a) DM must be driven LOW all the time. DQS, DQS are FLOATING.
b) DQ signals are FLOATING.
Rev. 0.1 / Apr 2009
45
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
Table 10 - IDD7 Measurement-Loop Patterna)
0
1
2
3
4
Static High
toggling
5
6
7
8
9
10
11
12
13
14
15
16
17
18
14
A[2:0]
A[6:3]
A[9:7]
A[10]
A[15:11]
BA[2:0]
ODT
WE
CAS
RAS
CS
Command
Cycle
Number
Sub-Loop
CKE
CK, CK
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
Datab)
0
ACT
0
0
1
1
0
0
00
0
0
0
0
RDA 0
1
0
1
0
0
00
1
0
0
0 00000000
D
1
0
0
0
0
0
00
0
0
0
0
repeat above D Command until nRRD - 1
ACT
0
0
1
1
0
1
00
0
0
F
0
RDA 0
1
0
1
0
1
00
1
0
F
0 00110011
D
1
0
0
0
0
1
00
0
0
F
0
repeat above D Command until 2* nRRD - 1
repeat Sub-Loop 0, but BA[2:0] = 2
repeat Sub-Loop 1, but BA[2:0] = 3
D
1
0
0
0
0
3
00
0
0
F
0
4*nRRD
...
Assert and repeat above D Command until nFAW - 1, if necessary
nFAW
repeat Sub-Loop 0, but BA[2:0] = 4
nFAW+nRRD
repeat Sub-Loop 1, but BA[2:0] = 5
nFAW+2*nRRD
repeat Sub-Loop 0, but BA[2:0] = 6
nFAW+3*nRRD
repeat Sub-Loop 1, but BA[2:0] = 7
D
1
0
0
0
0
7
00
0
0
F
0
nFAW+4*nRRD
...
Assert and repeat above D Command until 2* nFAW - 1, if necessary
2*nFAW+0
ACT
0
0
1
1
0
0
00
0
0
F
0
2*nFAW+1
RDA 0
1
0
1
0
0
00
1
0
F
0 00110011
D
1
0
0
0
0
0
00
0
0
F
0
2&nFAW+2
Repeat above D Command until 2* nFAW + nRRD - 1
2*nFAW+nRRD
ACT
0
0
1
1
0
1
00
0
0
0
0
2*nFAW+nRRD+1 RDA 0
1
0
1
0
1
00
1
0
0
0 00000000
D
1
0
0
0
0
1
00
0
0
0
0
2&nFAW+nRRD+
2
Repeat above D Command until 2* nFAW + 2* nRRD - 1
2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2
2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3
D
1
0
0
0
0
0
00
0
0
0
0
2*nFAW+4*nRRD
Assert and repeat above D Command until 3* nFAW - 1, if necessary
3*nFAW
repeat Sub-Loop 10, but BA[2:0] = 4
3*nFAW+nRRD
repeat Sub-Loop 11, but BA[2:0] = 5
3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6
3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7
D
1
0
0
0
0
0
00
0
0
0
0
3*nFAW+4*nRRD
Assert and repeat above D Command until 4* nFAW - 1, if necessary
1
2
...
nRRD
nRRD+1
nRRD+2
...
2*nRRD
3*nRRD
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise FLOATING.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are FLOATING.
Rev. 0.1 / Apr 2009
46
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
7. Electrical Characteristics and AC Timing
7.1 Refresh Parameters by Device Density
Parameter
REF command to
ACT or REF
command time
Average periodic
refresh interval
Rev. 0.1 / Apr 2009
tREFI
Symbol
512Mb
1Gb
2Gb
4Gb
8Gb
Units
tRFC
90
110
160
300
350
ns
0 ×C < TCASE < 85 ×C
7.8
7.8
7.8
7.8
7.8
us
85 ×C < TCASE < 95 ×C
3.9
3.9
3.9
3.9
3.9
us
47
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
7.2 DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC
for each corresponding bin
DDR3 1066 Speed Bin
DDR3-1066F
CL - nRCD - nRP
7-7-7
Parameter
Unit
Symbol
min
max
Internal read command to
first data
tAA
13.125
20
ns
ACT to internal read or write
delay time
tRCD
13.125
—
ns
PRE command period
tRP
13.125
—
ns
ACT to ACT or REF
command period
tRC
50.625
—
ns
ACT to PRE command
period
tRAS
37.5
9 * tREFI
ns
CL = 5
CL = 6
CL = 7
CL = 8
Note
CWL = 5
tCK(AVG)
Reserved
ns
1)2)3)4)6)
CWL = 6
tCK(AVG)
Reserved
ns
4)
CWL = 5
tCK(AVG)
ns
1)2)3)6)
CWL = 6
tCK(AVG)
Reserved
ns
1)2)3)4)
CWL = 5
tCK(AVG)
Reserved
ns
4)
CWL = 6
tCK(AVG)
ns
1)2)3)4)
CWL = 5
tCK(AVG)
ns
4)
CWL = 6
tCK(AVG)
ns
1)2)3)
2.5
3.3
1.875
< 2.5
Reserved
1.875
< 2.5
Supported CL Settings
6, 7, 8
nCK
Supported CWL Settings
5, 6
nCK
Rev. 0.1 / Apr 2009
48
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
DDR3 1333 Speed Bin
DDR3-1333H
CL - nRCD - nRP
9-9-9
Unit
Parameter
Symbol
min
max
Internal read command
to first data
tAA
13.5
20
ns
ACT to internal read or
write delay time
tRCD
13.5
—
ns
PRE command period
tRP
13.5
—
ns
ACT to ACT or REF
command period
tRC
49.5
—
ns
ACT to PRE command
period
tRAS
36
9 * tREFI
ns
Note
CWL = 5
tCK(AVG)
Reserved
ns
1,2,3,4,7
CWL = 6, 7
tCK(AVG)
Reserved
ns
4
CWL = 5
tCK(AVG)
ns
1,2,3,7
CWL = 6
tCK(AVG)
Reserved
ns
1,2,3,4,7
CWL = 7
tCK(AVG)
Reserved
ns
4
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
Reserved
ns
1,2,3,4,7
CWL = 7
tCK(AVG)
Reserved
ns
1,2,3,4
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
ns
1,2,3,7
CWL = 7
tCK(AVG)
Reserved
ns
1,2,3,4
CWL = 5, 6
tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
ns
1,2,3,4
CWL = 5, 6
tCK(AVG)
ns
4
CWL = 7
tCK(AVG)
ns
1,2,3
(Optional)
ns
5
Supported CL Settings
6, 8, 9
nCK
Supported CWL Settings
5, 6, 7
nCK
CL = 5
CL = 6
CL = 7
CL = 8
CL = 9
CL = 10
Rev. 0.1 / Apr 2009
2.5
3.3
1.875
< 2.5
1.5
<1.875
Reserved
1.5
<1.875
49
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
*Speed Bin Table Notes*
Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V);
Notes:
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection
of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the
DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC
standard tCK(AVG) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns],
rounding up to the next ‘Supported CL’.
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CLSELECTED and round the resulting tCK(AVG) down to the
next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to
CLSELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory
feature. Refer to supplier’s data sheet and SPD information if and how this setting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are
not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are
not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are
not subject to Production Tests but verified by Design/Characterization.
Rev. 0.1 / Apr 2009
50
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
8. Dimm Outline Diagram
8.1 164Mx64 - HMT164U6BFR6C
Front
2.10 ± 0.15
Max R0.70
Min 1.45
30.00
SPD
4 x 3.00 ± 0.10
17.30
DETAIL-B
DETAIL-A
2 x φ 2.50 ± 0.10
9.50
2 x 2.30 ± 0.10
47.00
5.175
71.00
128.95
133.35
Back
Side
Detail - A
Detail - B
3.18
0.3 ± 0.15
2.50 ± 0.20
3.80
0.35
0.05
1.27 ± 0.10
FULL R
2.50
0.80 ± 0.05
1.00
0.3~1.0
1.50 ± 0.10
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.1 / Apr 2009
51
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
8.2 128Mx64 - HMT112U6BFR8C
Front
2.10 ± 0.15
Min 1.45
Max R0.70
30.00
SPD
4 x 3.00 ± 0.10
17.30
2 x φ 2.50 ± 0.10
DETAIL-B
DETAIL-A
9.50
2 x 2.30 ± 0.10
47.00
5.175
71.00
128.95
133.35
Back
Side
Detail - A
Detail - B
3.18
0.3 ± 0.15
2.50 ± 0.20
3.80
0.35
0.05
1.27 ± 0.10
FULL R
2.50
0.80 ± 0.05
1.00
0.3~1.0
1.50 ±0.10
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.1 / Apr 2009
52
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
8.2 128Mx72
8.3
128Mx64 - HMT112U7BFR8C
HMT112U6BFR8C
Front
2.10 ± 0.15
Min 1.45
SPD
Max R0.70
30.00
4 x 3.00 ± 0.10
17.30
2 x φ 2.50 ± 0.10
DETAIL-B
DETAIL-A
9.50
2 x 2.30 ± 0.10
47.00
5.175
71.00
128.95
133.35
Back
Side
Detail - A
Detail - B
3.18
0.3 ± 0.15
2.50 ± 0.20
3.80
0.35
0.05
1.27 ± 0.10
FULL R
2.50
0.80 ± 0.05
1.00
0.3~1.0
1.50 ±0.10
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.1 / Apr 2009
53
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
8.4 256Mx64 - HMT125U6BFR8C
Front
2.10 ± 0.15
Min 1.45
Max R0.70
30.00
SPD
4 x 3.00 ± 0.10
17.30
2 x φ 2.50 ± 0.10
DETAIL-B
DETAIL-A
9.50
2 x 2.30 ± 0.10
47.00
5.175
71.00
128.95
133.35
Back
Detail - A
Detail - B
4.00
2.50 ± 0.20
3.80
0.35
0.05
1.27 ± 0.10
FULL R
2.50
0.80 ± 0.05
0.3 ± 0.15
Side
1.00
0.3~1.0
1.50 ±0.10
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.1 / Apr 2009
54
HMT164U6BFR6C
HMT112U6(7)BFR8C
HMT125U6(7)BFR8C
8.5 256Mx72 - HMT125U7BFR8C
Front
2.10 ± 0.15
Min 1.45
Max R0.70
SPD
30.00
4 x 3.00 ± 0.10
17.30
2 x φ 2.50 ± 0.10
DETAIL-B
DETAIL-A
9.50
2 x 2.30 ± 0.10
47.00
5.175
71.00
128.95
133.35
Back
Detail - A
Detail - B
4.00
2.50 ± 0.20
3.80
0.35
0.05
1.27 ± 0.10
FULL R
2.50
0.80 ± 0.05
0.3 ± 0.15
Side
1.00
0.3~1.0
1.50 ±0.10
5.00
Note) All dimensions are in millimeters unless otherwise stated.
Rev. 0.1 / Apr 2009
55