19-2153; Rev 3; 12/08 KIT ATION EVALU E L B AVAILA 3.125Gbps XAUI Quad Equalizer Features The MAX3980 quad equalizer provides compensation for transmission medium losses for four “lanes” of digital NRZ data at a 3.125Gbps data rate in one package. It is tailor-made for 10-Gigabit Ethernet (10GbE) backplane applications requiring attenuation of noise and jitter that occur in communicating from MAC to PMD or from MAC to Switch. In support of the IEEE-802.3ae for the XAUI interface, the MAX3980 adaptively allows XAUI lanes to reach up to 40in (1.0m) on FR-4 board material. The equalizer has 100Ω differential CML data inputs and outputs. The MAX3980 is available in a 44-pin exposed-pad QFN package. The MAX3980 consumes only 700mW at +3.3V or 175mW per channel. ♦ Four Differential Digital Data “Lanes” at 3.125Gbps ♦ Spans 40in (1.0m) of FR-4 PC Board ♦ Receiver Equalization Reduces Intersymbol Interference (ISI) ♦ Low-Power, 175mW per Channel ♦ Standby Mode—Power-Down State ♦ Single +3.3V Supply ♦ Signal Detect Ordering Information PART Applications IEEE-802.3ae XAUI Interface (3.125Gbps) TEMP RANGE PIN-PACKAGE MAX3980UGH 0°C to +85°C 44 QFN-EP* MAX3980UTH+ 0°C to +85°C 44 TQFN-EP* +Denotes a lead-free/RoHS-compliant package. *EP = Exposed pad. InfiniBandSM (2.5Gbps) Pin Configuration appears at end of data sheet. Typical Application Circuit SWITCH CARD LINE CARD PC BOARD BACKPLANE PMD MAC SWITCH ≤ 40in (1.0m) Rx Tx 4 Rx 4 Tx IN 4 x 3.125Gbps +3.3V SUPPLY 4x 3.125Gbps 10GbE Tx Rx 4 Tx Rx 4 OUT MAX3980 MAX3980 OUT 4 Rx +3.3V SUPPLY 4 IN Tx ≤ 40in (1.0m) InfiniBand is a trademark and service mark of the InfiniBand Trade Association. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3980 General Description MAX3980 3.125Gbps XAUI Quad Equalizer ABSOLUTE MAXIMUM RATINGS Operating Ambient Temperature Range ................0°C to +85°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Supply Voltage, VCC..............................................-0.5V to +4.0V Voltage at SDET, IN_±................................-0.5V to (VCC + 0.5V) Current Out of OUT_±.......................................-25mA to +25mA Continuous Power Dissipation (TA = +85°C) 44-Pin QFN-EP (derate 26.3mW/°C above +85°C)...2105mW Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, input data rate = 3.125Gbps, TA = 0°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP EN = TTL low Supply Power 0.25 EN = TTL high 0.7 10Hz < f < 100Hz 100 Supply Noise Tolerance 100Hz < f < 1MHz 40 Signal Detect Assert Input signal level to assert SDET (Note 1) Signal Detect Deassert Input signal level to deassert SDET (Note 1) 1MHz < f < 2.5GHz 0.9 UNITS W mVp-p 10 100 mVp-p Signal Detect Delay Latency MAX From input to output 30 mVp-p 10 μs 0.32 ns CML RECEIVER INPUT XAUI transmitter output measured differentially at point A, Figure 1, using K28.5 pattern Input Voltage Swing Return Loss 100MHz to 2.5GHz Input Resistance Differential 200 800 12 80 100 mVp-p dB 120 Ω EQUALIZATION Residual Jitter Random Jitter Total jitter (Note 2) 0.3 Deterministic jitter 0.2 (Note 2) 1.5 UIp-p psRMS CML TRANSMITTER OUTPUT (into 100Ω ±1Ω) Output Voltage Swing Differential swing 550 Common-Mode Voltage Transition Time mVp-p 130 ps 12 ps 60 Ω VCC - 0.3 tf, tr 20% to 80% (Note 3) Differential Skew Difference in 50% crossing between OUT_+ and OUT_- Output Resistance Single ended 2 850 60 40 50 _______________________________________________________________________________________ V 3.125Gbps XAUI Quad Equalizer (VCC = +3.0V to +3.6V, input data rate = 3.125Gbps, TA = 0°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Low Voltage 0.8 V Input High Current 250 μA Input Low Current 500 μA TTL CONTROL PINS Input High Voltage 2.0 Output High Voltage Internal 10kΩ pullup Output Low Voltage Internal 10kΩ pullup V 2.4 V 0.4 V Note 1: K28.7 pattern is applied differentially at point A as shown in Figure 1. Note 2: Total jitter does not include the signal source jitter. Total jitter (TJ) = [14.1 x RJ + DJ] where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5± pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for the random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from mediainduced loss and not from clock-source modulation. Jitter is measured at 0 at point C of Figure 1. Note 3: Using K28.7 (0011111000) pattern. C B A FR-4 STRIPLINE ≤ 40in (1m) MAX3980 SMA CONNECTOR SMA CONNECTOR IN OUT Figure 1. Test Conditions Referenced in the Electrical Characteristics Table _______________________________________________________________________________________ 3 MAX3980 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VCC = +3.3V, 3.125Gbps, 500mVp-p board input with 27 - 1 PRBS, TA = +25°C, unless otherwise noted.) EQUALIZER OUTPUT EYE DIAGRAM (20in BACKPLANE WITH TWO TERADYNE HSD CONNECTORS AND 3in DAUGHTERBOARD) 50mV/ div MAX3980 toc02 MAX3980 toc03 EQUALIZER OUTPUT EYE DIAGRAM AFTER EQUALIZATION (40in FR-4 6mil STRIPLINE) MAX3980 toc01 EQUALIZER INPUT EYE DIAGRAM BEFORE EQUALIZATION (40in FR-4 6mil STRIPLINE) 100mV/ div 100mV/ div 50ps/div 50ps/div 50ps/div INPUT RETURN GAIN (S11, DIFFERENTIAL, INPUT SIGNAL = -60dBm, DEVICE POWERED OFF) EQUALIZER DETERMINISTIC JITTER vs. LENGTH (FR-4 6mil STRIPLINE, K28.5 PATTERN) EQUALIZER LATENCY vs. TEMPERATURE 35 MAX3980 toc06 0 500 MAX3980 toc05 40 MAX3980 toc04 10 450 30 -20 400 25 DELAY (ps) JITTER (ps) -10 GAIN (dB) 20 15 -30 350 300 10 -40 250 5 -50 200 0 50 1050 2050 3050 4050 0 5050 10 20 FREQUENCY (MHz) 30 40 50 0 10 20 30 40 MAX3980 toc07 EQUALIZER OPERATING CURRENT vs. TEMPERATURE 210 NORMAL OPERATION (EN = TTL HIGH) 190 170 150 130 110 90 STANDBY POWER (EN = TTL LOW) 70 50 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) 4 50 60 TEMPERATURE (°C) LENGTH (in) CURRENT (mA) MAX3980 3.125Gbps XAUI Quad Equalizer _______________________________________________________________________________________ 70 80 90 3.125Gbps XAUI Quad Equalizer PIN NAME FUNCTION 1, 5, 9, 13, 23, 27, 31, 35 VCC +3.3V Supply Voltage 2 IN1+ Positive Equalizer Input Channel 1, CML 3 IN1- Negative Equalizer Input Channel 1, CML 4, 8, 12, 16, 26, 30, 34, 38 GND Supply Ground 6 IN2+ Positive Equalizer Input Channel 2, CML 7 IN2- Negative Equalizer Input Channel 2, CML 10 IN3+ Positive Equalizer Input Channel 3, CML 11 IN3- Negative Equalizer Input Channel 3, CML 14 IN4+ Positive Equalizer Input Channel 4, CML 15 IN4- Negative Equalizer Input Channel 4, CML 17–22, 39–42 N.C. No Connection. Leave unconnected. 24 OUT4- 25 OUT4+ Negative Equalizer Output Channel 4, CML Positive Equalizer Output Channel 4, CML 28 OUT3- Negative Equalizer Output Channel 3, CML 29 OUT3+ Positive Equalizer Output Channel 3, CML 32 OUT2- Negative Equalizer Output Channel 2, CML 33 OUT2+ Positive Equalizer Output Channel 2, CML 36 OUT1- Negative Equalizer Output Channel 1, CML 37 OUT1+ Positive Equalizer Output Channel 1, CML 43 EN Enable Equalizer Input. A TTL high selects normal operation. A TTL low selects low-power standby mode. 44 SDET Signal Detect Output for Channel 1. Produces a TTL high output when a signal is detected. — EP Exposed Pad. The exposed pad must be soldered to the circuit board ground plane for proper thermal and electrical performance. _______________________________________________________________________________________ 5 MAX3980 Pin Description 3.125Gbps XAUI Quad Equalizer MAX3980 Functional Diagram IP1, IN1 ONLY IN1+ IN1- 2 2 SIGNAL DETECT TTL OUT1+ 3 3 CML 4 4 3 3 EN SDET FUNCTION IS INDEPENDENT OF EN OUT1- 2 2 2 2 LIMITING AMP EQUALIZER 2 3 4 4 4 POWER MANAGEMENT Detailed Description Receiver and Transmitter The receiver accepts four lanes of 3.125Gbps currentmode logic (CML) digital data signals. The adaptive equalizer compensates each received signal for dielectric and skin losses. The limiting amp shapes the output of the equalizer. The regenerated XAUI lanes are transmitted as CML signals. The source impedance and termination impedances are 100Ω differential. General Theory of Operation Internally, the MAX3980 comprises signal-detect circuitry, four matched equalizers, and one equalizercontrol loop. The four equalizers are made up of a master equalizer and three slave equalizers. The adaptive control is generated from only channel 1. It is assumed that all channels have the same characterization in frequency content, coding, and transmission length. The master equalizer consists of the following functions: signal detect, adaptive equalizer, equalizer control, and limiting and output drivers. The signal detect indicates input signal power. When the input signal level is sufficiently high, the SDET output is asserted. This does not directly control the operation of the part. The equalizer core reduces intersymbol interference (ISI), compensating for frequency-dependent, mediainduced loss. The equalization control detects the spectral contents of the input signal and provides a control voltage to the equalizer core, adapting it to different media. The equalizer operation is optimized for 6 SDET 3 2 3 3 4 4 4 MAX3980 short-run DC-balanced transmission codes such as 8b/10b codes. CML Input and Output Buffers The input and output buffers are implemented using CML. Equivalent circuits are shown in Figures 2 and 3. For details on interfacing with CML, see Maxim application note HFAN-1.0, Interfacing Between CML, PECL, and LVDS. The common-mode voltage of the input and output is above 2.5V. AC-coupling capacitors are required when interfacing this part. Values of 0.10µF or greater are recommended. Media Equalization Equalization at the input port compensates for the highfrequency loss encountered with up to 40in (1.0m) of FR-4 transmission lines. This part is optimized for 40in and 3.125Gbps; however, the part reduces ISI for signals spanning longer distances and functions for data rates from 2Gbps to 4Gbps, provided that short-length balanced codes, such as 8b/10b, are used. Applications Information Standby Mode The power-saver standby state allows reduced-power operation. The TTL input, EN, must be set to TTL high for normal operation. A TTL low at EN forces the equalizer into the standby state. The signal EN does not affect the operation of the signal detect (SDET) function. For constant operation, connect the EN signal directly to VCC. _______________________________________________________________________________________ 3.125Gbps XAUI Quad Equalizer MAX3980 VCC VCC 50Ω 50Ω 1.2kΩ OUT+ 50Ω 50Ω OUT- IN+ Q1 Q2 INDATA 200μA ESD STRUCTURES ESD STRUCTURES Figure 2. CML Input Buffer Figure 3. CML Output Buffer Signal Detect with Standby Mode Layout Considerations Signal activity is detected on channel 1 only. When the peak-to-peak differential voltage at IN1± is less than 30mVp-p, the TTL output SDET goes low. When the peak-to-peak differential voltage becomes greater than 100mVp-p, SDET is asserted high. SDET can be used to automatically force the equalizer into standby mode by connecting SDET directly to the EN input. When not used, SDET should not be connected. Circuit-board layout and design can significantly affect the MAX3980 performance. Use good high-frequency design techniques, including minimizing ground inductances and vias and using controlled-impedance transmission lines for the high-frequency data signals. Signals should be routed differentially to reduce EMI susceptibility and crosstalk. Power-supply decoupling capacitors should be placed as close as possible to the VCC pins. The signal-detect function continues to operate while the part is in standby mode. While connected to the EN pin, the signal detect can “wake up” the part and resume normal operation. _______________________________________________________________________________________ 7 3.125Gbps XAUI Quad Equalizer MAX3980 Pin Configuration Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. VCC GND 34 35 36 37 38 39 N.C. N.C. N.C. GND OUT1+ OUT141 40 EN N.C. 43 42 SDET 44 TOP VIEW VCC 1 33 IN1+ IN1GND 2 32 3 31 OUT2+ OUT2VCC 4 30 GND VCC IN2+ 5 29 IN2GND VCC 7 27 8 26 OUT3+ OUT3VCC GND 9 25 IN3+ IN3- 10 24 6 *EP DOCUMENT NO. 44 QFN G4477-1 21-0092 44 TQFN T4477-3 21-0144 OUT4+ OUT4VCC 22 21 20 19 PACKAGE CODE N.C. N.C. N.C. N.C. 18 17 16 15 13 14 12 VCC IN4+ IN4GND N.C. N.C. 23 GND 11 28 MAX3980 PACKAGE TYPE QFN-EP/TQFN-EP *NOTE: THE EXPOSED PAD MUST BE SOLDERED TO SUPPLY GROUND. 8 _______________________________________________________________________________________ 3.125Gbps XAUI Quad Equalizer REVISION NUMBER REVISION DATE 0 9/01 1 5/03 DESCRIPTION Initial release. — Added the package code to the Ordering Information table. 1 Updated the 21-0092 package drawing in the Package Information section. 2 3 PAGES CHANGED 8, 9 Added the TQFN package to the Ordering Information table. 1 Added the 21-0144 package drawing to the Package Information section. 10 Changed the Absolute Maximum Ratings of SDET, IN_± from +5.0V to (VCC to 0.5V) to –5.0V to (VCC to 0.5V). 2 1/05 12/08 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 _____________________ 9 © 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc. MAX3980 Revision History