Revised August 1999 74FR573 Octal D-Type Latch with 3-STATE Outputs General Description Features The 74FR573 is a high speed octal latch with buffered common Latch Enable (LE) and buffered common Output Enable (OE) inputs. ■ Broadside pinout aids in PC layout This device is functionally identical to the 74F573. ■ Functionally identical to the 74F373, 74F573 ■ Outputs have current sourcing capability of 15 mA and current sinking capability of 64 mA ■ Guaranteed pin-to-pin skew Ordering Code: Order Number Package Number Package Description 74FR573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74FR573PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names OE Description Output Enable Input (Active-LOW) LE Latch Enable Input (Active-HIGH) D0–D7 Data Inputs O0–O7 3-STATE Latch Outputs © 1999 Fairchild Semiconductor Corporation DS010903 www.fairchildsemi.com 74FR573 Octal D-Type Latch with 3-STATE Outputs January 1991 74FR573 Functional Description Function Table The 74FR573 contains eight D-type latches with 3-STATE output buffers. When the latch enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode, but this does not interfere with entering new data into the latches. Inputs www.fairchildsemi.com LE Dn On L H H H L H L L L L X On − 1 H X X High Z State H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Logic Diagram 2 Output OE Recommended Operating Conditions −65°C to +150°C Storage Temperature Ambient Temperature under Bias −55°C to 125°C Free Air Ambient Temperature 0°C to +70°C Junction Temperature under Bias −55° to +150°C Supply Voltage +4.5V to 5.5V VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5 to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output in LOW State (Max) Note 2: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V DC Electrical Characteristics Symbol Parameter Min Typ Max 2.0 Units VCC V Conditions VIH Input HIGH Voltage Recognized HIGH Signal VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min VOH Output HIGH 2.4 V Min IOH = −3 mA Voltage 2.0 V Min IOH = −15 mA Recognized LOW Signal IIN = −18 mA VOL Output LOW Voltage 0.55 V Min IIOL = 64 mA IIH Input HIGH Current 5 µA Max VIN = 2.7V IBVI Input HIGH Current 7 µA Max VIN = 7.0V −150 µA Max VIN = 0.5V Data Inputs −100 µA Max VIN = 0.5V Control Inputs V 0.0 Breakdown Test IIL VID Input LOW Current Input Leakage Test 4.75 IID = 1.9 µA, All Other Pins Grounded IOD Output Circuit Leakage Current IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current ICEX Output HIGH Leakage Current −100 µAIOD = 150 mV, 3.75 µA 0.0 20 µA Max VOUT = 2.7V VOUT = 0.5V All Other Pins Grounded −20 µA Max −225 mA Max VOUT = 0.0V 50 µA Max VOUT = VCC IZZ Bus Drainage Test 100 µA 0.0 VOUT = 5.25V ICCH Power Supply Current 26 32 mA Max All Outputs HIGH ICCL Power Supply Current 55 65 mA Max All Outputs LOW ICCZ Power Supply Current 32 40 mA Max Outputs 3-STATED CIN Input Capacitance 8.0 pF 5.0 3 www.fairchildsemi.com 74FR573 Absolute Maximum Ratings(Note 1) 74FR573 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ Max Min Max tPLH Propagation Delay 1.7 2.9 4.5 1.7 4.5 tPHL Dn to On 1.7 2.6 4.5 1.7 4.5 tPLH Propagation Delay 2.6 6.0 8.5 2.6 8.5 tPHL LE to On 2.6 4.3 8.5 2.6 8.5 tPZH Output Enable Time tPZL tPHZ Output Disable Time tPLZ 2.8 4.0 7.4 2.8 7.4 2.8 5.0 7.4 2.8 7.4 2.2 4.0 6.3 2.2 6.3 2.2 3.5 6.3 2.2 6.3 Units ns ns ns ns AC Operating Requirements Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Min Typ tS(H) Setup Time, HIGH or LOW 1.0 −0.4 Max Min 1.0 tS(L) Dn to LE 1.0 −0.7 1.0 tH(H) Hold Time, HIGH or LOW 2.5 0.9 2.5 tH(L) Dn to LE 2.5 0.6 2.5 tW(H) LE Pulse Width HIGH 5.0 2.7 5.0 Units Max ns ns ns Extended AC Electrical Characteristics Symbol Parameter TA = 0°C to +70°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 250 pF Eight Outputs Switching (Note 4) Units (Note 3) Max Min Max tPLH Propagation Delay 1.7 5.7 3.4 8.1 tPHL Dn to On 1.7 5.7 3.4 8.1 tPLH Propagation Delay 2.6 9.8 4.5 12.3 tPHL LE to On 2.6 9.8 4.5 12.3 tPZH Output Enable Time 2.8 9.6 2.8 9.6 2.2 7.3 2.2 7.3 tPZL tPHZ Output Disable Time tPLZ tOSHL Pin-to-Pin Skew (Note 5) for HL Transitions tOSLH Pin-to-Pin Skew (Note 5) for LH Transitions tOST Pin-to-Pin Skew (Note 5) for HL/LH Transitions Min ns ns ns ns 1.3 ns 1.3 ns 3.0 ns Note 3: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase, i.e. all LOW-to-HIGH, HIGH-to-LOW, 3-STATE-to-HIGH, etc. Note 4: These specifications guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load. This specification pertains to single output switching only. Note 5: Skew is defined as the absolute value of the difference between the actual propagation delays for any two outputs of the same device. The specification applies to any outputs switching HIGH-to-LOW, (tOSHL), LOW-to-HIGH, (tOSLH) or any combination of HIGH-to-LOW and/or LOW-to-HIGH, (tOST). Specifications guaranteed with all outputs switching in phase. www.fairchildsemi.com 4 74FR573 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 5 www.fairchildsemi.com 74FR573 Octal D-Type Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 6