74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The LVQ374 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. n Ideal for low power/low noise 3.3V applications n Implements patented EMI reduction circuitry n Available in SOIC JEDEC, SOIC EIAJ and QSOP packages n Guaranteed simultaneous switching noise level and dynamic threshold performance n Improved latch-up immunity n Guaranteed incident wave switching into 75Ω n 4 kV minimum ESD immunity n Buffered positive edge-triggered clock n 3-STATE outputs drive bus lines or buffer memory address registers Ordering Code: Order Number Package Number 74LVQ374SC M20B 74LVQ374SJ 74LVQ374QSC Package Description 20-Lead (0.300" Wide) Molded Small Outline Package, SOIC JEDEC M20D 20-Lead Molded Shrink Small Outline Package, SOIC EIAJ MQA20 20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SOIC JEDEC Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram Pin Assignment for SOIC and QSOP DS011360-1 IEEE/IEC DS011360-3 DS011360-2 © 1998 Fairchild Semiconductor Corporation DS011360 www.fairchildsemi.com 74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs May 1998 Pin Descriptions Pin Names Truth Table Description Inputs Outputs D0–D7 Data Inputs Dn CP OE On CP Clock Pulse Input H N L H OE 3-STATE Output Enable Input L N L L O0–O7 3-STATE Outputs X X H Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition Functional Description The LVQ374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time re- quirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Logic Diagram DS011360-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Absolute Maximum Ratings (Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current Recommended Operating Conditions (Note 2) −0.5V to +7.0V Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) VIN from 0.8V to 2.0V VCC @ 3.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V 2.0V to 3.6V 0V to VCC 0V to VCC −40˚C to +85˚C 125 mV/ns Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. ± 50 mA ± 400 mA −65˚C to +150˚C Note 2: Unused inputs must be held HIGH or LOW. They may not float. ± 300 mA DC Electrical Characteristics Symbol Parameter VCC (V) TA = +25˚C Typ VIH Minimum High Level 3.0 1.5 TA = −40˚C to +85˚C Units Guaranteed Limits 2.0 2.0 V Input Voltage VIL Maximum Low Level VOUT = 0.1V or VCC − 0.1V 3.0 1.5 0.8 0.8 V VOUT = 0.1V or VCC − 0.1V Input Voltage VOH Conditions 2.9 2.9 V IOUT = −50 µA 2.58 2.48 V VIN = VIL or VIH (Note 3) 0.1 0.1 V IOUT = 50 µA 3.0 0.36 0.44 V VIN = VIL or VIH (Note 3) 3.6 ± 0.1 ± 1.0 µA Minimum High Level 3.0 Output Voltage 3.0 Maximum Low Level 3.0 Output Voltage Maximum Input 2.99 IOH = −12 mA VOL 0.002 IOL = 12 mA IIN VI = VCC, GND Leakage Current IOLD Minimum Dynamic 3.6 36 mA VOLD = 0.8V Max (Note 5) IOHD Output Current (Note 4) 3.6 −25 mA VOHD = 2.0V Min (Note 5) Maximum Quiescent 3.6 4.0 40.0 µA VIN = VCC or GND Leakage Current 3.6 ± 0.25 ± 2.5 µA VI = VCC, GND Quiet Output 3.3 0.5 0.8 V (Notes 6, 7) 3.3 −0.3 −0.8 V (Notes 6, 7) 3.3 1.7 2.0 V (Notes 6, 8) 3.3 1.6 0.8 V (Notes 6, 8) ICC Supply Current IOZ VI (OE) = VIL, VIH Maximum 3-STATE VO = VCC, GND VOLP Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VIHD Maximum High Level Dynamic Input Voltage VILD Maximum Low Level Dynamic Input Voltage Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. 3 www.fairchildsemi.com AC Electrical Characteristics Symbol TA = +25˚C CL = 50 pF VCC (V) Parameter Min Maximum Clock Frequency fmax tPLH Propagation Delay tPHL CP to On tPZL Output Enable Time tPZH Output Disable Time tPHZ tPLZ tOSHL Output to Output Skew (Note 9) tOSLH CP to On Typ TA = −40˚C to +85˚C CL = 50 pF Max Min 2.7 55 50 3.3 ± 0.3 75 70 Units Max MHz 2.7 3.0 11.4 18.3 3.0 19.0 3.3 ± 0.3 3.0 9.5 13.0 3.0 13.5 2.7 3.0 11.4 18.3 3.0 19.0 3.3 ± 0.3 3.0 9.5 13.0 3.0 13.5 2.7 1.0 11.4 20.4 1.0 21.0 3.3 ± 0.3 1.0 9.5 14.5 1.0 15.0 2.7 1.0 1.5 1.5 3.3 ± 0.3 1.0 1.5 1.5 ns ns ns ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. AC Operating Requirements Symbol TA = +25˚C CL = 50 pF VCC (V) Parameter TA = 40˚C− to +85˚C CL = 50 pF Typ Setup Time, HIGH or LOW tS Dn to CP tH Hold Time, HIGH or LOW Dn to CP CP Pulse Width, tW HIGH or LOW Guaranteed Minimum 2.7 0 4.0 4.5 3.3 ± 0.3 0 3.0 3.0 2.7 0 1.5 1.5 3.3 ± 0.3 0 1.5 1.5 2.7 2.4 5.0 6.0 3.3 ± 0.3 2.0 4.0 4.0 ns ns ns Capacitance Symbol Parameter Typ Units CIN Input Capacitance 4.5 pF VCC = Open CPD (Note 10) Power Dissipation Capacitance 39 pF VCC = 3.3V Note 10: CPD is measured at 10 MHz. www.fairchildsemi.com 4 Units Conditions Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead (0.300" Wide) Molded Small Outline Package, SOIC JEDEC Package Number M20B 20-Lead Molded Shrink Small Outline Package, SOIC EIAJ Package Number M20D 5 www.fairchildsemi.com 74LVQ374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead (0.150" Wide) Molded Shrink Small Outline Package, SOIC JEDEC (also known as QSOP) Package Number MQA20 LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. 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