Revised June 2001 74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset General Description Features The LVQ174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flipflops. ■ Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed pin-to-pin skew AC performance ■ Guaranteed incident wave switching into 75Ω Ordering Code: Order Number Package Number Package Description 74LVQ174SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVQ174SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names © 2001 Fairchild Semiconductor Corporation DS011353 Description D0–D5 Data Inputs CP Clock Pulse Input MR Master Reset Input Q0–Q5 Outputs www.fairchildsemi.com 74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset February 1992 74LVQ174 Functional Description Truth Table The LVQ174 consists of six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR) are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW-to-HIGH Clock (CP) transition. A LOW input to the Master Reset (MR) will force all outputs LOW independent of Clock or Data inputs. The LVQ174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Inputs Output MR CP D L X L H H H H H X L L L X Q H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW-to-HIGH Transition Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Q Supply Voltage (VCC) Recommended Operating Conditions (Note 2) −0.5V to +7.0V DC Input Diode Current (IIK) Supply Voltage (VCC) VI = −0.5V −20 mA Input Voltage (VI) VI = VCC + 0.5V +20 mA Output Voltage (VO) DC Input Voltage (VI) −0.5V to VCC + 0.5V 0V to VCC −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) VO = −0.5V −20 mA VIN from 0.8V to 2.0V VO = VCC + 0.5V +20 mA VCC @ 3.0V 125 mV/ns −0.5V to VCC + 0.5V DC Output Source Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. ±50 mA or Sink Current (IO) DC VCC or Ground Current ±200 mA (ICC or IGND) Storage Temperature (TSTG) 0V to VCC Operating Temperature (TA) DC Output Diode Current (IOK) DC Output Voltage (VO) 2.0V to 3.6V −65°C to +150°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Latch-Up Source or ±100 mA Sink Current DC Electrical Characteristics Symbol VIH Parameter Minimum High Level Input Voltage VIL Maximum Low Level Input Voltage VOH Minimum High Level Output Voltage VOL Maximum Low Level Output Voltage IIN Maximum Input Leakage Current VCC TA = +25°C TA = −40°C to +85°C Units (V) Typ 3.0 1.5 2.0 2.0 V 3.0 1.5 0.8 0.8 V 3.0 2.99 2.9 2.9 V 3.0 3.0 Conditions Guaranteed Limits 0.002 3.0 2.58 2.48 V 0.1 0.1 V 0.36 ±0.1 3.6 0.44 V ±1.0 µA VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V or VCC − 0.1V IOUT = −50 µA VIN = VIL or VIH (Note 3) IOH = −12 mA IOUT = 50 µA VIN = VIL or VIH (Note 3) IOL = 12 mA VI = VCC, GND IOLD Minimum Dynamic (Note 4) 3.6 36 mA VOLD = 0.8V Max (Note 5) IOHD Output Current 3.6 −25 mA VOHD = 2.0V Min (Note 5) ICC Maximum Quiescent 40.0 µA Supply Current VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VIHD Maximum High Level Dynamic Input Voltage VILD Maximum Low Level Dynamic Input Voltage 3.6 4.0 VIN = VCC or GND 3.3 0.7 0.8 V (Note 6)(Note 7) 3.3 −0.6 −0.8 V (Note 6)(Note 7) 3.3 1.8 2.0 V (Note 6)(Note 8) 3.3 1.6 0.8 V (Note 6)(Note 8) Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. 3 www.fairchildsemi.com 74LVQ174 Absolute Maximum Ratings(Note 1) 74LVQ174 AC Electrical Characteristics TA = +25°C Symbol fMAX Maximum Clock Frequency CP to Qn CP to Qn tPHL tOSHL, Output to tOSLH Output Skew (Note 9) CL = 50 pF Typ Max Min 60 90 50 90 100 70 Units Max MHz 2.7 2.0 10.8 16.2 1.5 18.0 3.3 ± 0.3 2.0 9.0 11.5 1.5 12.5 2.7 2.0 10.2 15.5 1.5 17.0 3.3 ± 0.3 2.0 8.5 11.0 1.5 12.0 2.7 2.5 10.8 16.2 2.0 18.0 3.3 ± 0.3 2.5 9.0 11.5 2.0 12.5 Propagation Delay MR to Qn Min 2.7 Propagation Delay tPHL (V) 3.3 ± 0.3 Propagation Delay tPLH TA = −40°C to +85°C CL = 50 pF VCC Parameter 2.7 1.0 1.5 1.5 3.3 ± 0.3 1.0 1.5 1.5 ns ns ns ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. AC Operating Requirements TA = +25°C Symbol tS Parameter Setup Time, HIGH or LOW Dn to CP tH Hold Time, HIGH or LOW Dn to CP tW tW tREC MR Pulse Width, LOW CP Pulse Width Recovery Time MR to CP TA = −40°C to +85°C CL = 50 pF VCC CL = 50 pF (V) Typ 2.7 3.0 8.0 10.0 3.3 ± 0.3 2.5 6.5 7.0 2.7 1.2 4.0 4.5 3.3 ± 0.3 1.0 3.0 3.0 2.7 1.2 7.0 10.0 3.3 ± 0.3 1.0 5.5 7.0 2.7 1.2 7.0 10.0 3.3 ± 0.3 1.0 5.5 7.0 2.7 0 3.5 3.5 3.3 ± 0.3 0 2.5 2.5 Typ Units CIN Input Capacitance Parameter 4.5 pF VCC = Open CPD (Note 10) Power Dissipation Capacitance 23 pF VCC = 3.3V Note 10: CPD is measured at 10 MHz. www.fairchildsemi.com 4 ns ns ns ns ns Capacitance Symbol Units Guaranteed Minimum Conditions 74LVQ174 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com 74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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