TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065A – OCTOBER 1983 – REVISED MARCH 1995 D D D D D D D DW OR N PACKAGE (TOP VIEW) 8-Bit Resolution A/D Converter Microprocessor Peripheral or Stand-Alone Operation On-Chip 12-Channel Analog Multiplexer Built-in Self-Test Mode Software-Controllable Sample and Hold Total Unadjusted Error . . . ± 0.5 LSB Max TLC541 is Direct Replacement for Motorola MC145040 and National Semiconductor ADC0811. TLC540 is Capable of Higher Speed Pinout and Control Signals Compatible with TLC1540 Family of 10-Bit A/D Converters CMOS Technology PARAMETER TLC540 TLC541 Channel Acquisition Sample Time Conversion Time (Max) Samples per Second (Max) Power Dissipation (Max) 2 µs 9 µs 75 x 103 12.5 mW 3.6 µs 17 µs 40 x 103 12.5 mW INPUT A0 INPUT A1 INPUT A2 INPUT A3 INPUT A4 INPUT A5 INPUT A6 INPUT A7 INPUT A8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC SYSTEM CLOCK I/O CLOCK ADDRESS INPUT DATA OUT CS REF + REF – INPUT A10 INPUT A9 FN PACKAGE (TOP VIEW) INPUT A2 INPUT A1 INPUT A0 VCC SYSTEM CLOCK D D description INPUT A3 INPUT A4 INPUT A5 INPUT A6 INPUT A7 4 3 2 1 20 19 18 I/O CLOCK INPUT A8 GND INPUT A9 INPUT A10 REF– The TLC540 and TLC541 are CMOS A / D 17 ADDRESS INPUT 5 converters built around an 8-bit switched16 DATA OUT 6 capacitor successive-approximation A/D 15 CS 7 converters. They are designed for serial interface 14 REF + 8 9 10 11 12 13 to a microprocessor or peripheral via a 3-state output with up to four control inputs, including independent SYSTEM CLOCK, I/O CLOCK, chip select (CS), and ADDRESS INPUT. A 4-MHz system clock for the TLC540 and a 2.1-MHz system clock for the TLC541 with a design that includes simultaneous read/write operation allow high-speed data transfers and sample rates of up to 75,180samples per second for the TLC540 and 40,000 samples per second for the TLC541. In addition to the high-speed converter and versatile control logic, there is an on-chip 12-channel analog multiplexer that can be used to sample any one of 11 inputs or an internal self-test voltage, and a sample-and-hold that can operate automatically or under microprocessor control. Detailed information on interfacing to most popular microprocessors is readily available from the factory. AVAILABLE OPTIONS PACKAGE TA SO PLASTIC DIP (DW) PLASTIC DIP (N) CHIP CARRIER (FN) – 40°C to 85°C — TLC541IDW TLC540IN TLC541IN TLC540IFN TLC541IFN – 55°C to 125°C — TLC541MN — Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065A – OCTOBER 1983 – REVISED MARCH 1995 The converters incorporated in the TLC540 and TLC541 feature differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises. A switched-capacitor design allows low-error (± 0.5 LSB) conversion in 9 µs for the TLC540 and 17 µs for the TLC541 over the full operating temperature range. The TLC540I and TLC541I are characterized for operation from – 40°C to 85°C.The TLC541M is characterized for operation from – 55°C to 125°C. functional block diagram REF+ 14 Analog Inputs 1 A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 A8 11 A9 A10 12 REF– 13 8-Bit Analog-to-Digital Converter (Switched-Capacitors) Sample and Hold 12-Channel Analog Multiplexer 8 Output Data Register Input Address Register 4 8 8-to-1 Data Selector and Driver 16 DATA OUT 4 Self-Test Reference 4 Input Multiplexer ADDRESS 17 INPUT 2 Control Logic and I/O Counters I/O 18 CLOCK CS 15 SYSTEM 19 CLOCK typical equivalent inputs INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE 1 kΩ TYP INPUT A0 – A10 2 INPUT A0 – A10 Ci = 60 pF TYP (equivalent input capacitance) POST OFFICE BOX 655303 5 MΩ TYP • DALLAS, TEXAS 75265 TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065A – OCTOBER 1983 – REVISED MARCH 1995 operating sequence 2 1 3 4 5 6 7 1 8 I/O CLOCK Don’t Access Cycle B (see Note C) Sample Cycle B 2 3 4 5 6 7 8 Care Access Cycle C tconv Sample Cycle C See Note A CS ADDRESS INPUT DATA OUT MSB twH(CS) Don’t Care LSB B3 B2 B1 B0 MSB LSB C3 C2 C1 C0 Don’t Care Hi-Z State Hi-Z State A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 A7 B7 Previous Conversion Data A MSB (See Note B) LSB MSB MSB Conversion Data B LSB MSB NOTES: A. The conversion cycle, which requires 36 system clock periods, is initiated on the 8th falling edge of I/O CLOCK after CS goes low for the channel whose address exists in memory at that time. If CS is kept low during conversion, I/O CLOCK must remain low for at least 36 system clock cycles to allow conversion to be completed. B. The most significant bit (MSB) will automatically be placed on the DATA OUT bus after CS is brought low. The remaining seven bits (A6 – A0) will be clocked out on the first seven I/O CLOCK falling edges. C. To minimize errors caused by noise at CS, the internal circuitry waits for three system clock cycles (or less) after a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in address data until the minimum chip-select setup time has elapsed. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V Peak input current range (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 10 mA Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 mA Operating free-air temperature range, TA: TLC540I, TLC541I . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to digital ground with REF– and GND wired together (unless otherwise noted). POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065A – OCTOBER 1983 – REVISED MARCH 1995 recommended operating conditions TLC540 MIN Supply voltage, VCC Positive reference voltage, Vref+ (see Note 2) MAX MIN 5.5 4.75 5 5.5 V VCC + 0.1 2.5 2.5 VCC + 0.1 2.5 V – 0.1 VCC 0 VCC + 0.2 VCC 1 VCC VCC + 0.2 VCC V 1 VCC Analog input voltage (see Note 2) 0 High-level control input voltage, VIH 2 Low-level control input voltage, VIL 0 2 0.8 Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 3) CS high during conversion, twH(CS) I/O CLOCK frequency, fclock(I/O) Pulse duration, SYSTEM CLOCK high, twH(SYS) V V V 0.8 V 200 400 0 0 ns 3 3 System clock cycles 36 36 System clock cycles 0 Pulse duration, SYSTEM CLOCK frequency, fclock(SYS) UNIT 5 – 0.1 Hold time, address bits after I/O CLOCK↑, th(A) MAX 2.5 Differential reference voltage, Vref+ – Vref– (see Note 2) Setup time, address bits at data input before I/O CLOCK↑, tsu(A) NOM 4.75 VCC 0 Negative reference voltage, Vref– (see Note 2) TLC541 NOM fclock(I/O) 110 2.048 4 0 fclock(I/O) 210 ns 1.1 MHz 2.1 MHz MHz Pulse duration, SYSTEM CLOCK low, twL(SYS) 100 190 MHz Pulse duration, I/O clock high, twH(I/O) 200 404 ns Pulse duration, I/O clock low, twL(I/O) 200 System fclock(SYS) ≤ 1048 kHz fclock(SYS) > 1048 kHz I/O fclock(I/O) ≤ 525 kHz fclock(I/O) > 525 kHz Clock transition time (see Note 4) 404 ns 30 30 20 20 100 100 40 40 ns Operating free-air temperature, TA TLC540I, TLC541I – 40 85 – 40 85 °C NOTES: 2. Analog input voltages greater than that applied to REF + convert as all “1”s (11111111), while input voltages less than that applied to REF– convert as all “0”s (00000000). For proper operation, REF+ voltage must be at least 1 V higher than REF– voltage. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V. 3. To minimize errors caused by noise at CS, the internal circuitry waits for three SYSTEM CLOCK cycles (or less) after a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum chip select setup time has elapsed. 4. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065A – OCTOBER 1983 – REVISED MARCH 1995 electrical characteristics over recommended operating temperature range, VCC = Vref+ = 4.75 V to 5.5 V, fclock(I/O) = 2.048 MHz for TLC540 or fclock(I/O) = 1.1 MHz for TLC541 (unless otherwise noted) PARAMETER VOH VOL TEST CONDITIONS High-level output voltage, DATA OUT Low-level output voltage VO = VCC, VO = 0, CS at VCC 10 CS at VCC – 10 IIH IIL High-level input current Low-level input current VI =VCC VI = 0 ICC Operating supply current Ci Input capacitance 2.4 UNIT V 0.4 V µA µA 0.005 2.5 – 0.005 – 2.5 µA CS at 0 V 1.2 2.5 mA Selected channel at VCC, Unselected channel at 0 V 0.4 1 – 0.4 –1 Selected channel at 0 V, Unselected channel at VCC Supply and reference current MAX IOH = 360 µA IOL = 1.6 mA Off state (high-impedance Off-state (high impedance state) output current ICC + Iref TYP† VCC = 4.75 V, VCC = 4.75 V, IOZ Selected channel leakage current MIN Vref+ = VCC, CS at 0 V µA 1.3 3 Analog inputs 7 55 Control inputs 5 15 mA pF † All typical values are at TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065A – OCTOBER 1983 – REVISED MARCH 1995 operating characteristics over recommended operating free-air temperature range, VCC = Vref+ – 4.75 V to 5.5 V, fclock(I/O) = 2.048 MHz for TLC540 or 1.1 MHz for TLC541, fclock(SYS) = 4 MHz for TLC540 or 2.1 MHz for TLC541 PARAMETER TEST CONDITIONS TLC540 MIN TLC541 MAX MIN MAX UNIT EL EZS Linearity error See Note 5 ± 0.5 ± 0.5 LSB Zero–scale error See Notes 2 and 6 ± 0.5 ± 0.5 LSB EFS Full-scale error See Notes 2 and 6 ± 0.5 ± 0.5 LSB Total unadjusted error See Note 7 ± 0.5 ± 0.5 LSB Self-test output code Input A11 address = 1011, (see Note 8) Conversion time See Operating Sequence 9 17 µs Total access and conversion time See Operating Sequence 13.3 25 µs ta Channel acquisition time (sample cycle) See Operating Sequence 4 4 I/O clock cylces tv Time output data remains valid after I/O CLOCK↓ td Delay time, I/O CLOCK↓ to data output valid tconv 01111101 (125) 10000011 (131) 10 See Parameter M Measurement t Information 01111101 (125) 10000011 (131) 10 ns 300 400 ns 150 150 ns 150 150 ns ten tdis Output enable time tr(bus) tf(bus) Data bus rise time 300 300 ns Data bus fall time 300 300 ns Output disable time NOTES: 2. Analog input voltages greater than that applied to REF+ convert to all “1”s (11111111) while input voltages less than that applied to REF– convert to all “0”s (00000000). For proper operation, REF+ voltage must be at least 1 V higher than REF– voltage. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V. 5. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics. 6. Zero-scale error is the difference between 00000000 and the converted output for zero input voltage; full-scale error is the difference between 11111111 and the converted output for full-scale input voltage. 7. Total unadjusted error is the sum of linearity, zero-scale, and full-scale errors. 8. Both the input address and the output codes are expressed in positive logic. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065A – OCTOBER 1983 – REVISED MARCH 1995 PARAMETER MEASUREMENT INFORMATION VCC 1.4 V 3 kΩ 3 kΩ Test Point Output Under Test CL (see Note A) Test Point Output Under Test CL (see Note A) 3 kΩ See Note B See Note B LOAD CIRCUIT FOR td, tr, AND tf Test Point Output Under Test CL (see Note A) LOAD CIRCUIT FOR tPZL AND tPLZ LOAD CIRCUIT FOR tPZH AND tPHZ VCC 50% CS 0V SYSTEM CLOCK tPZL tPLZ VCC Output Waveform 1 (see Note C) 50% See Note B 10% tPZH 0V tPHZ 90% Output Waveform 2 (see Note C) VOH 50% 0V VOLTAGE WAVEFORMS FOR ENABLE AND DISABLE TIMES I/O CLOCK 0.8 V 2.4 V Output 0.4 V td 2.4 V DATA OUT 0.8 V tr tf VOLTAGE WAVEFORMS FOR RISE AND FALL TIMES VOLTAGE WAVEFORMS FOR DELAY TIME NOTES: A. CL = 50 pF for TLC540 and 100 pF for TLC541. B. ten = tPZH or tPZL, tdis = tPHZ or tPLZ. C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065A – OCTOBER 1983 – REVISED MARCH 1995 APPLICATION INFORMATION simplified analog input analysis Using the equivalent circuit in Figure 1, the time required to charge the analog input capacitance from 0 to VS within 1/2 LSB can be derived as follows: ǒ Ǔ The capacitance charging voltage is given by V C + VS 1–e–tcńRtCi (1) where Rt = Rs + ri The final voltage to 1/2 LSB is given by VC (1/2 LSB) = VS – (VS /512) (2) ǒ Ǔ Equating equation 1 to equation 2 and solving for time tc gives V and S * ǒ V Ǔ ń512 + VS 1–e–tcńRtCi S (3) tc (1/2 LSB) = Rt × Ci × ln(512) (4) Therefore, with the values given the time for the analog input signal to settle is tc (1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(512) (5) This time must be less than the converter sample time shown in the timing diagrams. Driving Source† TLC540/1 Rs VS VI ri VC 1 kΩ MAX Ci 50 pF MAX VI = Input Voltage at INPUT A0 – A10 VS = External Driving Source Voltage Rs = Source Resistance ri = Input Resistance Ci = Equivalent Input Capacitance † Driving source requirements: • Noise and distortion for the source must be equivalent to the resolution of the converter. • Rs must be real at the input frequency. Figure 1. Equivalent Input Circuit Including the Driving Source 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065A – OCTOBER 1983 – REVISED MARCH 1995 PRINCIPLES OF OPERATION The TLC540 and TLC541 are each complete data acquisition systems on a single chip. They include such functions as analog multiplexer, sample and hold, 8-bit A/D converter, data and control registers, and control logic. For flexibility and access speed, there are four control inputs [two clocks, chip select (CS), and address]. These control inputs and a TTL-compatible 3-state output are intended for serial communications with a microprocessor or microcomputer. With judicious interface timing, with TLC540 a conversion can be completed in 9 µs, while complete input-conversion-output cycles can be repeated every 13 µs. With TLC541 a conversion can be completed in 17 µs, while complete input-conversion-output cycles are repeated every 25 µs. Furthermore, this fast conversion can be executed on any of 11 inputs or its built-in self-test and in any order desired by the controlling processor. The system and I/O clocks are normally used independently and do not require any special speed or phase relationships between them. This independence simplifies the hardware and software control tasks for the device. Once a clock signal within the specification range is applied to SYSTEM CLOCK, the control hardware and software need only be concerned with addressing the desired analog channel, reading the previous conversion result, and starting the conversion by using I/O CLOCK. SYSTEM CLOCK will drive the conversion crunching circuitry so that the control hardware and software need not be concerned with this task. When CS is high, DATA OUT is in a 3-state condition and ADDRESS INPUT and I/O CLOCK are disabled. This feature allows each of these terminals, with the exception of CS, to share a control logic point with their counterpart terminals on additional A/D devices when additional TLC540/541 devices are used. In this way, the above feature serves to minimize the required control logic terminals when using multiple A/D devices. The control sequence has been designed to minimize the time and effort required to initiate conversion and obtain the conversion result. A normal control sequence is: 1. CS is brought low. To minimize errors caused by noise at CS, the internal circuitry waits for two rising edges and then a falling edge of SYSTEM CLOCK after a low CS transition, before the low transition is recognized. This technique is used to protect the device against noise when the device is used in a noisy environment. The MSB of the previous conversion result automatically appears on DATA OUT. 2. A new positive-logic multiplexer address is shifted in on the first four rising edges of I/O CLOCK. The MSB of the address is shifted in first. The negative edges of these four I/O clock pulses shift out the second, third, fourth, and fifth most significant bits of the previous conversion result. The on-chip sample and hold begins sampling the newly addressed analog input after the fourth falling edge. The sampling operation basically involves the charging of internal capacitors to the level of the analog input voltage. 3. Three clock cycles are then applied to I/O CLOCK and the sixth, seventh, and eighth conversion bits are shifted out on the negative edges of these clock cycles. 4. The final eighth clock cycle is applied to I/O CLOCK. The falling edge of this clock cycle completes the analog sampling process and initiates the hold function. Conversion is then performed during the next 36 system clock cycles. After this final I/O clock cycle, CS must go high or the I/O CLOCK must remain low for at least 36 system clock cycles to allow for the conversion function. CS can be kept low during periods of multiple conversion. When keeping CS low during periods of multiple conversion, special care must be exercised to prevent noise glitches on I/O CLOCK. If glitches occur on I/O CLOCK, the I/O sequence between the microprocessor/controller and the device loses synchronization. Also, if CS is taken high, it must remain high until the end of the conversion. Otherwise, a valid falling edge of CS causes a reset condition, which aborts the conversion in progress. A new conversion can be started and the ongoing conversion simultaneously aborted by performing steps 1 through 4 before the 36 system clock cycles occur. Such action yields the conversion result of the previous conversion and not the ongoing conversion. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLC540I, TLC541I 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS SLAS065A – OCTOBER 1983 – REVISED MARCH 1995 PRINCIPLES OF OPERATION It is possible to connect SYSTEM CLOCK and I/O clock together in special situations in which controlling circuitry points must be minimized. In this case, the following special points must be considered in addition to the requirements of the normal control sequence previously described. 1. The first two clocks are required for this device to recognize CS is at a valid low level when the common clock signal is used as an I/O CLOCK. When CS is recognized by the device to be at a high level, the common clock signal is used for the conversion clock also. 2. A low CS must be recognized before the I/O CLOCK can shift in an analog channel address. The device recognizes a CS transition when the SYSTEM CLOCK terminal receives two positive edges and then a negative edge. For this reason, after a CS negative edge, the first two clock cycles do not shift in the address. Also, upon shifting in the address, CS must be raised after the eighth valid (10 total) I/O CLOCK. Otherwise, additional common clock cycles are recognized as I/O CLOCKS and will shift in an erroneous address. For certain applications, such as strobing applications, it is necessary to start conversion at a specific point in time. This device accommodates these applications. Although the on-chip sample and hold begins sampling upon the negative edge of the fourth valid I/O clock cycle, the hold function is not initiated until the negative edge of the eighth valid I/O clock cycle. Thus, the control circuitry can leave the I/O clock signal in its high state during the eighth valid I/O clock cycle until the moment at which the analog signal must be converted. The TLC540/TLC541 continues sampling the analog input until the eighth falling edge of the I/O clock. The control circuitry or software then immediately lowers the I/O clock signal and holds the analog signal at the desired point in time and start conversion. Detailed information on interfacing to most popular microprocessors is readily available from the factory. 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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