MCP631/2/3/5 24 MHz, 2.5 mA Op Amps Features Description • • • • • • • • The Microchip Technology, Inc. MCP631/2/3/5 family of operational amplifiers features high gain bandwidth product (24 MHz, typical) and high output short circuit current (70 mA, typical). Some also provide a Chip Select pin (CS) that supports a low power mode of operation. These amplifiers are optimized for high speed, low noise and distortion, single-supply operation with rail-to-rail output and an input that includes the negative rail. Gain Bandwidth Product: 24 MHz (typical) Short Circuit Current: 70 mA (typical) Noise: 10 nV/√Hz (typical, at 1 MHz) Rail-to-Rail Output Slew Rate: 10 V/µs (typical) Supply Current: 2.5 mA (typical) Power Supply: 2.5V to 5.5V Extended Temperature Range: -40°C to +125°C This family is offered in single (MCP631), single with CS pin (MCP633), dual (MCP632) and dual with two CS pins (MCP635). All devices are fully specified from -40°C to +125°C. Typical Applications • • • • Driving A/D Converters Power Amplifier Control Loops Barcode Scanners Optical Detector Amplifier Typical Application Circuit Design Aids • • • • • • R1 VDD/2 R2 VOUT RL R3 SPICE Macro Models FilterLab® Software Mindi™ Circuit Designer & Simulator Microchip Advanced Part Selector (MAPS) Analog Demonstration and Evaluation Boards Application Notes VIN MCP63X Power Driver with High Gain Package Types MCP631 SOIC NC 1 8 NC MCP633 SOIC MCP632 SOIC VOUTA 1 8 VDD VIN– 2 7 VDD VINA– 2 7 VOUTB VIN+ 3 6 VOUT VINA+ 3 6 VINB– 5 VINB+ VSS 4 VSS 4 5 NC MCP635 MSOP 8 CS VOUTA 1 VIN– 2 7 VDD VIN+ 3 6 VOUT VINA– 2 VINA+ 3 NC 1 VSS 4 5 NC VSS 4 CSA 5 MCP632 3x3 DFN * VOUTA 1 8 VDD VINA– 2 7 VOUTB VINA+ 3 6 VINB– VSS 4 5 VINB+ 10 VDD 9 VOUTB 8 VINB– 7 VINB+ 6 CSB MCP635 3x3 DFN * VOUTA VINA– VINA+ VSS CSA 1 2 3 4 5 10 VDD 9 8 7 6 VOUTB VINB– VINB+ CSB * Includes Exposed Thermal Pad (EP); see Table 3-1. © 2009 Microchip Technology Inc. DS22197A-page 1 MCP631/2/3/5 NOTES: DS22197A-page 2 © 2009 Microchip Technology Inc. MCP631/2/3/5 1.0 ELECTRICAL CHARACTERISTICS 1.1 Absolute Maximum Ratings † † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. VDD – VSS .......................................................................6.5V Current at Input Pins ....................................................±2 mA Analog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD + 1.0V All other Inputs and Outputs .......... VSS – 0.3V to VDD + 0.3V Output Short Circuit Current ................................ Continuous Current at Output and Supply Pins ..........................±150 mA Storage Temperature ...................................-65°C to +150°C Max. Junction Temperature ........................................ +150°C ESD protection on all pins (HBM, MM) ................≥ 1 kV, 200V 1.2 †† See Section 4.1.2 “Input Voltage and Current Limits”. Specifications TABLE 1-1: DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/3, VOUT ≈ VDD/2, VL = VDD/2, RL = 2 kΩ to VL and CS = VSS (refer to Figure 1-2). Parameters Sym Min Typ Max Units Conditions Input Offset Input Offset Voltage Input Offset Voltage Drift Power Supply Rejection Ratio VOS -8 ±1.8 +8 ΔVOS/ΔTA — ±2.0 — PSRR 61 76 — mV µV/°C TA= -40°C to +125°C dB Input Current and Impedance IB — 4 — pA Across Temperature IB — 100 — pA TA= +85°C Across Temperature IB — 1500 5,000 pA TA= +125°C IOS — ±2 — pA 13 Input Bias Current Input Offset Current Common Mode Input Impedance ZCM — 10 ||9 — Ω||pF Differential Input Impedance ZDIFF — 1013||2 — Ω||pF Common-Mode Input Voltage Range VCMR VSS − 0.3 — VDD − 1.3 V (Note 1) Common-Mode Rejection Ratio CMRR 63 78 — dB VDD = 2.5V, VCM = -0.3 to 1.2V CMRR 66 81 — dB VDD = 5.5V, VCM = -0.3 to 4.2V AOL 88 115 — dB VDD = 2.5V, VOUT = 0.3V to 2.2V AOL 94 124 — dB VDD = 5.5V, VOUT = 0.3V to 5.2V VOL, VOH VSS + 20 — VDD − 20 mV VDD = 2.5V, G = +2, 0.5V Input Overdrive VOL, VOH VSS + 40 — VDD − 40 mV VDD = 5.5V, G = +2, 0.5V Input Overdrive ISC ±40 ±85 ±130 mA VDD = 2.5V (Note 2) ISC ±35 ±70 ±110 mA VDD = 5.5V (Note 2) VDD 2.5 — 5.5 V IQ 1.2 2.5 3.6 mA Common Mode Open Loop Gain DC Open Loop Gain (large signal) Output Maximum Output Voltage Swing Output Short Circuit Current Power Supply Supply Voltage Quiescent Current per Amplifier Note 1: 2: No Load Current See Figure 2-5 for temperature effects. The ISC specifications are for design guidance only; they are not tested. © 2009 Microchip Technology Inc. DS22197A-page 3 MCP631/2/3/5 TABLE 1-2: AC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS (refer to Figure 1-2). Parameters Sym Min Typ Max Units Conditions GBWP — 24 — MHz PM — 65 — ° ROUT — 20 — Ω THD+N — 0.0015 — % G = +1, VOUT = 2VP-P, f = 1 kHz, VDD = 5.5V, BW = 80 kHz G = +1, VOUT = 100 mVP-P AC Response Gain Bandwidth Product Phase Margin Open Loop Output Impedance G = +1 AC Distortion Total Harmonic Distortion plus Noise Step Response tr — 20 — ns SR — 10 — V/µs G = +1 Input Noise Voltage Eni — 16 — µVP-P f = 0.1 Hz to 10 Hz Input Noise Voltage Density eni — 10 — nV/√Hz f = 1 MHz Input Noise Current Density ini 4 — fA/√Hz f = 1 kHz Rise Time, 10% to 90% Slew Rate Noise TABLE 1-3: DIGITAL ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS (refer to Figure 1-1 and Figure 1-2). Parameters Sym Min Typ Max Units Conditions CS Logic Threshold, Low VIL VSS — 0.2VDD V CS Input Current, Low ICSL — 0.1 — nA CS Logic Threshold, High VIH 0.8VDD VDD V CS Input Current, High ICSH — 0.7 — µA GND Current ISS -2 -1 — µA CS Internal Pull Down Resistor RPD — 5 — MΩ IO(LEAK) — 50 — nA VHYST — 0.25 — V CS High to Amplifier Off Time (output goes High-Z) tOFF — 200 — ns G = +1 V/V, VL = VSS CS = 0.8VDD to VOUT = 0.1(VDD/2) CS Low to Amplifier On Time tON — 2 10 µs G = +1 V/V, VL = VSS, CS = 0.2VDD to VOUT = 0.9(VDD/2) CS Low Specifications CS = 0V CS High Specifications Amplifier Output Leakage CS = VDD CS = VDD, TA = +125°C CS Dynamic Specifications CS Input Hysteresis DS22197A-page 4 © 2009 Microchip Technology Inc. MCP631/2/3/5 TABLE 1-4: TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V, VSS = GND. Parameters Sym Min Typ Max Units Specified Temperature Range TA -40 — +125 °C Operating Temperature Range TA -40 — +125 °C Storage Temperature Range TA -65 — +150 °C Conditions Temperature Ranges (Note 1) Thermal Package Resistances Thermal Resistance, 8L-3x3 DFN θJA — 60 — °C/W Thermal Resistance, 8L-SOIC θJA — 149.5 — °C/W Thermal Resistance, 10L-3x3 DFN θJA — 57 — °C/W Thermal Resistance, 10L-MSOP θJA — 202 — °C/W (Note 2) Operation must not cause TJ to exceed Maximum Junction Temperature specification (+150°C). Measured on a standard JC51-7, four layer printed circuit board with ground plane and vias. Note 1: 2: 1.3 (Note 2) Timing Diagram EQUATION 1-1: G DM = R F ⁄ R G ICS 0.1 nA (typical) 0.7 µA (typical) VIH VIL CS tON VOUT tOFF G N = 1 + G DM V CM = V P ( 1 – 1 ⁄ G N ) + V REF ( 1 ⁄ G N ) V OST = V IN– – V IN+ V OUT = V REF + ( V P – V M )G DM + V OST G N Where: GDM = Differential Mode Gain High-Z FIGURE 1-1: High-Z On -2.5 mA (typical) -1 µA ISS (typical) 1.4 0.7 µA (typical) -1 µA (typical) (V/V) GN = Noise Gain (V/V) VCM = Op Amp’s Common Mode Input Voltage (V) VOST = Op Amp’s Total Input Offset Voltage (mV) Timing Diagram. Test Circuits The circuit used for most DC and AC tests is shown in Figure 1-2. It independently sets VCM and VOUT; see Equation 1-1. The circuit’s common mode voltage is (VP + VM)/2, not VCM. VOST includes VOS plus the effects of temperature, CMRR, PSRR and AOL. CF 6.8 pF RG 10 kΩ RF 10 kΩ VREF = VDD/2 VP VDD VIN+ CB1 100 nF MCP63X CB2 2.2 µF VIN– VM RG 10 kΩ RL 2 kΩ RF 10 kΩ CF 6.8 pF VOUT CL 50 pF VL FIGURE 1-2: AC and DC Test Circuit for Most Specifications. © 2009 Microchip Technology Inc. DS22197A-page 5 MCP631/2/3/5 NOTES: DS22197A-page 6 © 2009 Microchip Technology Inc. MCP631/2/3/5 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS. DC Signal Inputs Percentage of Occurrences 14% 396 Samples TA = +25°C VDD = 2.5V and 5.5V 12% 10% 8% 6% 4% 2% 0% -6 -5 -4 -3 -2 -1 0 1 2 3 Input Offset Voltage (mV) FIGURE 2-1: 14% 12% 5 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 -2.4 -2.6 -2.8 -3.0 6 Input Offset Voltage. Representative Part VDD = 2.5V VDD = 5.5V 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) FIGURE 2-4: Output Voltage. 0.0 398 Samples VDD = 2.5V and 5.5V TA = -40°C to +125°C Low Input Common Mode Headroom (V) Percentage of Occurrences 16% 4 Input Offset Voltage (mV) 2.1 10% 8% 6% 4% 2% 0% 1 Lot Low (VCMR_L – VSS) -0.1 -0.2 -0.3 VDD = 2.5V and 5.5V -0.4 -0.5 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 -50 -25 Input Offset Voltage Drift (µV/°C) -2.0 -2.2 -2.4 -2.6 -2.8 -3.0 -3.2 -3.4 -3.6 -3.8 -4.0 Input Offset Voltage Drift. 1.3 Representative Part VCM = VSS +125°C +85°C +25°C -40°C 0 25 50 75 100 Ambient Temperature (°C) 125 FIGURE 2-5: Low Input Common Mode Voltage Headroom vs. Ambient Temperature. High Input Common Mode Headroom (V) Input Offset Voltage (mV) FIGURE 2-2: Input Offset Voltage vs. 1 Lot High (VDD – VCMR_H) 1.2 VDD = 2.5V 1.1 1.0 VDD = 5.5V 0.9 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 Power Supply Voltage (V) FIGURE 2-3: Input Offset Voltage vs. Power Supply Voltage with VCM = 0V. © 2009 Microchip Technology Inc. -50 -25 0 25 50 75 100 Ambient Temperature (°C) 125 FIGURE 2-6: High Input Common Mode Voltage Headroom vs. Ambient Temperature. DS22197A-page 7 MCP631/2/3/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS. 1.5 130 VDD = 2.5V Representative Part DC Open-Loop Gain (dB) Input Offset Voltage (mV) 2.0 +125°C +85°C +25°C -40°C 1.0 0.5 0.0 -0.5 -1.0 -1.5 VDD = 5.5V 120 115 VDD = 2.5V 110 105 100 3.0 2.5 2.0 1.5 1.0 0.5 -0.5 0.0 -2.0 125 -50 -25 Input Common Mode Voltage (V) FIGURE 2-7: Input Offset Voltage vs. Common Mode Voltage with VDD = 2.5V. 1.5 1.0 +125°C +85°C +25°C -40°C 0.5 0.0 -0.5 -1.0 -1.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -2.0 Input Common Mode Voltage (V) VDD = 5.5V 125 120 115 VDD = 2.5V 110 105 100 95 100 1.E+02 1k 10k 1.E+03 1.E+04 Load Resistance (Ω) FIGURE 2-11: Load Resistance. FIGURE 2-8: Input Offset Voltage vs. Common Mode Voltage with VDD = 5.5V. 1.E-08 10n Input Bias, Offset Currents (pA) CMRR, PSRR (dB) 125 130 VDD = 5.5V Representative Part 110 105 100 95 90 85 80 75 70 65 60 100 FIGURE 2-10: DC Open-Loop Gain vs. Ambient Temperature. DC Open-Loop Gain (dB) Input Offset Voltage (mV) 2.0 0 25 50 75 Ambient Temperature (°C) 100k 1.E+05 DC Open-Loop Gain vs. VDD = 5.5V VCM = VCMR_H 1n 1.E-09 CMRR, VDD = 2.5V CMRR, VDD = 5.5V 100p 1.E-10 IB 10p 1.E-11 PSRR | IOS | 1p 1.E-12 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 FIGURE 2-9: CMRR and PSRR vs. Ambient Temperature. DS22197A-page 8 125 25 45 65 85 105 Ambient Temperature (°C) 125 FIGURE 2-12: Input Bias and Offset Currents vs. Ambient Temperature with VDD = +5.5V. © 2009 Microchip Technology Inc. MCP631/2/3/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS. 2000 FIGURE 2-13: Input Bias Current vs. Input Voltage (below VSS). Representative Part TA = +125°C VDD = 5.5V 6.0 5.5 5.0 4.5 -1500 4.0 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 Input Voltage (V) -1000 3.5 10p 1.E-11 1p 1.E-12 -500 3.0 +125°C +85°C +25°C -40°C IOS 0 2.5 1n 1.E-09 100p 1.E-10 500 2.0 100n 1.E-07 10n 1.E-08 1000 1.5 1µ 1.E-06 1.0 10µ 1.E-05 IB 1500 0.5 100µ 1.E-04 0.0 Input Bias, Offset Currents (pA) Input Current Magnitude (A) 1.E-03 1m Common Mode Input Voltage (V) FIGURE 2-15: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +125°C. 150 IB 100 50 0 IOS -50 -100 -150 Representative Part TA = +85°C VDD = 5.5V 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 -200 0.0 Input Bias, Offset Currents (pA) 200 Common Mode Input Voltage (V) FIGURE 2-14: Input Bias and Offset Currents vs. Common Mode Input Voltage with TA = +85°C. © 2009 Microchip Technology Inc. DS22197A-page 9 MCP631/2/3/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS. Other DC Voltages and Currents 3.5 3.0 Supply Current (mA/amplifier) VDD = 5.5V 100 VDD = 2.5V VOL – VSS 10 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 100 Power Supply Voltage (V) FIGURE 2-19: Supply Voltage. Supply Current vs. Power 3.5 RL = 2 kΩ 3.0 Supply Current (mA/amplifier) VOL – VSS VDD = 5.5V VDD = 5.5V 2.5 2.0 VDD = 2.5V 1.5 1.0 0.5 6.0 5.5 5.0 4.5 4.0 Common Mode Input Voltage (V) FIGURE 2-17: Output Voltage Headroom vs. Ambient Temperature. 100 80 60 40 20 0 -20 -40 -60 -80 -100 3.5 125 3.0 100 2.5 0.0 0 25 50 75 Ambient Temperature (°C) 2.0 -25 1.5 -50 VDD – VOH 1.0 VDD = 2.5V -0.5 Output Headroom (mV) 1.0 0.0 1 10 Output Current Magnitude (mA) FIGURE 2-16: Output Voltage Headroom vs. Output Current. FIGURE 2-20: Supply Current vs. Common Mode Input Voltage. 6.5 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 +125°C +85°C +25°C -40°C 0.0 Output Short Circuit Current (mA) +125°C +85°C +25°C -40°C 1.5 0.0 1 20 18 16 14 12 10 8 6 4 2 0 2.0 0.5 VDD – VOH 0.1 2.5 0.5 Output Voltage Headroom (mV) 1000 0.0 2.2 Power Supply Voltage (V) FIGURE 2-18: Output Short Circuit Current vs. Power Supply Voltage. DS22197A-page 10 © 2009 Microchip Technology Inc. MCP631/2/3/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS. Frequency Response 34 80 70 60 50 CMRR PSRR+ PSRR- 30 20 55 24 50 22 45 GBWP 0 36 -30 34 100 -60 ∠AOL -90 60 -120 40 -150 | AOL | -180 0 -210 -20 -240 65 60 55 50 22 GBWP 20 -50 -25 0 25 50 75 100 Ambient Temperature (°C) 45 40 125 FIGURE 2-23: Gain Bandwidth Product and Phase Margin vs. Ambient Temperature. © 2009 Microchip Technology Inc. Closed-Loop Output Impedance (Ω) 70 Phase Margin (°) 32 24 6.0 5.5 5.0 4.0 3.5 4.5 60 26 55 24 50 22 45 GBWP 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Voltage (V) 80 75 VDD = 5.5V VDD = 2.5V 65 VDD = 5.5V VDD = 2.5V 28 FIGURE 2-25: Gain Bandwidth Product and Phase Margin vs. Output Voltage. 34 30 70 20 Open-Loop Gain vs. PM 75 PM 30 Frequency (Hz) 36 80 32 1 1.E+1 1M 10M 10 1.E+2 100 1.E+3 1k 1.E+4 10k 100k 1.E+0 1.E+5 1.E+6 1.E+7 100M 1.E+8 FIGURE 2-22: Frequency. 3.0 FIGURE 2-24: Gain Bandwidth Product and Phase Margin vs. Common Mode Input Voltage. 120 20 2.5 Common Mode Input Voltage (V) CMRR and PSRR vs. 80 2.0 40 1.5 10M 1.E+7 1.0 1M 1.E+6 0.5 100k 1.E+5 Frequency (Hz) 0.0 10k 1.E+4 Gain Bandwidth Product (MHz) Open-Loop Gain (dB) 60 26 140 Gain Bandwidth Product (MHz) 65 VDD = 5.5V VDD = 2.5V 28 -0.5 1k 1.E+3 FIGURE 2-21: Frequency. 26 70 30 20 10 100 1.E+2 28 75 PM 32 Phase Margin (°) 40 80 Phase Margin (°) 36 90 Gain Bandwidth Product (MHz) 100 Open-Loop Phase (°) CMRR, PSRR (dB) 2.3 100 10 G = 101 V/V G = 11 V/V G = 1 V/V 1 0.1 10k 1.0E+04 100k 1.0E+05 1M 10M 1.0E+06 1.0E+07 Frequency (Hz) 100M 1.0E+08 FIGURE 2-26: Closed-Loop Output Impedance vs. Frequency. DS22197A-page 11 MCP631/2/3/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS. 10 8 GN = 1 V/V GN = 2 V/V GN ≥ 4 V/V 7 6 5 4 3 2 1 0 10p 1.0E-11 100p 1n 1.0E-10 1.0E-09 Normalized Capacitive Load; CL/GN (F) FIGURE 2-27: Gain Peaking vs. Normalized Capacitive Load. DS22197A-page 12 Channel-to-Channel Separation; RTI (dB) Gain Peaking (dB) 9 150 140 130 120 110 100 90 80 70 RS = 10 kΩ 60 RS = 100 kΩ 50 1k 10k 1.E+03 1.E+04 RS = 0Ω RS = 100Ω RS = 1 kΩ VCM = VDD/2 G = +1 V/V 100k 1M 1.E+05 1.E+06 Frequency (Hz) 10M 1.E+07 FIGURE 2-28: Channel-to-Channel Separation vs. Frequency. © 2009 Microchip Technology Inc. MCP631/2/3/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS. Noise and Distortion 1.E+4 10µ Input Noise; e ni(t) (µV) 20 1.E+3 1µ 100n 1.E+2 10n 1.E+1 1 1.E+0 10 1.E+1 10 5 0 -5 -10 Analog NPBW = 0.1 Hz Sample Rate = 2 SPS VOS = -3150 µV -15 100 1.E+2 1k 1.E+3 0 100k 10M 1M 1.E+7 1.E+5 1.E+6 10k 1.E+4 Frequency (Hz) Input Noise Voltage Density 5 10 15 20 25 30 35 40 45 50 55 60 65 Time (min) FIGURE 2-32: 0.1 Hz Filter. THD + Noise (%) VDD = 2.5V VDD = 5.5V 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.0 0.5 FIGURE 2-30: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 100 Hz. 0.01 0.001 0.0001 100 1.E+2 FIGURE 2-33: VDD = 5.0V VOUT = 2 VP-P 1k 1.E+3 10k 1.E+4 Frequency (Hz) 100k 1.E+5 THD+N vs. Frequency. VDD = 2.5V VDD = 5.5V 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 f = 1 MHz -0.5 Input Noise Voltage Density (nV/√Hz) G = 1 V/V G = 11 V/V BW = 22 Hz to > 500 kHz BW = 22 Hz to 80 kHz f = 100 Hz 0.0 0.1 Common Mode Input Voltage (V) 20 18 16 14 12 10 8 6 4 2 0 Input Noise vs. Time with 1 -0.5 Input Noise Voltage Density (nV/√Hz) FIGURE 2-29: vs. Frequency. 200 180 160 140 120 100 80 60 40 20 0 Representative Part 15 -20 1n 1.E+0 0.1 1.E-1 1.5 Input Noise Voltage Density (V/√Hz) 2.4 Common Mode Input Voltage (V) FIGURE 2-31: Input Noise Voltage Density vs. Input Common Mode Voltage with f = 1 MHz. © 2009 Microchip Technology Inc. DS22197A-page 13 MCP631/2/3/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS. 2.5 Time Response 0.0 0.1 VOUT 0.2 Output Voltage (V) FIGURE 2-34: Step Response. 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 Output Voltage (V) VIN 0.3 0.4 0.5 Time (µs) 0.6 0.7 Non-inverting Small Signal VIN VOUT 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Time (µs) FIGURE 2-37: Response. Inverting Large Signal Step VOUT VDD = 5.5V G=2 6 VOUT 5 VIN 4 3 2 1 0 -1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 Time (µs) FIGURE 2-35: Step Response. Non-inverting Large Signal 0 Slew Rate (V/µs) Output Voltage (10 mV/div) VDD = 5.5V G = -1 RF = 1 kΩ VOUT 0.1 0.2 FIGURE 2-36: Response. DS22197A-page 14 0.3 0.4 0.5 Time (µs) 0.6 0.7 0.8 Inverting Small Signal Step 1 2 3 4 5 6 Time (ms) 7 8 9 10 FIGURE 2-38: The MCP631/2/3/5 family shows no input phase reversal with overdrive. VIN 0.0 VDD = 5.5V G = -1 RF = 1 kΩ 7 VDD = 5.5V G=1 VIN 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0.8 Input, Output Voltages (V) Output Voltage (10 mV/div) VDD = 5.5V G=1 24 22 20 18 16 14 12 10 8 6 4 2 0 Falling Edge VDD = 5.5V VDD = 2.5V Rising Edge -50 -25 FIGURE 2-39: Temperature. 0 25 50 75 Ambient Temperature (°C) 100 125 Slew Rate vs. Ambient © 2009 Microchip Technology Inc. MCP631/2/3/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS. Maximum Output Voltage Swing (V P-P ) 10 VDD = 5.5V VDD = 2.5V 1 0.1 100k 1.E+05 1M 10M 1.E+06 1.E+07 Frequency (Hz) 100M 1.E+08 FIGURE 2-40: Maximum Output Voltage Swing vs. Frequency. © 2009 Microchip Technology Inc. DS22197A-page 15 MCP631/2/3/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS. Chip Select Response 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.40 CS = VDD 0.35 CS Hysteresis (V) CS Current (µA) 2.6 0.30 0.25 0.15 0.05 0.00 FIGURE 2-41: Supply Voltage. -50 CS 2.0 1.5 VOUT 1.0 On 0.5 0.0 Off 100 125 CS Hysteresis vs. Ambient 4 3 VDD = 2.5V 2 1 VDD = 5.5V Off 0 -0.5 2 4 6 8 10 12 Time (µs) 14 16 18 20 FIGURE 2-42: CS and Output Voltages vs. Time with VDD = 2.5V. 6 4 3 VOUT 2 On 1 -25 Off Off 0 25 50 75 Ambient Temperature (°C) 100 125 FIGURE 2-45: CS Turn On Time vs. Ambient Temperature. 8 VDD = 5.5V G=1 VL = 0V CS 5 -50 CS Pull-down Resistor (MΩ) 0 0 0 25 50 75 Ambient Temperature (°C) 5 VDD = 2.5V G=1 VL = 0V CS Turn On Time (µs) 2.5 -25 FIGURE 2-44: Temperature. CS Current vs. Power 3.0 CS, V OUT (V) VDD = 2.5V 0.10 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Power Supply Voltage (V) CS, V OUT (V) VDD = 5.5V 0.20 Representative Part 7 6 5 4 3 2 1 0 -1 0 2 4 6 8 10 12 Time (µs) 14 16 18 20 FIGURE 2-43: CS and Output Voltages vs. Time with VDD = 5.5V. DS22197A-page 16 -50 -25 0 25 50 75 Ambient Temperature (°C) 100 125 FIGURE 2-46: CS’s Pull-down Resistor (RPD) vs. Ambient Temperature. © 2009 Microchip Technology Inc. MCP631/2/3/5 Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2, CS = VDD 1.E-06 1µ Output Leakage Current (A) 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 -2.0 -2.2 CS = VDD = 5.5V 1.E-07 100n 10n 1.E-08 1n 1.E-09 FIGURE 2-47: Quiescent Current in Shutdown vs. Power Supply Voltage. 6.5 6.0 5.5 5.0 4.5 4.0 Power Supply Voltage (V) © 2009 Microchip Technology Inc. +125°C +85°C 100p 1.E-10 3.5 3.0 2.5 2.0 1.5 1.0 0.5 -40°C +25°C +85°C +125°C 0.0 Negative Power Supply Current; I SS (µA) VL = VDD/2, RL = 2 kΩ to VL, CL = 50 pF and CS = VSS. +25°C 10p 1.E-11 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Output Voltage (V) FIGURE 2-48: Output Voltage. Output Leakage Current vs. DS22197A-page 17 MCP631/2/3/5 NOTES: DS22197A-page 18 © 2009 Microchip Technology Inc. MCP631/2/3/5 3.0 PIN DESCRIPTIONS Descriptions of the pins are listed in Table 3-1. TABLE 3-1: MCP631 PIN FUNCTION TABLE MCP632 MCP633 MCP635 Symbol Description SOIC SOIC DFN SOIC MSOP DFN 6 2 3 4 1 2 3 4 1 2 3 4 6 2 3 4 1 2 3 4 1 2 3 4 VOUT, VOUTA VIN–, VINA– VIN+, VINA+ VSS — — — 8 5 5 CS, CSA Chip Select Digital Input (op amp A) — — — — 7 1,5,8 — — 5 6 7 8 — — — 5 6 7 8 — 9 — — — — 7 1,5 — 6 7 8 9 10 — — 6 7 8 9 10 — 11 CSB VINB+ VINB– VOUTB VDD NC EP Chip Select Digital Input (op amp B) Non-inverting Input (op amp B) Inverting Input (op amp B) Output (op amp B) Positive Power Supply No Internal Connection Exposed Thermal Pad (EP); must be connected to VSS 3.1 Analog Outputs 3.4 Output (op amp A) Inverting Input (op amp A) Non-inverting Input (op amp A) Negative Power Supply Chip Select Digital Input (CS) The analog output pins (VOUT) are low-impedance voltage sources. This input (CS) is a CMOS, Schmitt-triggered input that places the part into a low power mode of operation. 3.2 3.5 Analog Inputs Exposed Thermal Pad (EP) The non-inverting and inverting inputs (VIN+, VIN–, …) are high-impedance CMOS inputs with low bias currents. There is an internal connection between the Exposed Thermal Pad (EP) and the VSS pin; they must be connected to the same potential on the Printed Circuit Board (PCB). 3.3 This pad can be connected to a PCB ground plane to provide a larger heat sink. This improves the package thermal resistance (θJA). Power Supply Pins The positive power supply (VDD) is 2.5V to 5.5V higher than the negative power supply (VSS). For normal operation, the other pins are between VSS and VDD. Typically, these parts are used in a single (positive) supply configuration. In this case, VSS is connected to ground and VDD is connected to the supply. VDD will need bypass capacitors. © 2009 Microchip Technology Inc. DS22197A-page 19 MCP631/2/3/5 NOTES: DS22197A-page 20 © 2009 Microchip Technology Inc. MCP631/2/3/5 4.0 APPLICATIONS VDD The MCP631/2/3/5 family op amps is manufactured using Microchip’s state of the art CMOS process. It is designed for low cost, low power and high speed applications. Its low supply voltage, low quiescent current and wide bandwidth make the MCP631/2/3/5 ideal for battery-powered applications. 4.1 V1 V2 Input 4.1.1 INPUT VOLTAGE AND CURRENT LIMITS The ESD protection on the inputs can be depicted as shown in Figure 4-1. This structure was chosen to protect the input transistors, and to minimize input bias current (IB). The input ESD diodes clamp the inputs when they try to go more than one diode drop below VSS. They also clamp any voltages that go too far above VDD; their breakdown voltage is high enough to allow normal operation, and low enough to bypass quick ESD events within the specified limits. Input Stage Bond V – IN Pad VOUT R2 FIGURE 4-2: Inputs. Protecting the Analog It is also possible to connect the diodes to the left of the resistor R1 and R2. In this case, the currents through the diodes D1 and D2 need to be limited by some other mechanism. The resistors then serve as in-rush current limiters; the DC current into the input pins (VIN+ and VIN–) should be very small. A significant amount of current can flow out of the inputs (through the ESD diodes) when the common mode voltage (VCM) is below ground (VSS); see Figure 2-13. Applications that are high impedance may need to limit the usable voltage range. NORMAL OPERATION The input stage of the MCP631/2/3/5 op amps uses a differential PMOS input stage. It operates at low common mode input voltages (VCM), with VCM between VSS – 0.3V and VDD – 1.3V. To ensure proper operation, the input offset voltage (VOS) is measured at both VCM = VSS – 0.3V and VDD – 1.3V. See Figure 2-5 and Figure 2-6 for temperature effects. When operating at very low non-inverting gains, the output voltage is limited at the top by the VCM range (< VDD – 1.3V); see Figure 4-3. VSS Bond Pad FIGURE 4-1: Structures. MCP63X VSS – (minimum expected V1) 2 mA VSS – (minimum expected V2) R2 > 2 mA 4.1.3 VDD Bond Pad VIN+ Bond Pad D2 R1 > PHASE REVERSAL The input devices are designed to not exhibit phase inversion when the input pins exceed the supply voltages. Figure 2-38 shows an input voltage exceeding both supplies with no phase inversion. 4.1.2 D1 R1 Simplified Analog Input ESD In order to prevent damage and/or improper operation of these amplifiers, the circuit must limit the currents (and voltages) at the input pins (see Section 1.1 “Absolute Maximum Ratings †”). Figure 4-2 shows the recommended approach to protecting these inputs. The internal ESD diodes prevent the input pins (VIN+ and VIN–) from going too far below ground, and the resistors R1 and R2 limit the possible current drawn out of the input pins. Diodes D1 and D2 prevent the input pins (VIN+ and VIN–) from going too far above VDD, and dump any currents onto VDD. When implemented as shown, resistors R1 and R2 also limit the current through D1 and D2. © 2009 Microchip Technology Inc. VDD VIN MCP63X VOUT V SS < V IN, V OUT ≤ V DD – 1.3V FIGURE 4-3: Unity Gain Voltage Limitations for Linear Operation. DS22197A-page 21 MCP631/2/3/5 4.2 Rail-to-Rail Output 4.2.1 VDD MAXIMUM OUTPUT VOLTAGE IDD The Maximum Output Voltage (see Figure 2-16 and Figure 2-17) describes the output range for a given load. For instance, the output voltage swings to within 50 mV of the negative rail with a 1 kΩ load tied to VDD/2. 4.2.2 VOH Limited RL = 1 kΩ -ISC Limited RL = 100Ω RL = 10Ω 4.2.3 120 80 100 60 40 0 20 -20 -40 -60 -80 -100 POWER DISSIPATION Since the output short circuit current (ISC) is specified at ±70 mA (typical), these op amps are capable of both delivering and dissipating significant power. Figure 4-5 show the quantities used in the following power calculations for a single op amp. RSER is 0 Ω in most applications; it can be used to limit IOUT. VOUT is the op amp’s output voltage, VL is the voltage at the load, and VLG is the load’s ground point. VSS is usually ground (0V). The input currents are assumed to be negligible. The currents shown are approximately: VLG VSS FIGURE 4-5: Calculations. Diagram for Power The instantaneous op amp power (POA(t)), RSER power (PRSER(t)) and load power (PL(t)) are: The maximum op amp power, for resistive loads, occurs when VOUT is halfway between VDD and VLG or halfway between VSS and VLG: EQUATION 4-3: POAmax ≤ max2(VDD – VLG , VLG – VSS) 4(RSER + RL) The maximum ambient to junction temperature rise (ΔTJA) and junction temperature (TJ) can be calculated using POAmax, ambient temperature (TA), the package thermal resistance (θJA) found in Table 1-4, and the number of op amps in the package (assuming equal power dissipations): EQUATION 4-4: ΔTJA = POA(t) θJA ≤ n POAmaxθJA TJ = TA + ΔTJA EQUATION 4-1: RSER + RL RL PL(t) = IL2RL Output Current. VOUT – VLG IL ISS PRSER(t) = IOUT2RSER IOUT (mA) IOUT = IL = VL POA(t) = IDD (VDD – VOUT) + ISS (VSS – VOUT) VOL Limited FIGURE 4-4: RSER EQUATION 4-2: +ISC Limited (VDD = 5.5V) -120 VOUT (V) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -0.5 IOUT MCP63X OUTPUT CURRENT Figure 4-4 shows the possible combinations of output voltage (VOUT) and output current (IOUT), when VDD = 5.5V. IOUT is positive when it flows out of the op amp into the external circuit. VOUT Where: n = number of op amps in package (1, 2) IDD ≈ IQ + max(0, IOUT) ISS ≈ –IQ + min(0, IOUT) Where: IQ = quiescent supply current DS22197A-page 22 © 2009 Microchip Technology Inc. MCP631/2/3/5 The power de-rating across temperature for an op amp in a particular package can be easily calculated (assuming equal power dissipations): EQUATION 4-5: T – TA POAmax ≤ Jmax n θJA = absolute maximum junction temperature Several techniques are available to reduce ΔTJA for a given POAmax: • Lower θJA - Use another package - PCB layout (ground plane, etc.) - Heat sinks and air flow • Reduce POAmax - Increase RL - Limit IOUT (using RSER) - Decrease VDD 4.3 4.3.1 GN = +1 GN ≥ +2 100p 1n 1.E-11 1.E-10 1.E-09 Normalized Capacitance; CL/GN (F) 10n 1.E-08 FIGURE 4-7: Recommended RISO Values for Capacitive Loads. CAPACITIVE LOADS Driving large capacitive loads can cause stability problems for voltage feedback op amps. As the load capacitance increases, the feedback loop’s phase margin decreases and the closed-loop bandwidth is reduced. This produces gain peaking in the frequency response, with overshoot and ringing in the step response. A unity gain buffer (G = +1) is the most sensitive to capacitive loads, though all gains show the same general behavior. When driving large capacitive loads with these op amps (e.g., > 20 pF when G = +1), a small series resistor at the output (RISO in Figure 4-6) improves the feedback loop’s phase margin (stability) by making the output load resistive at higher frequencies. The bandwidth will be generally lower than the bandwidth with no capacitive load. RF 100 10 10p 1.E-12 Improving Stability RG Recommended R ISO (Ω) 1,000 Where: TJmax Figure 4-7 gives recommended RISO values for different capacitive loads and gains. The x-axis is the normalized load capacitance (CL/GN), where GN is the circuit’s noise gain. For non-inverting gains, GN and the Signal Gain are equal. For inverting gains, GN is 1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V). After selecting RISO for your circuit, double check the resulting frequency response peaking and step response overshoot. Modify RISO’s value until the response is reasonable. Bench evaluation and simulations with the MCP631/2/3/5 SPICE macro model are helpful. 4.3.2 GAIN PEAKING Figure 4-8 shows an op amp circuit that represents non-inverting amplifiers (VM is a DC voltage and VP is the input) or inverting amplifiers (VP is a DC voltage and VM is the input). The capacitances CN and CG represent the total capacitance at the input pins; they include the op amp’s common mode input capacitance (CCM), board parasitic capacitance and any capacitor placed in parallel. VP VM RISO VOUT RN CN MCP63X VOUT RG CG RF CL RN MCP63X FIGURE 4-6: Output Resistor, RISO stabilizes large capacitive loads. © 2009 Microchip Technology Inc. FIGURE 4-8: Capacitance. Amplifier with Parasitic CG acts in parallel with RG (except for a gain of +1 V/V), which causes an increase in gain at high frequencies. CG also reduces the phase margin of the feedback loop, which becomes less stable. This effect can be reduced by either reducing CG or RF. DS22197A-page 23 MCP631/2/3/5 CN and RN form a low-pass filter that affects the signal at VP. This filter has a single real pole at 1/(2πRNCN). 1.E+05 100k CG = 10 pF CG = 32 pF CG = 100 pF CG = 320 pF CG = 1 nF Maximum Recommended R (Ω) F The largest value of RF that should be used depends on noise gain (see GN in Section 4.3.1 “Capacitive Loads”), CG and the open-loop gain’s phase shift. Figure 4-9 shows the maximum recommended RF for several CG values. Some applications may modify these values to reduce either output loading or gain peaking (step response overshoot). 10k 1.E+04 1k 1.E+03 GN > +1 V/V 100 1.E+02 1 FIGURE 4-9: RF vs. Gain. 10 Noise Gain; GN (V/V) Figure 2-34 and Figure 2-35 show the small signal and large signal step responses at G = +1 V/V. The unity gain buffer usually has RF = 0Ω and RG open. Figure 2-36 and Figure 2-37 show the small signal and large signal step responses at G = -1 V/V. Since the noise gain is 2 V/V and CG ≈ 10 pF, the resistors were chosen to be RF = RG = 1 kΩ and RN = 500Ω. It is also possible to add a capacitor (CF) in parallel with RF to compensate for the de-stabilizing effect of CG. This makes it possible to use larger values of RF. The conditions for stability are summarized in Equation 4-6. Given: G N1 = 1 + R F ⁄ R G G N2 = 1 + C G ⁄ C F fF = 1 ⁄ ( 2 π RF CF ) f Z = f F ( G N1 ⁄ G N2 ) We need: f F ≤ f GBWP ⁄ ( 2G N2 ) , G N1 < G N2 f F ≤ f GBWP ⁄ ( 4G N1 ) , G N1 > G N2 MCP633 and MCP635 Chip Select The MCP633 is a single amplifier with Chip Select (CS). When CS is pulled high, the supply current drops to 1 µA (typical) and flows through the CS pin to VSS. When this happens, the amplifier output is put into a high-impedance state. By pulling CS low, the amplifier is enabled. The CS pin has an internal 5 MΩ (typical) pulldown resistor connected to VSS, so it will go low if the CS pin is left floating. Figure 1-1, Figure 2-42 and Figure 2-43 show the output voltage and supply current response to a CS pulse. The MCP635 is a dual amplifier with two CS pins; CSA controls op amp A and CSB controls op amp B. These op amps are controlled independently, with an enabled quiescent current (IQ) of 2.5 mA/amplifier (typical) and a disabled IQ of 1 µA/amplifier (typical). The IQ seen at the supply pins is the sum of the two op amps’ IQ; the typical value for the MCP635’s IQ will be 2 µA, 2.5 mA or 5 mA when there are 0, 1 or 2 amplifiers enabled, respectively. 100 Maximum Recommended EQUATION 4-6: 4.4 4.5 Power Supply With this family of operational amplifiers, the power supply pin (VDD for single supply) should have a local bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good high frequency performance. Surface mount, multilayer ceramic capacitors, or their equivalent, should be used. These op amps require a bulk capacitor (i.e., 2.2 µF or larger) within 50 mm to provide large, slow currents. Tantalum capacitors, or their equivalent, may be a good choice. This bulk capacitor can be shared with other nearby analog parts as long as crosstalk through the supplies does not prove to be a problem. 4.6 High Speed PCB Layout These op amps are fast enough that a little extra care in the PCB (Printed Circuit Board) layout can make a significant difference in performance. Good PC board layout techniques will help you achieve the performance shown in the specifications and Typical Performance Curves; it will also help you minimize EMC (Electro-Magnetic Compatibility) issues. Use a solid ground plane. Connect the bypass local capacitor(s) to this plane with minimal length traces. This cuts down inductive and capacitive crosstalk. Separate digital from analog, low speed from high speed, and low power from high power. This will reduce interference. Keep sensitive traces short and straight. Separate them from interfering components and traces. This is especially important for high frequency (low rise time) signals. DS22197A-page 24 © 2009 Microchip Technology Inc. MCP631/2/3/5 Sometimes, it helps to place guard traces next to victim traces. They should be on both sides of the victim trace, and as close as possible. Connect guard traces to ground plane at both ends, and in the middle for long traces. Use coax cables, or low inductance wiring, to route signal and power to and from the PCB. Mutual and self inductance of power wires is often a cause of crosstalk and unusual behavior. 4.7 4.7.3 H-BRIDGE DRIVER Figure 4-12 shows the MCP632 dual op amp used as a H-bridge driver. The load could be a speaker or a DC motor. ½ MCP632 VIN Typical Applications 4.7.1 RF POWER DRIVER WITH HIGH GAIN Figure 4-10 shows a power driver with high gain (1 + R2/R1). The MCP631/2/3/5 op amp’s short circuit current makes it possible to drive significant loads. The calibrated input offset voltage supports accurate response at high gains. R3 should be small, and equal to R1||R2, in order to minimize the bias current induced offset. VDD/2 R1 R2 RL R3 MCP63X VIN FIGURE 4-10: 4.7.2 VOUT OPTICAL DETECTOR AMPLIFIER Figure 4-11 shows a transimpedance amplifier, using the MCP63X op amp, in a photo detector circuit. The photo detector is a capacitive current source. RF provides enough gain to produce 10 mV at VOUT. CF stabilizes the gain and limits the transimpedance bandwidth to about 1.1 MHz. RF’s parasitic capacitance (e.g., 0.2 pF for a 0805 SMD) acts in parallel with CF. CF 1.5 pF ID 100 nA RF 100 kΩ CD 30pF RL RGT RGB VDD/2 RF VOB ½ MCP632 FIGURE 4-12: H-Bridge Driver. This circuit automatically makes the noise gains (GN) equal, when the gains are set properly, so that the frequency responses match well (in magnitude and in phase). Equation 4-7 shows how to calculate RGT and RGB so that both op amps have the same DC gains; GDM needs to be selected first. EQUATION 4-7: Power Driver. Photo Detector VOT RF V OT – V OB G DM ≡ -------------------------------- ≥ 1 V/V V IN – V DD ⁄ 2 RF R GT = -------------------------------( G DM ⁄ 2 ) – 1 RF R GB = -----------------G DM ⁄ 2 Equation 4-8 gives the resulting common mode and differential mode output voltages. EQUATION 4-8: V OT + V OB V DD --------------------------- = ---------2 2 VOUT V DD⎞ V OT – V OB = G DM ⎛ V IN – ---------⎝ 2 ⎠ MCP63X VDD/2 FIGURE 4-11: Transimpedance Amplifier for an Optical Detector. © 2009 Microchip Technology Inc. DS22197A-page 25 MCP631/2/3/5 NOTES: DS22197A-page 26 © 2009 Microchip Technology Inc. MCP631/2/3/5 5.0 DESIGN AIDS Microchip provides the basic design aids needed for the MCP631/2/3/5 family of op amps. 5.1 SPICE Macro Model The latest SPICE macro model for the MCP631/2/3/5 op amps is available on the Microchip web site at www.microchip.com. This model is intended to be an initial design tool that works well in the op amp’s linear region of operation over the temperature range. See the model file for information on its capabilities. Bench testing is a very important part of any design and cannot be replaced with simulations. Also, simulation results using this macro model need to be validated by comparing them to the data sheet specifications and characteristic curves. 5.2 FilterLab® Software Microchip’s FilterLab® software is an innovative software tool that simplifies analog active filter (using op amps) design. Available at no cost from the Microchip web site at www.microchip.com/filterlab, the Filter-Lab design tool provides full schematic diagrams of the filter circuit with component values. It also outputs the filter circuit in SPICE format, which can be used with the macro model to simulate actual filter performance. 5.3 Mindi™ Circuit Designer & Simulator Microchip’s Mindi™ Circuit Designer & Simulator aids in the design of various circuits useful for active filter, amplifier and power management applications. It is a free online circuit designer & simulator available from the Microchip web site at www.microchip.com/mindi. This interactive circuit designer & simulator enables designers to quickly generate circuit diagrams, and simulate circuits. Circuits developed using the Mindi Circuit Designer & Simulator can be downloaded to a personal computer or workstation. 5.4 5.5 Analog Demonstration and Evaluation Boards Microchip offers a broad spectrum of Analog Demonstration and Evaluation Boards that are designed to help customers achieve faster time to market. For a complete listing of these boards and their corresponding user’s guides and technical information, visit the Microchip web site at www.microchip.com/analog tools. Some boards that are especially useful are: • • • • • • MCP6XXX Amplifier Evaluation Board 1 MCP6XXX Amplifier Evaluation Board 2 MCP6XXX Amplifier Evaluation Board 3 MCP6XXX Amplifier Evaluation Board 4 Active Filter Demo Board Kit 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board, P/N SOIC8EV 5.6 Application Notes The following Microchip Application Notes are available on the Microchip web site at www.microchip. com/appnotes and are recommended as supplemental reference resources. • ADN003: “Select the Right Operational Amplifier for your Filtering Circuits”, DS21821 • AN722: “Operational Amplifier Topologies and DC Specifications”, DS00722 • AN723: “Operational Amplifier AC Specifications and Applications”, DS00723 • AN884: “Driving Capacitive Loads With Op Amps”, DS00884 • AN990: “Analog Sensor Conditioning Circuits – An Overview”, DS00990 • AN1228: “Op Amp Precision Design: Random Noise”, DS01228 Some of these application notes, and others, are listed in the design guide: • “Signal Chain Design Guide”, DS21825 Microchip Advanced Part Selector (MAPS) MAPS is a software tool that helps efficiently identify Microchip devices that fit a particular design requirement. Available at no cost from the Microchip website at www.microchip.com/maps, the MAPS is an overall selection tool for Microchip’s product portfolio that includes Analog, Memory, MCUs and DSCs. Using this tool, a customer can define a filter to sort features for a parametric search of devices and export side-by-side technical comparison reports. Helpful links are also provided for Data sheets, Purchase and Sampling of Microchip parts. © 2009 Microchip Technology Inc. DS22197A-page 27 MCP631/2/3/5 NOTES: DS22197A-page 28 © 2009 Microchip Technology Inc. MCP631/2/3/5 6.0 PACKAGING INFORMATION 6.1 Package Marking Information Example 8-Lead DFN (3×3) (MCP632) XXXX YYWW NNN Device MCP632 Note: Code DABM Applies to 8-Lead 3x3 DFN 8-Lead SOIC (150 mil) (MCP631, MCP632, MCP633) XXXXXXXX XXXXYYWW NNN Example Device MCP635 Note: 10-Lead MSOP (MCP635) XXXXXX YWWNNN Legend: XX...X Y YY WW NNN *e3 Note: Example: MCP631E SN e3 0931 256 10-Lead DFN (3×3) (MCP635) XXXX YYWW NNN DABM 0931 256 Code BAFB BAFB 0931 256 Applies to 10-Lead 3x3 DFN Example: 635EUN 931256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( ) can be found on the outer packaging for this package. e3 In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. DS22197A-page 29 MCP631/2/3/5 % !"#$ 2%& %!% *") ' % * $%%"% %% 133)))& &3 * D e b N N L EXPOSED PAD E2 E K NOTE 1 1 2 D2 2 NOTE 1 1 BOTTOM VIEW TOP VIEW A NOTE 2 A3 A1 4% & 5&% 6!&($ 55,, 6 6 67 8 9 % 7;% 9 :./0 %"$$ . 0%%* + ,2 75% ,# ""<"% , 7<"% , ,# ""5% = ( . + +. 0%%5% 5 + .. 0%%%,# "" > = = 0%%<"% +/0 = : +/0 % !"#$%!&'(!%&! %(%")%%%" *&&# "%( %" + * ) !%" & "% ,-. /01 / & %#%! ))%!%% ,21 $& '! !)%!%%'$$&% ! ) 0:/ DS22197A-page 30 © 2009 Microchip Technology Inc. MCP631/2/3/5 % !"#$ 2%& %!% *") ' % * $%%"% %% 133)))& &3 * © 2009 Microchip Technology Inc. DS22197A-page 31 MCP631/2/3/5 & ' (&))* % !"#&'+,$ 2%& %!% *") ' % * $%%"% %% 133)))& &3 * D e N E E1 NOTE 1 1 2 3 α h b h A2 A c φ L A1 L1 4% & 5&% 6!&($ β 55,, 6 6 67 8 9 % 7;% = /0 = ""** . = = %"$$? = . 7<"% , ""*<"% , +/0 75% /0 . :/0 0&$@ %A . = . 2%5% 5 = 2% % 5 ,2 2% I B = 9B 5"* = . 5"<"% ( + = . "$% D .B = .B "$%/%%& E .B = .B % !"#$%!&'(!%&! %(%")%%%" ?$%0% % + & ","%!"&"$ %! "$ %! %#".&& " & "% ,-. /01 / & %#%! ))%!%% ,21 $& '! !)%!%%'$$&% ! ) 0./ DS22197A-page 32 © 2009 Microchip Technology Inc. MCP631/2/3/5 & ' (&))* % !"#&'+,$ 2%& %!% *") ' % * $%%"% %% 133)))& &3 * © 2009 Microchip Technology Inc. DS22197A-page 33 MCP631/2/3/5 - % !"#$ 2%& %!% *") ' % * $%%"% %% 133)))& &3 * D e b N N L K E E2 EXPOSED PAD NOTE 1 1 2 2 1 NOTE 1 D2 BOTTOM VIEW TOP VIEW A A1 A3 NOTE 2 4% & 5&% 6!&($ 55,, 6 6 67 8 % 7;% 9 ./0 %"$$ . 0%%* + ,2 75% ,# ""5% 7<"% , ,# ""<"% , .9 . ( 9 . + 0%%5% 5 + . 0%%%,# "" > = = 0%%<"% +/0 +. 9 +/0 % !"#$%!&'(!%&! %(%")%%%" *&&# "%( %" + * ) !%" & "% ,-. /01 / & %#%! ))%!%% ,21 $& '! !)%!%%'$$&% ! ) 0:+/ DS22197A-page 34 © 2009 Microchip Technology Inc. MCP631/2/3/5 - % !"#$ 2%& %!% *") ' % * $%%"% %% 133)))& &3 * © 2009 Microchip Technology Inc. DS22197A-page 35 MCP631/2/3/5 - )& ' (.#&'$ % 2%& %!% *") ' % * $%%"% %% 133)))& &3 * D N E E1 NOTE 1 1 2 b e A A2 c φ L A1 L1 4% & 5&% 6!&($ 55,, 6 6 67 8 % 7;% = ./0 = ""** . 9. . %"$$ = . 7<"% , ""*<"% , +/0 75% +/0 2%5% 5 2% % 5 /0 : 9 .,2 2% I B = 9B 5"* 9 = + 5"<"% ( . = ++ % !"#$%!&'(!%&! %(%")%%%" & ","%!"&"$ %! "$ %! %#".&& " + & "% ,-. /01 / & %#%! ))%!%% ,21 $& '! !)%!%%'$$&% ! ) 0/ DS22197A-page 36 © 2009 Microchip Technology Inc. MCP631/2/3/5 APPENDIX A: REVISION HISTORY Revision A (August 2009) • Original Release of this Document. © 2009 Microchip Technology Inc. DS22197A-page 37 MCP631/2/3/5 NOTES: DS22197A-page 38 © 2009 Microchip Technology Inc. MCP631/2/3/5 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X /XX Device Temperature Range Package Device: MCP631 MCP631T MCP632 MCP632T MCP633 MCP633T MCP635 MCP635T Temperature Range: E Package: Single Op Amp Single Op Amp (Tape and Reel) (SOIC) Dual Op Amp Dual Op Amp (Tape and Reel) (DFN and SOIC) Single Op Amp with CS Single Op Amp with CS (Tape and Reel) (SOIC) Dual Op Amp with CS Dual Op Amp with CS (Tape and Reel) (DFN and MSOP) = -40°C to +125°C Examples: a) MCP631T-E/SN: Tape and Reel Extended temperature, 8LD SOIC package a) MCP632T-E/MF: Tape and Reel Extended temperature, 8LD DFN package MCP632T-E/SN: Tape and Reel Extended temperature, 8LD SOIC package b) a) MCP633T-E/SN: Tape and Reel Extended temperature, 8LD SOIC package a) MCP635T-E/MF: Tape and Reel Extended temperature, 10LD DFN package MCP635T-E/UN: Tape and Reel Extended temperature, 10LD MSOP package b) MF = Plastic Dual Flat, No Lead (3×3 DFN), 8-lead, 10-lead SN = Plastic Small Outline (3.90 mm), 8-lead UN = Plastic Micro Small Outline (MSOP), 10-lead © 2009 Microchip Technology Inc. DS22197A-page 39 MCP631/2/3/5 NOTES: DS22197A-page 40 © 2009 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2009 Microchip Technology Inc. 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