www.fairchildsemi.com AN-8024 Applying Fairchild Power Switch (FPSTM) FSBH-series to Standby Auxiliary Power Supply The FSBH-series has built-in synchronized slope compensation to achieve stable peak-current-mode control. The proprietary external line compensation ensures constant output power limit over a wide AC input voltage range, from 90VAC to 264VAC and helps optimize the power stage. 1. Introduction The highly integrated FSBH-series consists of an integrated current mode Pulse Width Modulator (PWM) and an avalanche-rugged 700V SenseFET. It is specifically designed for high-performance offline Switch-Mode Power Supplies (SMPS) with minimal external components. Many protection functions, such as open-loop / overload protection (OLP), over-voltage protection (OVP), brownout protection, and over-temperature protection (OTP); are fully integrated into FSBH-series, which improves the SMPS reliability without increasing the system cost. The integrated PWM controller features include a proprietary green-mode function that provides off-time modulation to linearly decrease the switching frequency at light-load conditions to minimize standby power consumption. The PWM controller is manufactured using the BiCMOS process to further reduce power consumption. The green and burst modes function with a low operating current (2.5mA in green mode) to maximize the light load efficiency so that the power supply can meet stringent standby power regulations. This application note presents design consideration to apply FSBH-series to a standby auxiliary power supply with single output. It covers designing the transformer, selecting the components, feedback loop design, and design tips to maximize efficiency. For multi-output applications, refer to Fairchild application note AN-4137. Figure 1. Typical Application Circuit © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/18/09 www.fairchildsemi.com 1 AN-8024 APPLICATION NOTE [STEP-2] Determine the Input Capacitor (CIN) and the Input Voltage Range 2. Design Considerations Flyback converters have two kinds of operation modes; Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). CCM and DCM each has advantages and disadvantages. In general, DCM provides better switching conditions for the rectifier diodes, since the diodes are operating at zero current just before becoming reverse biased and the reverse recovery loss is minimized. The transformer size can be reduced using DCM because the average energy storage is low compared to CCM. However, DCM inherently causes high RMS current, which increases the conduction loss of the MOSFET severely for low line condition. Thus, especially for standby auxiliary power supply applications with low output voltage where Schottky diode without reverse recovery can be used; it is typical to design the converter such that the converter operates in CCM to maximize efficiency. It is typical to select the input capacitor as 2~3μF per watt of peak input power for universal input range (85-265VAC) and 1μF per watt of peak input power for European input range (195V-265VAC). With the input capacitor chosen, the minimum input capacitor voltage at nominal load condition is obtained as: VIN MIN = 2 ⋅ (VLINE MIN ) 2 − PIN ⋅ (1 − DCH ) CIN ⋅ f L (2) where DCH is the input capacitor charging duty ratio defined as shown in Figure 2, which is typically about 0.2. The maximum input capacitor voltage is given as: VIN MAX = 2VLINE MAX (3) In this section, a design procedure is presented using Figure 1 as a reference. An offline SMPS with 20W/5V nominal output power has been selected as a design example. [STEP-1] Define the System Specifications When designing a power supply with peak load current profile, the following specifications should be determined: `Line voltage range (VLINEMIN and VLINEMAX) Figure 2. Input Capacitor Voltage Waveform `Line frequency (fL) `Nominal output power (PO) (Design Example) By choosing 100μF capacitor for `Estimated efficiencies for nominal load (η): The power conversion efficiency must be estimated to calculate the input powers for nominal load condition. If no reference data is available, set η = 0.7~0.75 for low-voltage output applications and η = 0.8~0.85 for high-voltage output applications. input capacitor, the minimum input voltages for nominal load is obtained as: VIN MIN = 2 ⋅ (VLINE MIN ) 2 − With the estimated efficiency, the input power for peak load condition is given by: PIN = PO η = 2 ⋅ (90) 2 − 26 ⋅ (1 − 0.2) = 113V 100 × 10 −6 ⋅ 60 The maximum input voltage is obtained as: (1) VIN MAX = 2 ⋅ VLINE MAX = 2 ⋅ 264 = 373V (Design Example) The specifications of the target system are: • VLINEMIN =90VAC and VLINEMAX =264VAC • Line frequency fL = 60Hz (90VAC) and 50Hz (264VAC) • Nominal output power PO = 20W (5V/4A) • Estimated efficiency: η = 0.77 P 20 PIN = O = = 26W η 0.77 © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/18/09 PIN ⋅ (1 − DCH ) C IN ⋅ f L [STEP-3] Determine the Reflected Output Voltage (VRO) When the MOSFET is turned off, the input voltage (VIN), together with the output voltage reflected to the primary (VRO), are imposed across the MOSFET, as shown in 0. With a given VRO, the maximum duty cycle (DMAX), and the maximum nominal MOSFET voltage (VDSNOM) are obtained as: DMAX = VRO VRO + VIN MIN (4) www.fairchildsemi.com 2 AN-8024 APPLICATION NOTE VDS NOM = VIN MAX + VRO VDO NOM = VIN MAX ⋅ (VO + VF ) + VO VRO (5) Table 1. Diode Forward-Voltage Drop for Different Voltage Ratings (3A Schottky Diode) (6) Part Name SB320 SB330 SB340 SB350 SB360 SB380 SB3100 VRRM 20V 30V 40V 50V 60V 80V 100V VF 0.5V 0.74V 0.85V (Design Example) As can be seen in Table 1, it is necessary to use a rectifier diode with 40V voltage rating to maximize efficiency. Assuming that the nominal voltages of MOSFET and diode are less than 68% of their voltage rating, the reflected output voltage is given as: V MAX ⋅ (VO + VF ) VDO NOM = IN + VO VRO 373 ⋅ (5 + 0.5) + 5 < 0.68 ⋅ 40 = 27.2 VRO 373 ⋅ (5 + 0.5) ⇒ VRO > = 92.4V 22.2 VDS NOM = VIN MAX + VRO < 0.68 ⋅ 700 = 476 ⇒ VRO < 476 − 373 < 103V = By determining VRO as 100V, DMAX = VDS NOM = VIN MAX + VRO = 373 + 100 = 473V Figure 3. Output Voltage Reflected to the Primary VDO NOM = As can be seen in Equation (5), the voltage stress across MOSFET can be reduced by reducing VRO. This, however, increases the voltage stresses on the rectifier diodes in the secondary side, as shown in Equation (6). Therefore, VRO should be determined by a trade-off between the voltage stresses of MOSFET and diode. Especially for low output voltage application, the rectifier diode forward-voltage drop is a dominant factor determining the power supply efficiency. Therefore, the reflected output voltage should be determined such that rectifier diode forward voltage can be minimized. Table 1 shows the forward-voltage drops for Schottky diodes with different voltage ratings. = VIN MAX ⋅ (VO + VF ) + VO VRO 373 ⋅ (5 + 0.5) + 5 = 25.5V 100 [STEP-4] Determine the Transformer Primary-Side Inductance (LM) The transformer primary-side inductance is determined for the minimum input voltage and nominal load condition. With the DMAX from step 3, the primary-side inductance (LM) of the transformer is obtained as: LM = Because the actual drain voltage and diode voltage rise above the nominal voltage due to the leakage inductance of the transformer, as shown in 0, it is typical to set VRO such that VDSNOM and VDONOM are 60~70% of voltage ratings of MOSFET and diode, respectively. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/18/09 VRO VRO 100 = = 0.47 MIN 100 + 113 + VIN (VIN MIN ⋅ DMAX ) 2 2 P IN f SW K RF (7) where fSW is the switching frequency and KRF is the ripple factor at minimum input voltage and nominal load condition, defined as shown in Figure 4. The ripple factor is closely related with the transformer size and the RMS value of the MOSFET current. Even though the conduction loss in the MOSFET can be reduced by reducing the ripple factor, too small a ripple factor forces an increase in www.fairchildsemi.com 3 AN-8024 APPLICATION NOTE Table 2. transformer size. From a practical point of view, it is reasonable to set KRF = 0.3~0.6 for the universal input range and KRF = 0.4~0.8 for the European input range. ΔI 2 ΔI ⎤ D ⎡ I DS RMS = ⎢3( I EDC ) 2 + ( ) 2 ⎥ MAX 2 ⎦ 3 ⎣ PIN where I EDC = VIN MIN ⋅ DMAX ΔI = and K RF = VIN MIN DMAX LM f SW ILIM (8) FSBH0F70 FSBH0170 FSBH0270 FSBH0370 0.73A 0.80A 1.00A 1.20A (9) (Design Example) FSBH0370 is selected. 8W 13W 16W 19W [STEP-6] Determine the Minimum Primary Turns (10) With a given core, the minimum number of turns for the transformer primary side to avoid core saturation is given by: (11) N P min = ΔI 2 I EDC LM I LIM × 106 BSAT Ae (12) where Ae is the cross-sectional area of the core in mm2, ILIM is the pulse-by-pulse current limit level, and BSAT is the saturation flux density in Tesla. ΔI The pulse-by-pulse current limit level is included in Equation (12) because the inductor current reaches the pulse-by-pulse current limit level during the load transient or overload condition. Error! Reference source not found. shows the typical characteristics of ferrite core from TDK (PC40). Since the saturation flux density (BSAT) decreases as the temperature increases, the high temperature characteristics should be considered. If there is no reference data, use BMAX =0.3 T. I DS PK Figure 4. MOSFET Current and Ripple Factor (KRF) (Design Example) Determining the ripple factor as 0.6: LM = Maximum Output Power for Universal Input Range and Open Frame Product Once LM is calculated by determining KRF from Equation (7), the peak current and RMS current of the MOSFET for minimum input voltage and nominal load condition are obtained as: I DS PK = I EDC + Lineup of FSBH-Series with Power Ratings (VIN MIN ⋅ DMAX ) 2 (113 ⋅ 0.47) 2 = 2 P IN f SW K RF 2 ⋅ 26 ⋅ 100 × 103 ⋅ 0.6 = 900 μ H I EDC = ΔI = VIN PIN 26 = = 0.49 A ⋅ DMAX 113 ⋅ 0.47 MIN VIN MIN DMAX 113 ⋅ 0.47 = = 0.59 A LM f SW 900 × 10−6 ⋅ 100 × 103 I DS PK = I EDC + ΔI = 0.49 + 0.295 = 0.78 A 2 ΔI ⎤ D ⎡ I DS RMS = ⎢3( I EDC ) 2 + ( ) 2 ⎥ MAX 2 ⎦ 3 ⎣ 0.47 = ⎣⎡3(0.49) 2 + (0.295) 2 ⎤⎦ = 0.36 A 3 [STEP-5] Choose the Proper FPS, Considering Input Power and Peak Drain Current With the resulting maximum peak drain current of the MOSFET (IDSPK) from Equation (8), choose the proper FPS for which the pulse-by-pulse current limit level (ILIM) is higher than IDSPK. Since FPS has ±10% tolerance of ILIM, there should be some margin when choosing the proper FPS device. The FSBH-series lineup with power ratings is summarized in Table 2. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/18/09 Figure 5. Typical B-H Characteristics of Ferrite Core (TDK/PC40) www.fairchildsemi.com 4 AN-8024 APPLICATION NOTE (Design Example) Assuming the diode forward- (Design Example) EEL-19 core is selected, whose voltage drop is 0.5V, the turn ratio is obtained as: VRO 100 N n= P = = = 18.18 N S VO + VF 5 + 0.5 Then, determine the proper integer for NS, such that the resulting NP is larger than NPmin as: N S = 8, N P = n ⋅ N S = 146 > N P min Setting VDD* as 15V, the number of turns for the auxiliary winding is obtained as: V * + VFA 15 + 1.2 ⋅ NS = ⋅ 8 = 24 N A = DD 5 + 0.5 VO + VF 2 effective cross-sectional area is 25mm . Choosing the saturation flux density as 0.3 T, the minimum number of turns for the primary side is obtained as: L ⋅I N P min = M LIM × 106 BSAT Ae = 900 × 10 −6 ⋅ 1.2 × 106 = 144 0.3 ⋅ 25 [STEP-7] Determine the Number of Turns for Each Winding Figure 6 shows the simplified diagram of the transformer. First, calculate the turn ratio (n) between the primary side and the secondary side from the reflected output voltage, determined in step 3, as: VRO N n= P = N S VO + VF [STEP-8] Determine the Wire Diameter for Each Winding Based on the RMS Current of Winding The maximum RMS current of the secondary winding is obtained as: (13) I SEC RMS = n ⋅ I DS RMS where NP and NS are the number of turns for primary side and secondary side, respectively; VO is the output voltage; and VF is the diode (DO) forward-voltage drop. Then, determine the proper integer for NS, such that the resulting NP is larger than NPmin obtained from Equation (12). VDD* + VFA ⋅ N S1 VO + VF (15) The current density is typically 3~5A/mm2 when the wire is long (>1m). When the wire is short with a small number of turns, a current density of 5~10A/mm2 is also acceptable. Avoid using wire with a diameter larger than 1mm to avoid severe eddy current losses as well as to make winding easier. For high-current output, it is better to use parallel windings with multiple strands of thinner wire to minimize skin effect. The number of turns for the auxiliary winding for VDD supply is determined as: NA = 1 − DMAX DMAX (14) where VDD* is the nominal value of the supply voltage and VFA is the forward-voltage drop of DDD as defined in Figure 6. Since VDD increases as the output load increases, it is proper to set VDD at 3~5V higher than VDD UVLO level (8V) to avoid the over-voltage protection condition during the peak load operation. (Design Example) The RMS current of primary-side winding is obtained from step 4 as 0.36A. The RMS current of secondary-side winding is calculated as: I SEC RMS = n ⋅ I DS RMS 1 − DMAX DMAX 1 − 0.47 = 6.9 A 0.47 0.3mm (5A/mm2) and 0.65mm×2 (10A/mm2) diameter wires are selected for primary and secondary windings, respectively. = 18.18 ⋅ 0.36 [STEP-9] Choose the Rectifier Diode in the Secondary Side Based on the Voltage and Current Ratings The maximum reverse voltage and the RMS current of the rectifier diode are obtained as: VDO = VO + VIN MAX n I DO RMS = n ⋅ I DS RMS (16) 1 − DMAX DMAX (17) Figure 6. Simplified Transformer Diagram © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/18/09 www.fairchildsemi.com 5 AN-8024 APPLICATION NOTE Figure 7 shows the variation of a CCM flyback converter control-to-output transfer function for different input voltages. This figure shows the system poles and zeros together with the DC gain change for different input voltages. The gain is highest at the high input voltage condition and the RHP zero is lowest at the low input voltage condition. The typical voltage and current margins for the rectifier diode are: (18) VRRM > 1.3 ⋅ VDO I F > 1.5 ⋅ I DO RMS (19) where VRRM is the maximum reverse voltage and IF is the current rating of the diode. (Design Example) The diode voltage and current are calculated as: V MAX 373 VDO = VO + IN =5+ = 25.5V n 18.18 1 − DMAX I DO RMS = n ⋅ I DS RMS DMAX 1 − 0.47 = 6.9 A 0.47 Two 5A and 40V diodes in parallel are selected for the rectifier diode. = 18.18 ⋅ 0.36 Figure 7. [STEP-10] Feedback Circuit Configuration Since FSBH-series employs current-mode control, the feedback loop can be implemented with a one-pole and onezero compensation circuit. The current control factor of FPS, K is defined as: K= I LIM I = LIM VFB SAT 3.2 CC M Flyback Converter Control-to Output Transfer Function Variation for Different Input Voltages Figure 8 shows the variation of a CCM flyback converter control-to-output transfer function for different loads. This figure shows that the low frequency gain does not change for different loads and the RHP zero is lowest at the full load condition. (20) where ILIM is the pulse-by-pulse current limit and VFBSAT is the feedback saturation voltage. which is typically 3.2V. As described in step 4, it is typical to design the flyback converter to operate in CCM for heavy load condition. For CCM operation, the control-to-output transfer function of a flyback converter using current mode control is given by: Gvc = vˆo vˆFB K ⋅ RL ⋅ VIN ( N P / N S ) (1 + s / ω Z )(1 − s / ω RZ ) = ⋅ 2VRO + VIN (1 + s / ω P ) (21) where RL is the load resistance and the pole and zeros of Equation (21) are obtained as: ωZ = Figure 8. CCM Flyback Converter Control-to Output Transfer Function Variation for Different Loads RL (1 − D ) 2 1 (1 + D ) , ω RZ = and ω P = 2 RC CO DLM ( N S / N P ) RL CO When the input voltage and the load current vary over a wide range, it is not easy to determine the worst case for the feedback loop design. The gain, together with zeros and poles, vary according to the operating conditions. Moreover, even though the converter is designed to operate in CCM or at the boundary of DCM and CCM in the minimum input voltage and full load condition, the converter enters into DCM, where D is the duty cycle of the FPS and RC is the ESR of CO. Notice that there is a right half plane (RHP) zero (ωRZ) in the control-to-output transfer function of Equation (21). Because the RHP zero reduces the phase by 90 degrees, the crossover frequency should be placed below the RHP zero. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/18/09 www.fairchildsemi.com 6 AN-8024 APPLICATION NOTE changing the system transfer functions as the load current decreases and/or input voltage increases. The feedback compensation network transfer function of Figure 9 is obtained as: One simple and practical way to address this problem is designing the feedback loop for low input voltage and full load condition with enough phase and gain margin. When the converter operates in CCM, the RHP zero is lowest in low input voltage and full load condition. The gain increases only about 6dB as the operating condition is changed from the lowest input voltage to the highest input voltage condition under universal input condition. When the operating mode changes from CCM to DCM, the RHP zero disappears, making the system stable. Therefore, by designing the feedback loop with more than 45 degrees phase margin in low input voltage and full load condition, the stability over all the operating ranges can be guaranteed. vˆFB ω 1 + s / ω ZC =− I ⋅ vˆo s 1 + s / ω PC RFB 1 where ω I = , ω ZC = , and ( RF + R1 )C F R1 RD C F 1 . ω PC = RFB C FB and RFB is the equivalent feedback bias resistor of FSBHseries (5kΩ); and R1, RD, RF, CF and CFB are shown in Figure 10. (Design Example) Assuming CTR is 100%, VO − VOPD − VKA ⋅ CTR > 1 × 10 −3 RD Figure 9 is a typical feedback circuit mainly consisting of a shunt regulator and a photo-coupler. R1 and R2 form a voltage divider for output voltage regulation. RF and CF are adjusted for control-loop compensation. The maximum source current of the FB pin is about 1mA. The phototransistor must be capable of sinking this current to pull the FB level down at no load. The value of RD, is determined as: VO − VOPD − VKA ⋅ CTR > I FB RD (23) RD < VO − VOPD − VKA 5 − 1.2 − 2.5 = = 1.3k Ω 1× 10 −3 1× 10 −3 The minimum cathode current for KA431 is 1mA. RBIAS < VOPD = 1.2 k Ω 1× 10 −3 1kΩ resistor is selected for RBIAS. (22) The voltage divider resistors R1 and R2 for VO sensing are selected as 20kΩ and 20kΩ. where VOPD is the drop voltage of the photodiode, about 1.2V; VKA is the minimum cathode to anode voltage of KA431 (2.5V); and CTR is the current transfer rate of the opto-coupler. [STEP-11] Design Input Voltage Sensing Circuit Figure 10 shows a resistive voltage divider with low-pass filter for line-voltage detection of the VIN pin. The VIN voltage is used for brownout protection, which triggers when the VIN voltage drops below 0.6V. A 500ms debounce time is introduced for brownout protection to prevent false triggering by the voltage ripple on the input capacitor. FSBH-series devices start up when the VIN voltage reaches 1.1V. It is typical to use 100:1 voltage divider for VIN level. Figure 9. Feedback Circuit Figure 10. Input Voltage Sensing © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/18/09 www.fairchildsemi.com 7 AN-8024 APPLICATION NOTE Design Summary Figure 11 shows the final schematic of the 20W power supply of the design example. Figure 11. Final Schematic of Design Example © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/18/09 www.fairchildsemi.com 8 AN-8024 APPLICATION NOTE EEL-19 1 10 N 5V Np/2 2 6 Np/2 3 Na 4 5 Figure 12. Transformer Specification 2 Core: EEL-19 (Ae=25mm ) Bobbin: EEL-19 Pin (S → F) Wire Turns Winding Method 4→5 0.3φ×1 24 Solenoid Winding 73 Solenoid Winding 8 Solenoid Winding 73 Solenoid Winding Na Insulation: Polyester Tape t = 0.025mm, 1 Layer Np/2 3→2 0.3φ×1 Insulation: Polyester Tape t = 0.025mm, 2 Layers N5V 6 → 10 0.65φ×3 Insulation: Polyester Tape t = 0.025mm, 2 Layers Np/2 2→1 0.3φ×1 Insulation: Polyester Tape t = 0.025mm, 2 Layers Pin Specifications Remark Inductance 1－3 900μH ± 10% 100 kHz, 1 V Leakage 1－3 < 30 μH Max. Short All Other Pins © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/18/09 www.fairchildsemi.com 9 AN-8024 APPLICATION NOTE Related Datasheets FSBH0F70A, FSBH0170/A, FSBH0270/A, FSBH0370 — Green Mode Fairchild Power Switch (FPS™) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2009 Fairchild Semiconductor Corporation Rev. 1.0.1 • 9/18/09 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 10