www.fairchildsemi.com Application Note AN4134 Design Guidelines for Off-line Forward Converters Using Fairchild Power Switch (FPSTM) Abstract This paper presents practical design guidelines for off-line forward converter employing FPS (Fairchild Power Switch). Switched mode power supply (SMPS) design is inherently a time consuming job requiring many trade-offs and iteration with a large number of design variables. The step-by-step design procedure described in this paper helps the engineers to design a SMPS easily. In order to make the design process more efficient, a software design tool, FPS design assistant, that contains all the equations described in this paper, is also provided. Lp2 L2 DR2 + 2CDC Bridge rectifier diode Np Reset Circuit Non-doubled NS2 VO2 Cp2 CO2 DF2 VDC Doubled FPS 2CDC - Ra Vcc L1 Da GND Ca Rd Rbias 817A CB RL1 NTC VO1 Cp1 CO1 Na Line Filter CL1 NS1 DF1 CL2 FB Lp1 DR1 Drain R1 RF CF KA431 Fuse R2 AC line Figure 1. Basic Off-line Forward Converter Using FPS 1. Introduction transformer Due to circuit simplicity, the forward converter has been widely used for low to medium power conversion applications. Figure 1 shows the schematic of the basic offline forward converter using FPS, which also serves as the reference circuit for the design procedure described in this paper. Because the MOSFET and PWM controller together with various additional circuits are integrated into a single package, the design of SMPS is much easier than the discrete MOSFET and PWM controller solution. This paper provides step-by-step design procedure for an FPS based off-line forward converter, which includes design, reset circuit design, output filter design, component selection and closing the feedback loop. The design procedure described herein is general enough to be applied to various applications. The design procedure presented in this paper is also implemented in a software design tool (FPS design assistant) to enable the engineer to finish SMPS design in a short time. In the appendix, a step-by-step design example using the software tool is provided. Rev. 1.0.0 ©2003 Fairchild Semiconductor Corporation AN4134 APPLICATION NOTE 2. Step-by-step Design Procedure In this section, design procedure is presented using the schematic of the figure 1 as a reference. In general, most FPS has the same pin configuration from pin 1 to pin 4, as shown in figure 1. DC link voltage ripple DC link voltage (1) STEP-1 : Determine the system specifications (Vlinemin T1 Dch = T1 / T2 = 0.2 - 0.25 and Vlinemax) : - Line voltage range Usually, voltage doubler circuit as shown in figure 1 is used for a forward converter with universal input. Then, the minimum line voltage is twice the actual minimum line voltage. - Line frequency (fL). T2 Figure 2.DC Link Voltage Waveform (3) STEP-3 : Determine the transformer reset method and the maximum duty ratio (Dmax) - Maximum output power (Po). - Estimated efficiency (Eff) : It is required to estimate the power conversion efficiency to calculate the maximum input power. If no reference data is available, set Eff = 0.7~0.75 for low voltage output applications and Eff = 0.8~0.85 for high voltage output applications. With the estimated efficiency, the maximum input power is given by P P in = ------oE ff (1) Considering the maximum input power, choose the proper FPS. Since the voltage stress on the MOSFET is about twice the input voltage in the case of the forward converter, an FPS with 800V rated MOSFET is recommended for universal input voltage. The FPS lineup with proper power rating is also included in the software design tool. One inherent limitation of the forward converter is that the transformer must be reset during the MOSFET off period. Thus, additional reset schemes should be employed. Two most commonly used reset schemes are auxiliary winding reset and RCD reset. According to the reset schemes, the design procedure is changed a little bit. (a) Auxiliary winding reset : Figure 3 shows the basic circuit diagram of forward converter with auxiliary winding reset. This scheme is advantageous in respect of efficiency since the energy stored in the magnetizing inductor goes back to the input. However, the extra reset winding makes the construction of the transformer more complicated. L Nr Lm (2) STEP-2 : Determine DC link capacitor (CDC) and the DC link voltage range. VDC Vo Ns Np IM Dreset The maximum DC link voltage ripple is obtained as Ir + Vds Vgs - ∆ V DC max P in ⋅ ( 1 – D ch ) = -----------------------------------------------------------min 2V line ⋅ 2f L ⋅ C DC (2) Vgs where Dch is the DC link capacitor charging duty ratio defined as shown in figure 2, which is typically about 0.2. Vds It is typical to set ∆VDC as 10~15% of 2V line For voltage doubler circuit, two capacitors are used in series, each of which has capacitance twice of the capacitance that is determined by equation (2). VDC With the resulting maximum voltage ripple, the minimum and maximum DC link voltages are given as IM VDC min max ON min max V DC ON min = 2V line = 2V line – ∆ V DC max max VinNp/Nr IM- (3) (4) Np V DC Lm / C oss N r IM+ Ir T0 T1 T2 T3 T4 T5 Figure 3. Auxiliary Winding Reset Forward Converter 2 ©2002 Fairchild Semiconductor Corporation APPLICATION NOTE AN4134 The maximum voltage on MOSFET and the maximum duty ratio are given by V ds max = V DC N p 1 + -----N max The maximum voltage stress and the nominal snubber capacitor voltage are given by (5) V ds r Np D max ≤ -------------------Np + Nr As can be seen in equations (5) and (6), the maximum voltage on the MOSFET can be reduced by decreasing Dmax. However, decreasing Dmax results in increased voltage stress on the secondary side. Therefore, it is proper to set Dmax=0.45 and Np=Nr for universal input. For auxiliary winding reset, FPS, of which duty ratio is internally limited below 50%, is recommended to prevent core saturation during transient. (b) RCD reset : Figure 4 shows the basic circuit diagram of the forward converter with RCD reset. One disadvantage of this scheme is that the energy stored in the magnetizing inductor is dissipated in the RCD snubber, unlike in the reset winding method. However, due to its simplicity, this scheme is widely used for many cost-sensitive SMPS. Np Rsn VDC Dreset Vsn + Ns L Vo = V DC max (7) + V sn min V DC ⋅ D max V sn > ---------------------------------------( 1 – D max ) (6) where Np and Nr are the number of turns for the primary winding and reset winding, respectively. max (8) Since the snubber capacitor voltage is fixed and almost independent of the input voltage, the MOSFET voltage stress can be reduced compared to the reset winding approach when the converter is operated with a wide input voltage range. Another advantage of RCD reset method is that it is possible to set the maximum duty ratio larger than 50% with relatively low voltage stress on the MOSFET compared to auxiliary winding reset method, which results in reduced voltage stress on the secondary side. (4) STEP-4 : Determine the ripple factor of the output inductor current. Figure 5 shows the current of the output inductor. The ripple factor is defined as ∆ IK RF = ------2I o (9) where Io is the maximum output current. For most practical design, it is reasonable to set KRF=0.1~ 0.2. Lm Isn Vgs ∆I IM Io + Vds K RF = ∆I 2 Io Ts - DTs Vgs ON Figure 5. Output Inductor Current and Ripple Factor ON Vds Once the ripple factor is determined, the peak current and rms current of MOSFET are obtained as Vsn VDC I ds Vsn IM IM+ Lm / Coss rms where IMIsn T0 I ds peak T1 T2 T3 T4 T5 = I EDC ( 1 + KRF ) 2 D max = I EDC ( 3 + K RF ) ------------3 P in I EDC = ------------------------------------min V DC ⋅ D max (10) (11) (12) Check if the MOSFET maximum peak current (Idspeak) is below the pulse-by-pulse current limit level of the FPS (Ilim). Figure 4. RCD Reset Forward Converter ©2002 Fairchild Semiconductor Corporation 3 AN4134 APPLICATION NOTE (5) STEP-5 : Determine the proper core and the minimum primary turns for the transformer to prevent core saturation. Actually, the initial selection of the core is bound to be crude since there are too many variables. One way to select the proper core is to refer to the manufacture's core selection guide. If there is no proper reference, use the following equation as a starting point. Ap = Aw Ae 11.1 × P in = ------------------------------------0.141 ⋅ ∆B ⋅ f s 1.31 4 4 × 10 ( mm ) ( 13 ) where Aw is the window area and Ae is the cross sectional area of the core in mm2 as shown in figure 6. fs is the switching frequency and ∆B is the maximum flux density swing in tesla for normal operation. ∆B is typically 0.2-0.3 T for most power ferrite cores in the case of a forward converter. Notice that the maximum flux density swing is small compared to flyback converter due to the remnant flux density. min ⋅ D max V DC N n = -------p- = ------------------------------------N sI V o1 + VF1 (15) where Np and Ns1 are the number of turns for primary side and reference output, respectively. Vo1 is the output voltage and VF1 is the diode forward voltage drop of the reference output. Then, determine the proper integer numbers for Ns1 so that the resulting Np is larger than Npmin obtained from equation (14). The magnetizing inductance of the primary side is given by 2 L m = A L × N p × 10 –9 (H) (16) where AL is the AL-value with no gap in nH/turns2. The numer of turns for the n-th output is determined as Vo (n ) + VF (n ) N s ( n ) = ---------------------------------- ⋅ N s1 V o1 + V F1 (turns) (17) where Vo(n) is the output voltage and VF(n) is the diode forward voltage drop of the n-th output. Aw The next step is to determine the number of turns for Vcc winding. The number of turns for Vcc winding is determined differently according to the reset method. (a) Auxiliary winding reset : For auxiliary winding reset, the number of turns of the Vcc winding is obtained as V cc * + V Fa - ⋅ N r (turns) N a = --------------------------min V DC where Vcc* is the nominal voltage for Vcc and VFa is the diode forward voltage drop. Since Vcc is proportional to the input voltage when auxiliary winding reset is used, it is proper to set Vcc* as the Vcc start voltage to avoid the over voltage protection during the normal operation. Ae Figure 6. Window Area and Cross Sectional Area With a determined core, the minimum number of turns for the transformer primary side to avoid saturation is given by min Np min V DC ⋅ D max 6 = -------------------------------------- × 10 Ae ⋅ fs ⋅ ∆ B ( turns ) (18) ( 14 ) (b) RCD reset : For RCD reset, the number of turns of the Vcc winding is obtained as Vcc * + V Fa N a = ---------------------------- ⋅ N p (turns) V sn (19) where Vcc* is the nominal voltage for Vcc. Since Vcc is almost constant for RCD reset in normal operation, it is proper to set Vcc* to be 2-3 V higher than Vcc start voltage. (7) STEP-7 : Determine the wire diameter for each transformer winding based on the rms current. The rms current of the n-th winding is obtained as (6) STEP-6 : Determine the number of turns for each inding of the transformer First, determine the turns ratio between the primary side and the feedback controlled secondary side as a reference. 4 I sec ( n ) rms 2 D max = Io ( n ) ( 3 + K RF ) ------------3 (20) where Io(n) is the maximum current of n-th output. ©2002 Fairchild Semiconductor Corporation APPLICATION NOTE AN4134 When the auxiliary winding reset is employed, the rms current of the reset winding is as follows. Then, calculate the inductance of the reference output inductor as V o1 ( Vo1 + V F1 ) - ( 1 – D min ) L 1 = ---------------------------------------2 ⋅ f s ⋅ KRF ⋅ P o min I Reset rms V DC D max D max = ----------------------------------------------------Lm f s 3 (21) (24) min 2 The current density is typically 5A/mm when the wire is long (>1m). When the wire is short with small number of turns, current density of 6-10 A/mm2 is also acceptable. Avoid using wire with a diameter larger than 1 mm to avoid severe eddy current losses and to make winding easier. For high current output, it is better to use parallel winding with multiple strands of thinner wire to minimize skin effect. Check if the winding window area of the core is enough to accommodate the wires. The required window area is given by Aw = A c ⁄ K F (22) where Ac is the actual conductor area and KF is the fill factor. Typically the fill factor is 0.2-0.3 when a bobbin is used. (8) STEP-8 : Determine the proper core and the number of turns for output inductor When the forward converter has more than one output as shown in figure 7, coupled inductors are usually employed to improve the cross regulation, which are implemented by winding their separate coils on a single, common core. where N L1 min L 1 P O ( 1 + K RF ) 6 = ---------------------------------------- × 10 VO1 B sat A e Np NS2 VO2 DF2 DR1 CO2 NL1 CO1 VO1 Figure 7. Coupled Output Inductors (9) STEP-9 : Determine the wire diameter for each inductor winding based on the rms current. The rms current of the n-th inductor winding is obtained as 2 ©2002 Fairchild Semiconductor Corporation rms ( 3 + K RF ) = I o ( n ) --------------------------3 (27) The current density is typically 5A/mm2 when the wire is long (>1m). When the wire is short with small number of turns, a current density of 6-10 A/mm2 is also acceptable. Avoid using wire with diameter larger than 1 mm to avoid severe eddy current losses and to make winding easier. For high current output, it is better to use parallel winding with multiple strands of thinner wire to minimize skin effect. The maximum voltage and the rms current of the rectifier diode of the n-th output are obtained as V D ( n ) = VDC First, determine the turns ratio of the n-th winding to the reference winding (the first winding) of the coupled inductor. The turns ratio should be the same with the transformer turns ratio of the two outputs as follows. NL (n ) Ns ( n ) ------------- = ------------N s1 N L1 ( 26 ) (10) STEP-10 : Determine the diode in the secondary side based on the voltage and current ratings. L1 NS1 DF1 ( turns ) where Ilim is the FPS current limit level, Ae is the cross sectional area of the core in mm2 and Bsat is the saturation flux density in tesla. If there is no reference data, use Bsat =0.35-0.4 T. Once NL1 is determined, NL(n) is determined by equation (23). L2 NL2 (25) The minimum number of turns for L1 to avoid saturation is given by IL( n) DR2 D min V DC = D max ⋅ -------------------max VDC (23) ID ( n) rms max N s ( n ) ------------NP 2 D max = I o ( n ) ( 3 + K RF ) ------------3 (28) (29) (11) STEP-11 : Determine the output capacitor considering the voltage and current ripple. The ripple current of the n-th output capacitor is obtained as 5 AN4134 APPLICATION NOTE IC ( n) K RF Io ( n ) = --------------------3 rms (30) The ripple current should be equal to or smaller than the ripple current specification of the capacitor. the ouput capacitance of the MOSFET. Based on the power loss, the snubber resistor with proper rated wattage should be chosen. The ripple of the snubber capacitor voltage in normal operation is obtained as The voltage ripple on the n-th output is given by Io ( n ) ⋅ K RF ∆ V o ( n ) = ------------------------- + 2KRF I o ( n ) R c ( n ) 4C o ( n ) fs V D C sn R sn f s sn max ∆ V sn = ----------------------- (31) (37) In general, 5-10% ripple is practically reasonable. Vds where Co(n) is the capacitance and Rc(n) is the effective series resistance (ESR) of the n-th output capacitor. Sometimes it is impossible to meet the ripple specification with a single output capacitor due to the high ESR of the electrolytic capacitor. Then, additional LC filter (post filter) can be used. When using additional LC filter, be careful not to place the corner frequency too low. If the corner frequency is too low, it may make the system unstable or limit the control bandwidth. It is proper to set the corner frequency of the filter to be around 1/10 to 1/5 of the switching frequency. V sn V DC Vsn ∆ Vsn T1 T0 (12) STEP-12 : Design the Reset circuit. Figure 8. Snubber Capacitor Voltage (a) Auxiliary winding reset : For auxiliary winding reset, the maximum voltage and rms current of the reset diode are given by V Dreset = V DC Nr 1 + -----N max (32) rms V DC Dmax D max - -------------= --------------------------------Lm f s 3 ( 33 ) V DR = V DC + V sn vo1' FPS vFB (b) RCD reset : For RCD reset, the maximum voltage and rms current of the reset diode are given by max (13) STEP-13 : Design the feed back loop. Since FPS employs current mode control as shown in figure 9, the feedback loop can be simply implemented with a one pole and one zero compensation circuit. p min IDreset T2 T3 T4 (34) CB RD ibias Lp1 Rbias iD 1:1 vo1 B CF RF R1 431 min I DR rms V DC D max D max = --------------------------------- -------------L m fs 3 (35) The power loss of the snubber network in normal operation is obtained as 2 Loss sn m ( 36 ) Figure 9. Control Block Diagram oss where Vsn is the snubber capacitor voltage in normal operation, Rsn is the snubber resistor, n is Np/Ns1 and Coss is 6 Ipk MOSFET current 2 V sn 2nVo1 V sn 1 ( nV o1 ) - = --- -------------------- – --------------------------= ----------R sn 2 L m fs L ⁄C R2 For continuous conduction mode (CCM) operation, the control-to-output transfer function of forward converter using FPS is given by ©2002 Fairchild Semiconductor Corporation APPLICATION NOTE AN4134 ˆ N p 1 + s ⁄ wz ν o1 G vc = -------- = K ⋅ R L ⋅ --------- ⋅ -----------------------ˆ N s1 1 + s ⁄ w p ν (c) Place compensator zero (fzc) around fc/3. (d) Place compensator pole (fpc) above 3fc . ( 38 ) FB where 1 w z = -------------------- , Rc1 C o1 1 w p = ----------------R L C o1 and RL is the effective total load resistance of the controlled output defined as Vo12/Po.When the converter has more than one output, the DC and low frequency control-to-output transfer function are proportional to the parallel combination of all load resistance, adjusted by the square of the turns ratio. Therefore, the effective total load resistance is used in equation (38) instead of the actual load resistance of Vo1. The voltage-to-current conversion ratio of FPS, K is defined as I pk I lim K = --------- = ------V FB 3 40 dB 20 dB 0 dB fp Light load fp Heavy load fz -20 dB -40 dB 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz Figure 10. CCM Forward Converter Control-to-output Transfer Function variation According to the Load (39) Loog gain T 40 dB where Ipk is the peak drain current and VFB is the feedback voltage for a given operating condition. Figure 10 shows the variation of control-to-output transfer function for a CCM forward converter according to the load. Since a CCM forward converter has inherent good line regulation, the transfer function is independent of input voltage variation. While the system pole together with the DC gain changes according to the load condition. The feedback compensation network transfer function of figure 9 is obtained as w 1 + s ⁄ wzc -----i --------------------------------ˆν - = - s ⋅ 1 + 1 ⁄ w pc o1 νˆ FB fzc 20 dB fpc fp Compensator wi/wzc 0 dB Control to output fc -20 dB fz -40 dB 1Hz 10Hz 100Hz 1kHz 10kHz 100kHz Figure 11. Compensator Design (40) RB 1 1 -,w = ---------------------------------,w = --------------where wi = ------------------------R 1 R D CF s zc ( RF + R 1 )C F pc R B C B As can be seen in figure 10, the worst case in designing the feedback loop for a CCM forward converter is the full load condition. Therefore, by designing the feedback loop with proper phase and gain margin in low line and full load condition, the stability all over the operation ranges can be guaranteed. The procedure to design the feedback loop is as follows: (a) Determine the crossover frequency (fc). When an additional LC filter (post filter) is employed, the crossover frequency should be placed below 1/3 of the corner frequency of the post filter, since it introduces -180 degrees phase drop. Never place the crossover frequency beyond the corner frequency of the post filter. If the crossover frequency is too close to the corner frequency, the controller should be designed to have enough phase margin more than about 90 degrees when ignoring the effect of the post filter. When determining the feedback circuit component, there are some restrictions as follows. (a) The capacitor connected to feedback pin (CB) is related to the shutdown delay time in an overload situation as T delay = ( VSD – 3 ) ⋅ C B ⁄ I delay (41) where VSD is the shutdown feedback voltage and Idelay is the shutdown delay current. These values are given in the data sheet. In general, 10~100 ms delay time is proper for most practical applications. In some cases, the bandwidth may be limited due to the required delay time in over load protection. (b) The resistor Rbias and RD used together with opto-coupler and the KA431 should be designed to provide proper operating current for the KA431 and to guarantee the full swing of the feedback voltage of the FPS. In general, the minimum cathode voltage and current for KA431 is 2.5V and 1mA, respectively. Therefore, Rbias and RD should be designed to satisfy the following conditions. (b) Determine the DC gain of the compensator (wi/wzc) to cancel the control-to-output gain at fc. ©2003 Fairchild Semiconductor Corporation 7 AN4134 APPLICATION NOTE V o – V OP – 2.5 -------------------------------------- > I FB RD (42) V OP ------------- > 1mA R bias (43) where VOP is opto-diode forward voltage drop, which is typically 1V and IFB is the feedback current of FPS, which is typically 1mA. For example, Rbias<1kΩ and RD <1.5kΩ for Vo1=5V. ©2003 Fairchild Semiconductor Corporation 8 APPLICATION NOTE AN4134 - Summary of symbols Aw Ae Bsat ∆B Co Dmax Eff fL fs Idspeak Idsrms Ilim Isec(n)rms ID(n)rms Ic(n)rms IO KL(n) KRF Lm Losssn Npmin Np Nr Ns1 Po Pin Rc Rsn RL Vlinemin Vlinemax VDCmin VDCmax Vdsnom Vo1 VF1* Vcc* VFa ∆VDCmax VD(n) ∆Vo(n) Vsn ∆Vsn Vsnmax Vdsmax : Window area of the core in mm2 : Cross sectional area of the core in mm2 : Saturation flux density in tesla. : Maximum flux density swing in tesla in normal operation : Capacitance of the output capacitor. : Maximum duty cycle ratio : Estimated efficiency : Line frequency : Switching frequency : Maximum peak current of MOSFET : RMS current of MOSFET : FPS current limit level. : RMS current of the n-th secondary winding : Maximum rms current of the rectifier diode for the n-th output : RMS Ripple current of the n-th output capacitor : Output load current : Load occupying factor for n-th output : Current ripple factor : Transformer primary side inductance : Power loss of the snubber network in normal operation : The minimum number of turns for the transformer primary side to avoid saturation : Number of turns for primary side : Number of turns for reset winding : Number of turns for the reference output : Maximum output power : Maximum input power : Effective series resistance (ESR) of the output capacitor. : Snubber resistor : Output load resistor : Minimum line voltage : Maximum line voltage : Minimum DC link voltage : Maximum DC line voltage : Maximum nominal MOSFET voltage : Output voltage of the reference output. : Diode forward voltage drop of the reference output. : Nominal voltage for Vcc : Diode forward voltage drop of Vcc winding : Maximum DC link voltage ripple : Maximum voltage of the rectifier diode for the n-th output : Output voltage ripple of the n-th output : Snubber capacitor voltage in normal operation : Snubber capacitor voltage ripple : Maximum snubber capacitor voltage during transient or over load situation : Maximum voltage stress of MOSFET ©2002 Fairchild Semiconductor Corporation 9 AN4134 APPLICATION NOTE Appendix. Design Example using FPS design Assistant Target System : PC Power Supply - Input : universal input (90V-265Vrms) with voltage doubler - Output : 5V/15A, 3.3V/10A, 12V/6A FPS Design Assistant ver.1.0 By Choi For forward converter with reset winding Blue cell is the input parameters Red cell is the output parameters 1. Defin e specifications of the SMPS Minimum Line voltage (V_line.min) Maximum Line voltage (V_line.max) Line frequency (fL) 180 V.rms 265 V.rms 60 Hz Vo 1st output for feedback 2nd output 3rd output 4th output Maximum output power (Po) = Estimated efficiency (Eff) Maximum input power (Pin) = 5 3.3 12 0 180.0 70 257.1 V V V V W % W Io 15 10 6 0 Po A A A A KL 75 33 72 0 W W W W 42 18 40 0 % % % % 2. Determin e DC link capacitor and the DC voltage range DC link capacitor 235 uF 29 V DC link voltage ripple = Minimum DC link voltage = 226 V Maximum DC link voltage = 375 V 3. Determin e the maximum duty ratio (Dmax) Maximum duty ratio Turns ratio (Np/Nr) Maximum nominal MOSFET voltage = 0.4 1 > 750 V 0.67 4. Determin e the ripple factor of the output inductor current Output Inductor current ripple factor 0.15 3.27 A Maximum peak drain c urren t = RMS drain current = 1.81 A Current limit of FPS 4 A ∆I Io KRF = ∆I 2I o Ts DT s 5. Determin e proper core and minimum primary turns for transformer Switching frequency of FPS (kHz) 67 kHz Maximum flux density swing 0.32 T --> EER2834 4 AP=12470 Estimated AP value of core = 9275 mm 2 Cross sectional area of core (Ae) 86 mm Ae=86 Minimum primary turns = 49.0 T Aw=145 ©2003 Fairchild Semiconductor Corporation 10 APPLICATION NOTE AN4134 6. Determine the numner of turns for each outputs Vo Vcc (Use Vcc start voltage) 1st output for feedback 2nd output 3rd output 4th output VF : Forward voltage drop of rectifier diode AL value (no gap) Transformer magnetizing inductance = 15 5 3.3 12 0 VF # of turns 1.2 V 3.6 => 4 T 0.4 V 3 => 3 T 0.4 V 2.06 => 2 T 0.5 V 6.94 => 7 T 0 V 0 => 0 T Reset winding = 50 T Primary turns = 50 T ->enough turns V V V V V 2490 nH/T2 6.27499 mH --> EER2834 7. Determine the wire diameter for each transformer winding Primary winding (Np) Reset windin g (Nr) Vcc winding 1st output winding 2nd output winding 3rd output winding 4th output winding Copper area = Fill factor Required window area Diameter 0.68 0.31 0.31 0.68 0.68 0.68 0 33.9262 0.25 135.705 mm mm mm mm mm mm mm 2 mm Parallel 1 T 1 T 1 T 4 T 3 T 2 T 0 T Irms 1.81 0.08 0.10 9.5 6.3 3.8 0.0 A A A A A A A (A/mm 2) 4.98 1.04 1.33 6.56 5.83 5.25 #DIV/0! 2 mm --> EER2834 (Aw=145) 8. Determine proper core and number of turns for inductor (coupled inductor) 86 mm2 --> EER2834 Cross sectional area of Inductor core (A Saturation flux density 0.42 T Inductance of 1st output (L1) = 5.7 uH Minimum turns of L1 = 6.5 T Actual number of turns for L1 6 => 6 T 4 => 4 T Number of turns for L2 = 14 => 14 T Number of turns for L3 = 0 => 0 T Number of turns for L4 = 9. Determine the wire diameter for each inductor winding Winding for L1 Winding for L2 Winding for L3 Winding for L4 Copper area = Fill factor Required window area Diameter 0.68 0.68 0.68 0 25.4089 0.25 101.636 mm mm mm mm mm2 Parallel 5 T 3 T 2 T 0 T Irms 15.1 10.0 6.0 0.0 2 A A A A (A/mm ) 8.30 9.22 8.30 #DIV/0! mm2 --> EER2834(Aw=145) 10. Determine the rectifier diodes in the secondary side Vcc diode 1st output diode 2nd output diode 3rd output diode 4th output diode ©2002 Fairchild Semiconductor Corporation Reverse voltage 55 V 22 V 15 V 52 V 0 V Rms Current 0.10 A -->UF4003 9.5 A -->MBR3060PT 6.3 A -->MBR3045PT 3.81 A -->MBR20H100CT 0.00 A 11 AN4134 APPLICATION NOTE 11. Determine the output capacitor Capacitance 1st output capacitor 2nd output capacitor 3rd output capacitor 4th output capacitor 4400 4400 2000 0 12. Design the Reset Circuit Reset diode rms current Maximum voltage of reset diode ESR uF uF uF uF 0.08 A 750 V 20 20 60 0 Current Voltage ripple Ripple mΩ 1.3 V 0.09 V mΩ 0.9 V 0.06 V mΩ 0.5 V 0.11 V mΩ 0.0 V #### V -->UF4007 13. Design Feedback control loop Contr ol-to-output DC gain = Contr ol-to-output zero = Contr ol-to-output pole = 3 1,809 Hz 261 Hz FPS vo ' vFB Voltage divider resistor (R1) Voltage divider resistor (R2) Opto coupler diode resistor (RD ) 431 Bias resistor (Rbias) Feeback pin capacitor (CB) = Feedback Capacitor (CF) = Feedback resistor (RF) = Feedback integrator gain (fi) = Feedback zero (fz) = Feedback pole (fp) = 60 Gain (dB) 40 20 0 10 100 -20 -40 0 10 Phase (degree) -30 -60 100 5 5 1 1.2 10 100 1 ㏀ ㏀ ㏀ ㏀ nF nF ㏀ CB RD ibias R bia s iD 1: 1 vo B CF R1 RF 431 R2 955 Hz 265.393 Hz 5307.86 Hz 16 25 40 63 100 160 250 400 630 1000 1600 2500 4000 6300 10000 16000 25000 40000 63000 100000 9.80783 36 45 16 Contorl-to-output 9.78487 32 Compensator 41 25 9.7248 28 T37 40 9.58236 24 33 63 9.24037 20 29 100 8.46816 17 25 160 7.07174 14 21 250 1000 4.77208 13 10000 17 400 1.96652 12 14 630 -0.9856 11 10 1000 -3.5451 11 7.3 1600 -5.2263 10 5.1 2500 -6.2187 9.2 3 4000 -6.6721 7.3 0.6 6300 1000 -6.8719 4.5 10000 -2 #### -6.9549 1.1 -6 #### -6.9867 -3 -10 #### -7.0002 -6 -13 #### -7.0054 -10 -17 #### -7.0075 -14 -21 #### # -86.7 # -84.9 # -81.9 # -77.3 # -70.4 # -60.6 # -49.4 # 100000 -37.8 # -29.6 # -25.5 # -26.2 # -31.3 # -40.8 # -52.3 # 100000 -63.5 # -72.6 # -78.6 # -82.8 # -85.4 # -87.1 # # # # # # # # # # # # # # # # # # # # -90 -120 ©2003 Fairchild Semiconductor Corporation 12 APPLICATION NOTE AN4134 Design Summary • For the FPS, FS7M0880 is chosen. This device has a fixed switching frequency of 67kHz. • To limit the current, a 10 ohm resistor (Ra) is used in series with the Vcc diode. • The control bandwidth is 6kHz. Since the crossover frequency is too close the corner frequency of the post filter (additional LC filter), the controller is designed to have enough phase margin of 120 degrees when ignoring the effect of the post filter. Figure 12 shows the final schematic of the forward converter designed by FPS Design Assistant MBR120H100CT UF4007 L3 DR3 NS2 DReset V O3 12V CO3 DF3 1000uF ×2 Nr L2 MBR3045PT 470uF 2CDC GBU606 + Np N on-doubled DR2 NS2 Rstart DF2 Doubled FS7M0880 MBR3060PT 2CDC S/S CL2 100nF R a 10 D a Vcc UF4003 FB Css 1uF GND Ca D NS1 R1 3.3V 1000uF Lp1 1.2uH Drain 470uF VO2 C p2 CO2 2200uF× 2 560k V DC L p2 1.2uH L1 DF1 V O1 C p1 CO1 5V 470uF 2200uF ×2 Na 22uF 1k Rd Line Filter Rbias 1.2k CL1 100nF CB 817A 5k R1 10nF 1k 100nF R L1 RF 1M NTC CF KA431 Fuse 5k R2 AC line Figure 12. The final schematic of the forward converter KA1M0280RB,KA1M0380RB,KA1L0380RB,KA1H0680B,KA1M0680B,KA1H0680RFB,KA1M0680RB,KA1M0880B,KA1M0 880BF,KA1M0880D,KA5H0280R,KA5M0280R,KA5H0380R,KA5M0380R,KA5L0380R,KA5P0680C,FS7M0680,FS7M0880 ©2003 Fairchild Semiconductor Corporation 13 AN4134 APPLICATION NOTE by Hang-Seok Choi / Ph. D FPS Application Group / Fairchild Semiconductor Phone : +82-32-680-1383 Facsimile : +82-32-680-1317 E-mail : [email protected] DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPROATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 3/24/04 0.0m 002 2003 Fairchild Semiconductor Corporation

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