www.fairchildsemi.com AN-8209 Design Guideline for Quick Charger Using FAN6100M/FAN6100Q/FAN6100HM Introduction Over the last decade, power consumption in mobile electronic devices such as smart-phones and tablets has increased significantly because of bigger screens and high performance processors. As a result, the batteries used in these devices have become larger and more energy is required to charge them. Conventionally, these devices have been charged with a 5 V power supply whose maximum current capability is limited by the cable to 2 A. This restricts the amount of power that can be delivered, making the charging extremely time-consuming. If the power supply is operated at a higher voltage, more power can be delivered even though the current is limited. Hence, several Quick Charge protocols have been developed to charge the devices at higher voltages (7 V-12 V), which allow higher power output even with a conventional USB cable. A High-Voltage Dedicated Charging Port (HVDCP) power supply is an AC/DC power supply with a micro USB captive cable or USB Type A receptacle that has the ability to adjust the output according to a request made by the device. The HVDCP power supply produces the requested higher voltage while maintaining compatibility with USB Battery Charging 1.2 (USB BC 1.2) and communication protocols. The FAN6100x is a highly integrated secondary-side controller for adaptive voltage power adaptor to support fast charging protocols. FAN6100 is available in 2 versions for the following fast-charging protocols. FAN6100M/FAN6100HM compatible with MediaTek Pump ExpressTM Plus fast-charging and Fairchild’s FCP-Single communication protocol. FAN6100Q - compatible with Qualcomm’s Quick Charge 2.0 technology solution. © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 The FAN6100x allows the change of output voltage of a power supply when it detects that the device charger is requesting a higher voltage compatible to its supporting protocol. If a smart phone and tablet supports only 5 V, the controller disables adaptive output voltage to ensure safe operation at 5 V. The FAN6100x consists of two transistors in an open drain configuration for Constant Voltage (CV) and Constant Current (CC) regulation with adjustable references voltage. Outputs of the CV and CC amplifiers are tied together in open drain configuration to select the dominant signal. FAN6100x also incorporates an internal charge pump circuit to maintain CC regulation down to output voltage of 2 V without any external voltage supply to the IC. Programmable cable voltage drop compensation allows precise CV regulation at end of USB cable by adjusting one external resistor. To ensure a safe transition from high to low output voltage, a “bleeder” function is activated during mode change. Furthermore, several protection functions are incorporated in FAN6100x which include adaptive OverVoltage Protection (VOUT OVP) and adaptive UnderVoltage Protection (VOUT UVP). Hence, FAN6100x is an advanced secondary side controller for charging next generation devices in a swift and secure manner. This application note presents step-by-step design considerations for 15 W adaptive power adapter using the FAN6100M and FAN501AMPX; the typical application circuit is shown in Figure 1. It includes selecting the components for power stage and feedback loop design for implementing CC/CV control. www.fairchildsemi.com AN-8209 APPLICATION NOTE VO D+ D- AC IN GND 8 7 U1 FAN501A 6 4 5 10 1 9 2 11 10 9 2 1 3 3 12 18 13 U2 FAN6100M 19 15 17 14 16 6 5 Figure 1. 4 8 20 7 Typical Application Circuit 2. Operation Principle Np:Ns Lm CO1 + VO - CO2 RCS_SEC RL Gate S Q OSC R Q CSN RLED CLED Drv CSP CF1 RF1 IDS AV-CCR CS IREF RCS_PRI MOSCC SIGCV CFV1 RFV1 - + - Av VREF SFB RFB CFV2 IMOS VCCR Rbias + Slope Compensation 1/3 RFC1 CFC1 + SIGCC VSAW VEA.V MOSCV VCVR FB RF2 CFB COPT Figure 2. Internal PWM Control Circuit 2.1 Constant-Voltage Regulation Operation 2.2 Constant-Current Regulation Operation Figure 2 shows the primary-side internal PWM control circuit of the FAN501AMPX and the secondary-side regulator circuit of the FAN6100M which consists of two MOSFETs in an open-drain configuration for Constant Voltage (CV) and Constant Current (CC) regulation. The constant current (CC) regulation is implemented by sensing the output current via the secondary current-sense resistor (RCS_SEC) connected between the CSP and CSN pins, placed on the output ground return path. The sensed signal is amplified with a gain of 10 by internal amplifier AV-CCR, which is compared with the internal reference voltage for constant current regulation (VCCR). This generates the CC compensation signal (SIGCC) which becomes the gate signal of the CC MOSFET (MOSCC). The constant current point (IO_CC) can be set by selecting the current sensing resistor as: For constant voltage (CV) regulation, the output voltage (VOUT) is sensed on the VREF pin via the resistor divider (RF1 and RF2) and compared with the internal reference voltage for CV regulation VCVR. This generates a CV compensation signal (SIGCV) which becomes the gate signal for the CV MOSFET (MOSCV). The VOUT can be derived by setting RF1 and RF2, as calculated by: R RF 2 VO VCVR F 1 RF 2 © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 I O _ CC (1) 1 AV CCR VCCR RCS (2) www.fairchildsemi.com 2 AN-8209 APPLICATION NOTE During CV Mode, SIGCV is high and MOSCV stays in an active state, pulling current to drive SFB low. At this time, SIGCC is low which keeps MOSCC in an inactive state and has no impact on SFB. During CC Mode, SIGCC is high and MOSCC stays in an active state, pulling current to drive SFB low. At this time, SIGCV is low and MOSCV stays in an inactive state. SFB is transferred to the primary-side PWM controller using an opto-coupler and attenuated by AV to generate VEA. VEA wide VOUT operation range from 16 V to 2 V to meet different output requirement of various electronic devices. FAN6100x is an optimal solution for several quick charge protocols. For Qualcomm’s Quick Charge 2.0 technology solution, it generates a VOUT of 5 V at the beginning, and then 9 V or 12 V to meet class A requirement of HVDCP power supply. For Fairchild’s FCP-Single communication protocol, it produces a VOUT of 5 V at the beginning, and then changes VOUT to 7 V, 9 V or 12 V. For MediaTek Pump ExpressTM Plus fast-charging, it produces a VOUT of 5 V at the beginning, and then 7 V, 9 V or 12 V to meet requirements of a High-Voltage Dedicated Charging Port (HVDCP) power supply. In order to maximize the charging current, it can also attain lower voltages or 4.8 V/4.6 V/4.4 V/4.2 V/4 V. VSAW VCS Vslope Gate Another important thing to consider is the constant current mode selection set by QP and QN pins. FAN6100x provides flexible CC output choice for variety of power rating design. The constant output current mode selection specifications of FAN6100M and FAN6100Q are as follows: Pri FB SFB SIGCV SIGCC Table 1. Mode Descriptions and Settings of FAN6100M and FAN6100Q OSC CLK CV Regulation Figure 3. CC Regulation PWM Operation for CV and CC While the primary MOSFET is turned on, the current IDS through transformer magnetizing inductance rises. VCS is the rising current signal through RCS-PRI. This is added to slope compensation signal, Vslope to generate VSAW. VEA is compared to VSAW to determine the duty cycle. As seen in, Figure 2 output of comparator is used as a reset signal of flip-flop to determine the MOSFET turn-off instant. Fixed 1.5 A CC Mode QP=0 and QN=1 Fixed 2.0 A CC Mode QP=1 and QN=0 Table 2. Variable CC Mode Specifications Output Voltage(V) Rated Current (A) 5.0 2.0 7.0 1.8 9.0 1.67 12.0 1.25 For Fixed 1.5 A CC mode setting, output current is fixed at 1.5 A except 12 V mode as shown in Table 3. Table 3. Fixed 1.5 A CC Mode Specifications Output Voltage (V) Rated Current (A) 4.0 4.2 4.4 4.6 The power supply for the VDD pin of the FAN6100x is obtained from the VIN pin which is tied to VOUT. For IC operation during low VOUT, the VIN voltage is fed to a built-in charge-pump circuit which regulates the VDD pin voltage. The charge-pump circuit enables CC regulation down to VOUT of 2 V without external voltage supply to the IC. The VDD operation range determines the allowable VOUT variation range in CC mode. At high output voltages, the charge-pump circuit is disabled and a built-in Zener diode prevents the VDD pin from over-voltage damage. The HVDCP power supply is designed to operate for a © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 Mode Setting QP=0 and QN=0 For variable CC mode setting, the CC level is different for each VOUT level. The variable output current for each mode are shown in Table 2. 3. Design Considerations The CV and CC output of the HVDCP power supply are adaptive in nature. This makes the overall design approach more rigorous compared to a conventional power supply with a fixed output voltage. In CV operation, the output voltage changes according to the device requirements. In CC operation, the output current changes according to the output current mode setting on FAN6100x. The HVDCP specification details a method for the device charger to request a voltage from the power supply while maintaining USB BC 1.2 compatibility and allowing compatibility with other specifications that use the USB pin. The voltages are based on the capabilities of the HVDCP power supply. Mode Description Variable CC Mode 4.8 1.5 5.0 7.0 9.0 12.0 1.1 www.fairchildsemi.com 3 AN-8209 APPLICATION NOTE For fixed 2.0 A CC mode setting, CC output is fixed at 2.0 A except 12 V mode as shown in Table 4. For mode 3 setting, the CC output is fixed at 3 A for each output voltage level as shown in Table 8. Table 4. Fixed 2.0 A CC Mode Specifications Table 8. Mode 3 Specifications Output Voltage (V) Rated Current Output Voltage (V) 4.0 4.0 4.2 4.2 4.4 4.4 4.6 4.8 4.6 2.0 5.0 7.0 7.0 9.0 9.0 1.56 For FAN6100HM, the constant output current mode selection specifications are different than the FAN6100M and FAN6100Q as shown in Table 5 12.0 For mode 4 setting, the CC output is fixed at 3 A except for 12 V mode as shown in Table 9. Table 9. Mode 4 Specifications Table 5. Mode Descriptions and Settings of FAN6100HM Mode Description Mode Setting Mode 1 QP=0 and QN=0 Mode 2 QP=0 and QN=1 Mode 3 QP=1 and QN=0 Mode 4 QP=1 and QN=1 Output Voltage (V) 4.2 4.4 4.6 3.0 4.8 5.0 7.0 9.0 Mode 1 Specifications Output Voltage(V) Rated Current 4.0 For mode 1 setting, the CC output is fixed at 2 A for each output voltage level as shown in Table 6. Table 6. 3.0 4.8 5.0 12.0 Rated Current 12.0 2.25 Rated Current (A) 4.0 4. Design Procedure 4.2 In this section, a design procedure is presented using the schematic of Figure 1 as a reference. All relevant equations to select the components are also presented. The HVDCP power supply is designed for the output voltage and current modes as shown in Table 10. 4.4 4.6 4.8 2.0 5.0 The design specifications are: 7.0 9.0 12.0 For mode 2 setting, the CC output is fixed at 2.5 A except for 12 V mode as shown in Table 7. Table 10. Nominal Output Voltage and Current Vo N1 / I o N1 Table 7. Mode 2 Specifications Output Voltage (V) Vo Rated Current (A) 4.2 Vo 4.4 4.8 2.5 5.0 7.0 9.0 12.0 © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 N2 / Io N2 Vo N 3 / I o N 3 4.0 4.6 Line Voltage Range: 90~264 VAC Line Frequency: 60 Hz Maximum Output Power (Po): 15 W 1.87 N4 / Io N4 5 V/2.0 A 7 V/1.8 A 9 V/1.67 A 12 V/1.25 A [STEP-1] Determine Input Bulk DC Voltage Range and Input Bulk Capacitor (CDL) Before input bulk DC voltage range determination, it is required to estimate the power conversion efficiency (Eff) to calculate the rated input power. If no reference data is available, set Eff = 80-85% for high voltage output application. Total Input power, PIN, can be calculated as: www.fairchildsemi.com 4 AN-8209 PIN APPLICATION NOTE Po Eff ratio is obtained with a given de-rated MOSFET breakdown voltage (VDSS_DRT) as: (3) It is typical to select the DC link capacitor as 2-3 µF per watt of input power for universal input range (90264 VAC). With the DC link capacitor selected, the minimum DC link voltage (VDLmin) is obtained as: VDL min 2 VLINE min P C1 . fD 2 IN ch DL VDSS .DRT VDL max VOS _ DS Np Vo N 4 VF N s max (8) Voltage stress across secondary-side rectifier diode during PWM turn-on period is expressed as: VD (4) L NS VDL max VO N 4 NP (9) where: VLINEmin is the minimum line voltage; CDL is the DC link capacitance; fL is the line frequency; and Dch is the DC link capacitor charging duty ratio, which is typically about 0.2. VLINEmin and the ripple voltage change with input power. The maximum DC link voltage, VDLmax is given as: Minimum primary-to-secondary turns ratio is obtained with a given de-rated secondary-side rectifier diode breakdown voltage (VRRM_DRT) as: VDL max 2 VLINE max As observed in Equations (8) and (10), when Np/Ns increases, the voltage stress on the MOSFET increases while voltage stress on the rectifier diode decreases. Therefore, Np/Ns should be determined by the trade-off between the MOSFET and diode voltage stresses. (5) where VLINEmax is the maximum line voltage. (Design Example) Assuming the overall efficiency at 83% the input power at rated output power is obtained as: PIN Po 15W 18.07W Eff 83% By choosing two 12 µF capacitors in parallel for the DC link capacitor, the minimum and maximum DC link voltages for each condition are obtained as: VDL min 2 VLINE min P C1 . fD 2 IN ch DL VDL min 290V 2 Np VDL max N4 N S min VRRM .DRT Vo The transformer turns ratio between the auxiliary winding and the secondary winding (Na/Ns) should be determined by considering the allowable IC supply voltage (VDD) range. Due to the voltage overshoot of the auxiliary winding voltage caused by the transformer leakage inductance, the minimum VDD typically occurs at minimum load condition. VDD at minimum load condition is obtained as: VDD min L 18.071 0.2 78.49V 2 12 10 6.60 NA (VO N 1 VF ) VFA NS [STEP-2] Determine Transformer Turns Ratio For Quick Charge solution, the HVDCP power supply is requested to supply a higher voltage for portable device. Therefore, the transformer primary-to-secondary turns ratio (Np/Ns) is mainly determined by the maximum output voltage, power MOSFET breakdown voltage rating and rectifier diode breakdown voltage rating. Ns (VO N 4 VF ) Vgs (6) 10~15% of BVdss VDSS_DRT VOS_DS BVdss (7) where VF is the rectifier diode forward voltage drop, VoN4 is the nominal VOUT for 12 V mode, Np and Ns are number of turns for the primary-side and secondaryside, respectively. Usually a derating of 10-15% is applied on the specified breakdown voltage (BVDSS) to obtain VDSS_DRT. Maximum primary-to-secondary turns © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 (12) Since VDDmin is related to standby power consumption, smaller Na/Ns lead to lower standby power consumption. However, 2~3 V margin (VMRGN) should be added as shown in Equation (12), considering the VDD ripple caused by Burst Mode operation at no-load condition. where VOS_DS is overshoot voltage on MOSFET due to primary-side leakage inductance as shown in Figure 4. and VRO is reflected output voltage, defined as: Np NA VO N1 VF VFA VDD _ OFF VMRGN NS Voltage stress across MOSFET when the primary-side power MOSFET is turned off is expressed as: VRO (11) where; VFA is the diode forward-voltage drop of the auxiliary winding diode. The transformer turns ratio should be determined such that VDDmin is higher than the VDD UVLO voltage, VDD_OFF as shown in Equation (12): VDL max 2 264 373V VDS VDL max VRO VOS _ DS (10) NP (VO VF ) NS VDLmax Vds Figure 4. Voltage Stress Across Primary MOSFET www.fairchildsemi.com 5 AN-8209 APPLICATION NOTE (Design Example) (Design Example) By choosing a power MOSFET with a breakdown voltage of 640 V, and setting voltage derating at 10%, the maximum primary-to-secondary turns ratio should be: For 12 V mode, the maximum duty cycle DMax for minimum DC link voltage and maximum load is obtained as: VDSS .DRT VDL max VOS _ DS Np Vo N 4 VF N s max 640 0.9 373 75 10.3 12 0.4 VRO DMax Choosing a secondary-side rectifier diode with peak repetitive reverse voltage 60 V, and setting voltage derating at 15% for secondary-side rectifier diode, the minimum primary-to-secondary turns ratio should be: Np N S VDL max 373 9.56 N4 60 0.85 12 min VRRM 0.85 Vo Transformer primary-to-secondary turns ratio must be between 9.6 to 10.3. We choose 10 as NP/NS turns ratio. The allowable minimum VDD is 6.3 V, considering the tolerances of UVLO. Considering voltage ripple on VDD caused by burst operation at no-load condition, a 2 V margin is added for VDD voltage calculation at no-load condition, calculated as: VDD min NA VO N 1 VF VFA VDD _ OFF VMRGN NS NA 5 0.4 0.7 6.5 2 NS NA 1.74 NS NP 10 (VO N 4 VF ) (12 0.4) 124V NS 1 VRO VRO VDL min 124 0.612 124 78.49 The transformer primary-side inductance with setting KRF=0.8 is calculated as: Lm (VDL min DMax )2 (78.49 0.655)2 653 H 2 PIN f S K RF 2 18.07 140k 0.8 [STEP-4] Set Constant Current Mode FAN6100x provides flexible output CC choice for different power ratings via QP and QN setting. Figure 5 shows CC mode selection circuit. After IC turns on, the internal current source IS1 and IS2, which are 2 μA current sources, flowing out of the QP and QN pin separately. The CC mode selection comparator compares QP and QN analog input voltage with reference voltage and produces logic output high “1” or low “0”. It is not necessary to add a component for comparator logical output high “1” setting of CC mode selection. However, a 1.8 MΩ resistor can be used between the QP or QN pin and GND for noise immunity. It is recommended to connect the QP or QN pin directly to GND for comparator logical output low “0” setting of CC mode selection. To minimize the power consumption of the IC by minimizing VDD at no-load condition, Na / Ns is determined as 1.8. VDD IS1 [STEP-3] Designing the Transformer For CCM operation, the maximum duty cycle, DMax, ocurrs at maximum load and minimum input voltage. It is obtained as: DMax VRO VRO VDL min QN 3.6 V / 0.4 V QP (13) 3.6 V / 0.4 V Primary-side inductance Lm is estimated as: Lm (VDL min DMax )2 2 PIN f S _140 kHz K RF Figure 5. (14) where VDLmin and PIN are specified in Equation (4). Usually VDLmin is on low line condition. VRO is reflected output voltage, and fs_140kHz is the switching frequency at low line condition (140 khz). KRF is the ripple factor at full load and minimum input voltage condition. It is recommended that KRF = 1 for DCM operation and KRF < 1 for CCM operation. When designing the flyback converter to operate in CCM, it is reasonable to set KRF = 0.4-0.8 for the HVDCP power supply application. © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 IS2 Constant Current Mode Selection (Design Example) For variable CC mode setting, QP and QN both should be analog input low voltage for internal comparator to produce logical output low “0”. It is typical to connect QP and QN directly to GND. [STEP-5] Set Secondary-Side Output Constant Current Sensing Resistor The constant current (CC) regulation is implemented by sensing the output current via current-sense resistor (RCS_SEC) connected between the CSP and CSN pins and placed on the output ground return path. The sensed signal is amplified by internal current sensing amplifier AV-CCR and compared with internal current reference (VCCR) to generate a CC compensation signal (SIGCC) which becomes the gate signal of the CC MOSFET (MOSCC). www.fairchildsemi.com 6 AN-8209 APPLICATION NOTE VCCR level adjusts internally depending on the CC mode selection. Table 11 shows the corresponding VCCR thresholds. During CC mode, SIGCC is high and MOSCC stays in an active state, pulling current to drive SFB low. At this time, SIGCV is low and MOSCV stays in an inactive state. Thus the feedback signal, SFB, is driven by MOSCC. SFB is transferred to the primary-side PWM controller using an opto-coupler. The constant current point (IO_CC) can be set by selecting the current sensing resistor as: V 1 I O _ CC CCR (15) AV CCR RCS _ SEC Table 11. CC Mode Thresholds Symbol Parameter AV-CCR Current Sense Amplifier Gain 10 VCCR for Variable CC Mode at 5 V 1.20 V VCCR-VR-9V VCCR for Variable CC Mode at 9 V 0.96 V VCCR-VR-12V VCCR for Variable CC Mode at 12 V 0.72 V VCCR-FIX-1.5A VCCR for Fixative CC Mode at 1.5 A 0.87 V VCCR-FIX-2.0V VCCR for Fixative CC Mode at 2.0 A 1.20 V AV-CCR-UVP (Design Example) Using the CC regulation with primary-side-regulation (PSR) technique for over-current protection, we set the output CC regulation by FAN501A at 2.55 A, the primary-side sensing resistor is obtained as R CS_PRI = N P 1 VCCR 1 2.43 10 0.794 NS IO_CC K 2.55 12 Choosing primary-side sensing resistor RCS _ PRI is 0.8 Ω. Typ. VCCR-VR-5V CC attenuator for VIN UVP Attenuator at 9 V/12 V secondary CC limit. The primary CC regulation plays an important role during startup and when FAN6100x is damaged. [STEP-7] Select Output Voltage Sensing Resistor for VREF Pin The constant voltage (CV) regulation is implemented in the same way as the conventional isolated power supply. The output voltage is sensed on the VREF pin via the resistor divider, RF1 and RF2 and compared with the internal adjustable voltage references (VCVR). shows the corresponding VCVR thresholds. Table 12. CV Mode Thresholds 0.125 (Min.) Symbol Parameter Typ. VGreen-H VCCR for Green Mode Disable 0.495 V VCVR-5V VCVR for CV Mode at 5 V 1.00 V VGreen-L VCCR for Green Mode Enable 0.37 V VCVR-7V VCVR for CV Mode at 7 V 1.40 V Since there is a low standby power requirement, the output current in the sensed signal is used to determine green mode operation. FAN6100x enters green mode when the amplified output current sensed signal is smaller than VGreen-L (0.37 V). During Green Mode, the charge pump function is disabled to reduce power consumption; the operating current is reduced from 2.4 mA to 850 µA. If amplified output current sensed signal increases to become larger than VGreen-H (0.495 V), it leaves green mode and charge pump function is enabled. VCVR-9V VCVR for CV Mode at 9 V 1.80 V VCVR-12V VCVR for CV Mode at 12 V 2.40 V (Design Example) Setting the output CC regulation by secondary side at 2.3 A for 5 V mode, the secondary-side sensing resistor is obtained as: RCS _ SEC V 1 1 1.2 CCR VR 5V 52.1m A V CCR I O _ CC 10 2.3 [STEP-6] Set the Primary-Side Output Constant Current FAN501AMPX implements CC regulation with primaryside-regulation (PSR) technique. The output constant current is determined by the primary-side sensing resistor (RCS_PRI) and transformer turns ratio as: N P 1 VCCR NS IO_CC K Vo N VCVR (17) (16) In order to have low stand-by power and noise immunity for VREF, it is essential to have low currents flowing through the VREF resistor divider. It is typical to design the current through low side resistor between 100-250 µA. Selecting the low side resistor current to be 130 µA and constant current reference voltage at 5 V (VCVR-5V) is 1 V, the RF2 can be calculated as: RF 2 VCVR 5V 7.7k 130u By choosing low side resistor divider RF2 is 7.5 kΩ, the RF1 can be obtained as: where VCCR is 2.43 V and K=12 for FAN501AMPX. Since FAN6100x implements secondary-side CC regulation, the primary CC limit is set at larger than © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 RF 1 RF 2 RF 2 (Design Example) We can choose secondary-side sensing resistor RCS_SEC as 52 mΩ. R CS_PRI = This comparator generates a CV compensation signal (SIGCV) which becomes the gate signal for the CV MOSFET (MOSCV). During CV mode, SIGCV is high and MOSCV stays in an active state, pulling current to drive SFB low. At this time, SIGCC is low which keeps MOSCC in an inactive state and having no impact on SFB. SFB is transferred to the primary-side using an opto-coupler and applied to the PWM comparator through attenuator Av to determine the duty cycle. The output voltage can be derived by setting RF1 and RF2, as calculated by: RF 1 V o N1 VCVR 5V VCVR 5V RF 2 5 1 1 7.5k 30k www.fairchildsemi.com 7 AN-8209 APPLICATION NOTE VIN [STEP-8] Set Capacitance for VDD and ChargePump Circuit Figure 6 shows the supply voltage circuit, including VDD and the charge-pump stage. The supply voltage is given by the VIN pin. The charge pump boosts the VDD voltage to allow normal operation of the controller when output voltage is low. Apart from the charge-pump circuit, it also includes a Low Dropout (LDO) pre-regulator. The FAN6100M/ FAN6100Q can withstand up to 20 V on the VIN pin and can be connected directly to the output terminal of a power supply. However, it is typical to connect a 100 Ω resistance between the VIN pin and VOUT a power supply and then connect 470 nF capacitor on VIN pin for improved ESD immunity. Figure 7 shows the timing diagram of charge pump operation. During startup, the charge-pump circuit is enabled when VIN voltage is larger than 2 V and boosts the VDD voltage to double the VIN voltage. In normal operation, the LDO pre-regulator regulates the input voltage of charge-pump circuit to 2.7 V and the chargepump circuit is enabled to boost the VDD voltage to 5.4 V as long as VIN is lower than VIN-CP (6.4 V). The chargepump circuit and the LDO pre-regulator is disabled when VIN is greater than VIN-CP (6.4 V), VIN voltage will directly supply to VDD. As VIN decreases below 6.2 V (VIN-CP-VIN-CP-Hys), the LDO pre-regulator regulates the input voltage of chargepump circuit to 2.7 V and the charge-pump circuit is enabled to boost the VDD voltage to 5.4 V. The chargepump circuit needs an external capacitor, CCP, typically 220 nF~1 µF, as the energy storage element to stabilize the operation of the LDO stage. When the charge-pump circuit is disabled, output capacitor supplies charging current to charge the hold-up capacitor CVDD. The VDD voltage is clamped by internal Zener diode to 5.4 V when the charge-pump circuit is disabled. The CVDD typically 100 nF~1 µF, as the energy storage element. 6.4V 6.2V 2.7V 2V VCLAMP 5.4V 2.7V VDD 5.4V Charge Pump ON Figure 7. (Design Example) Selecting the VDD pin to GND capacitor as 1 µF and CCP between CP pin and CN pin as 1 µF. When VIN voltage rises sharply, a delay by the LDO to turn on can cause voltage stress on VDD pin. In order to avoid this, it is recommended to connect a Zener diode on the VDD pin. [STEP-9] Feedback Loop Design In order to express the small signal AC transfer functions, the small signal variations of feedback voltage (vFB), controlled output voltage (Vo) and controlled output current (io) are introduced as vˆ , vˆ and iˆ . FB VO RCS_SEC VDD CCP CP 0.495V/0.37V 6.4V / 6.2V (18) RL 1 D ; rz _ cv 2 Ns D Lm Np ; 2 RL COUT GV _ CV ( AVCCR I R V N 1 m 1 DS L DL P ) 2.5 m ma RCS _ PRI I DS N S 2VRO VDL (19) where 1/2.5 is the attenuation factor of feedback voltage; IDS is the peak drain current at given operating condition; ma is the slope of slope compensation signal; and m is the slope of current sensing signal, given as: CSP Supply Voltage Block © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 1 D 1 RES _ C COUT The gain GV_CV of Equation (19) is defined as: CSN Figure 6. o RES_C is the effective series resistance of the output capacitor; COUT is effective output capacitance; RL is the effective output load resistance; Lm is specified in Equation (14); D is the duty cycle. CVDD 3.65V / 3.25V p _ cv VIN Voltage Magement with Charge Pump Internal Bias 1 s z _ cv 1 s rz _ cv vˆo GV _ CV vˆFB 1 s p _ cv where z _ cv CN o Since the FAN501AMPX operates a flyback converter in CCM operation, the CV control-to-output transfer function of the flyback converter is given by: The controller includes Under-Voltage Lockout (UVLO) protection. UVLO begins operation once the VDD voltage falls below VDD-off (3.25 V). CO1 Charge Pump Operation Timing Diagram www.fairchildsemi.com 8 AN-8209 m APPLICATION NOTE VDL RCS Lm (20) There is a Right Half Plane (RHP) zero (ωrz) in the control-to-output transfer function of Equation (19) which will cause a phase reduction by 90 degrees. For a proper feedback design, the crossover frequency should be placed well below the RHP zero. (Design Example) The output capacitor is selected as two 330 µF aluminum solid capacitor with effective series resistance 20 m. The effective output capacitance and its effective series resistance are given as: COUT 330 F 2 660 F RES 20m / 2 10m When the converter operates in CCM, the RHP zero has lowest frequency for low input voltage and full load condition. By designing the feedback loop with more than 45 degrees phase margin for low input voltage and full load condition, stability across all the operating ranges can be guaranteed. Considering CCM operation of a flyback converter for 5 V output, the system pole (wp_cv), RHP zero (wrz_cv) and zero (wz_cv) are obtained as: The system pole and zeroes vary with different output voltage and output current condition for HVDCP power supply. Hence, it is desired to check the feedback loop for all conditions for enough phase, and gain margin. rz _ cv An example of a suitable feedback compensation network for CV regulation is shown in Figure 2. It consists of capacitors, CLED = 3.3 nF, CFV1 = 470 nF, CFV2= 1 nF and CF1= 6.8 nF, and resistors, RLED = 1k Ω, RFV1 = 7.5 kΩ and RF1= 30.1 kΩ. z _ cv p _ cv where p z 1 RES _ C COUT ; rz 1 D (21) RL 1 D 2 Ns D Lm Np ; 2 RL COUT I R V N 1 m 1 1 DS L DL P ) 2.5 m ma RCS _ PRI I DS N S 2VRO VDL RL RL 1 D 2 Ns D Lm Np 2 689 103 rad / s 1 151103 rad / s RES _ C COUT GV _ CV ( I R V N 1 m 1 DS L DL P ) 2.5 m ma RCS _ PRI I DS N S 2VRO VDL 13.65dB In the CV feedback circuit design it is assumed that the current transfer ratio (CTR) of the opto coupler is 100%. The compensation circuit as shown in Figure 2 RLED =1 kΩ, CLED =3.3 nF, RFV1=7.5 kΩ, CFV2=470 nF, CFV1=1 nF, CF1= 6.8 nF and CFB=4 nF (including output capacitance of opto-transistor). For CFB, output capacitance of an opto-transistor is assumed to be 3 nF and a 470 pF external capacitor is used. Considering the CCM operation of a flyback converter in CC region for 5 V mode, the system pole (ωp_cc), RHP zero (ωrz_cc) and zero (ωz_cc) are obtained as: The gain GV _ CC of Equation (21) is defined as: GV _ CC ( 786rad / s The gain GV_CV is obtained as: For CC regulation, the CC control-to-output transfer function of the flyback converter in CCM operation is given by: 1 s z 1 s rz iˆo GV _ CC ˆvFB 1 s p 1 D RL COUT (22) p _ cc Figure 2 also shows the suitable feedback compensation network for CC regulation. It consists of capacitor, CFC1= 47 nF and resistor, RFC1 = 1 kΩ. Note that the opto-coupler introduces a mid-frequency pole due to the collector-emitter junction capacitance. Since the collector-base junction in a photo-transistor is used as a light detector, its area is relatively large, which introduces a large effective collector-emitter junction capacitance, COTP. Since FAN501A has a high FB pin resistance, ZFB it causes one pole at low frequency which is around 1~10 kHz. rz _ cc z _ cc 1 D RL COUT 954rad / s RL 1 D 2 Ns D Lm Np 2 703 103 rad / s 1 151103 rad / s RES _ C COUT The gain GV _ CC is obtained as: GV _ CC ( I R V N 1 m 1 1 DS L DL P ) 2.5 m ma RCS _ PRI I DS N S 2VRO VDL RL 7.63dB For CC feedback circuit design, the compensation circuit as shown in Figure 2, RFC1=1 kΩ and CFC1=47 nF. © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 www.fairchildsemi.com 9 AN-8209 APPLICATION NOTE [STEP-10] Select Cable Compensation Resistor Voltage Drop mode changes from high output voltage to low output voltage can avoid system shutdown. FAN6100x incorporates programmable cable voltage drop compensation function by adjusting one external resistor to maintain constant voltage regulation at the end of the USB cable. Figure 9 shows the internal block of bleeder function. FAN6100x implements the bleeder function to discharge the output voltage rapidly during mode changes. The BLD pin is connected to the output voltage terminal as a discharging path and can withstand up to 20 V. When the device requests a change from high voltage to low voltage, an internal switch is turned on to discharge the output voltage. The switch stays on for a time period of tBLD-MAX. When the voltage drops, the feedback loop gets saturated since the output voltage is higher than its target level during transition and it takes some time to come out of saturation for the new voltage setting. Because the power supply does not operate until the feedback loop comes out of saturation causing the output voltage to keep dropping, there exists some amount of output voltage dip during mode transition. Hence, in order to minimize the output voltage dip, it is recommended to add a 2-step bleeder circuit; a 5.1 V Zener diode and an external resistance (RBLD) which slows down the output voltage drop while the feedback loop comes out of saturation. In the first step, the bleeder current (IBLD) is determined by internal MOSFET RDSON; the typical value of which is 240 mA. This high current allows rapid decay of the voltage. Once the output voltage is close to 5.1 V, the Zener diode starts blocking and RBLD is determined by external bleeder resistor (RBLD). The voltage decay in this stage is much slower. This allows the feedback loop enough time to react to the transition and prevent the output voltage from dropping too much. IBLD in the 2nd stage can be calculated as: Figure 8 shows the internal block of the cable voltage drop compensation function. Output current information is obtained from the amplified current sensing voltage. Depending on the external resistor, the current signal is modulated to offset the CV loop reference voltage, V CVR. Thus, output voltage is increased by this offset voltage on the CV loop reference to compensate for cable voltage drop. The external compensation resistor, RCOMR, can be calculated by: RCOMR R RF 2 1 1 Cable RF 1 RF 2 RCS _ SEC AV CCR KCOMR CDC (23) where Rcable is cable resistance, KCOMR-CDC is cable compensation design parameter of the controller, which is 1.0 µA/V. RCable CO1 VO_End RCS_SEC CSP XAVCCR CSN IO COMR I BLD Cable Voltage Drop Compensation RF1 RCOMR CCOMR VO RBLD (24) VREF RF2 Σ VCVR Figure 8. IBLD Mode Condition Cable Voltage Drop Compensation 5.1V ZD (Design Example) Mode Change Signal from high output voltage to low output voltage R RF 2 1 1 Cable 92k RF 1 RF 2 RCS _ SEC AV CCR KCOMR CDC In order to achieve a tight CV regulation during dynamic load, it is recommended that one capacitor CCOMR is connected on COMR pin. Typically, the suggested value is 100 to 470 nF. [STEP-11] Select Bleeder Resistor For adaptive output power supply, it is necessary to ensure that a high output voltage can drop to a lower output voltage quickly during the mode change. Hence, a discharge path on the output of the power supply is required. This is especially critical under no-load condition where the natural discharge speed of the output capacitor is low. Enabling the “bleeder” function when the © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 RBLD BLD Setting cable resistance is 0.24 Ω, the RCOMR can be obtained as: RCOMR VO Figure 9. Bleeder Function (Design Example) By choosing the 5.1 V Zener diode and setting RBLD is 51 kΩ, the second step bleeder discharging current (IBLD) can be obtained as: I BLD VO 100uA RBLD www.fairchildsemi.com 10 AN-8209 APPLICATION NOTE [STEP-12] Over-Voltage and Under-Voltage Protection FAN6100x implements VIN Under-Voltage Protection (VIN UVP) and VIN Over-Voltage Protection (VIN OVP) using output voltage and output current sense signal. Figure 10 shows the VIN UVP block. Once VOUT drops below VIN-UVP-L, the VIN UVP function is enabled and the output current is reduced by CC mode VIN UVP attenuator, AV-CCR-UVP. Figure 11 shows the V IN OVP block, which is adaptive according to CV mode setting. V OUT is sensed through the VIN pin. Once VOUT rises to the respective VIN-OVP level, OVP is triggered. Then the OVP pin is pulled down to ground through an internal switch until VDD-OFF (3.25 V) is reached. [STEP-13] Protocol Communication Qualcomm® Quick Charge™ 2.0 Class A Technology FAN6100Q is compatible with Qualcomm® Quick Charge™ 2.0 Class A technology which is capable of producing initial 5 V at the startup, and then 9 V or 12 V according to the protocol commands through DP and DN signal. If portable device is detected as a HVDCP, FAN6100Q will complete the USB BC1.2 procedure first and then the output voltage is determined by both DP and DN voltage as shown in Table 13 Table 13. DP and DN Voltage Detection Voltage HVDCP Power Supply DP DN Output Voltage The adaptive OVP can be disabled by connecting this pin directly to ground. Then, the OVP function is provided by the primary IC through auxiliary winding feedback. However, only the highest voltage setting can be protected by the primary IC. 0.6 V 0.6 V 12 V 3.3 V 0.6 V 9V 0.6 V 3.3 V Reserved 3.3 V 3.3 V Reserved The output current during OVP can be calculated as: 0.6 V GND I O _ CC 1 A V CCR MediaTek Pump Express Plus Fast-Charging VCCR AV CCR UVP RCS _ SEC (25) CO1 VO_End RCS_SEC IO CSN CSP VIN XAVCCR IREF SFB MOSCC Mode Condition Multiplier VIN-UVP VIN UVP Protection SIGCC Figure 10. FAN6100M is compatible with MediaTek Pump ExpressTM Plus fast-charging which can permit receiving output voltage change signal by output current patterns. There are two kinds of output current control pattern, one for output voltage increase and another for output voltage reduction as shown in the Figure 12 and Figure 13. FAN6100M monitors the output current control pattern by CSP and CSN pin. The initial voltage is 5 V and increment of output voltage from 5 V to 7 V to 9 V to 12 V is done step by step after output current control pattern for voltage increase is detected. Similarly, the output voltage can be reduced step by step after output current control pattern for output voltage reduction detection is completed. If the output current decreases to zero over Current Plug-out Detection watchdog timer TWDT (180 ms), the HVDCP power supply resets output voltage to 5 V. FAN6100M not only supports MediaTek Pump ExpressTM Plus fast-charging for 5 V to 12 V quick charger application but also for 4 V to 5 V low output voltage charger solution. Mode Condition VCCR 5V ™ VIN Under-Voltage-Protection Output Voltage Return to 5V after TWDT 7V 5V CO1 Output Current VO_End C TWDT C B B A B RCS VIN Figure 12. Output Current Control Pattern for Output Voltage Growth OVP Output Voltage OVP Return to 5V after TWDT 9V 7V 5V Mode Condition VIN-OVP Output Current B Figure 11. TWDT B B C C A VIN Over-Voltage-Protection Figure 13. © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 Output Current Control Pattern for Output Voltage Reduction www.fairchildsemi.com 11 AN-8209 APPLICATION NOTE Fairchild’s FCP-Single Communication Protocol FAN6100M is compatible with Fairchild’s FCP-Single communication protocol includes high-speed mode and low-speed mode to apply high-end processor and low-end processor application. FCP-Single communication protocol detection uses DN signal to determine output voltage of HVDCP power supply. Figure 14 shows FCPSingle communication protocol control signal waveform. FAN6100M receives output voltage change signal from portable device by DN pin signal. FCP-Single protocol starts with a low signal (TSTART) and then deliver highlow-high-low-high-low signal with the specific pulse width. By acknowledging the different period of DN pin signal, the output voltage can be adjusted. There are four types of the control signal for the output voltage adjustment, 1. Output voltage increase (SV+_HS) for high-speed mode detection. (TSV+_HS = 182 μs) 2. Output voltage decrease to 5 V (5V_HS) for high-speed mode detection. (T5V_HS = 102 μs) 3. Output voltage increase (SV+_LS) for low-speed mode detection. (TSV+_LS = 15.3 ms) 4. Output voltage decrease to 5 V (5V_LS) for low-speed mode detection. (T5V_LS = 10 ms) A device which is capable of either high speed or low speed communication can request for a specific voltage according to the protocol. For example, in the high-speed mode detection, output voltage increase from the initial output voltage of 5 V can be done by delivering high-lowhigh-low-high-low signal with time period of TSV+_HS. This will increase output voltage from 5 V to 7 V to 9 V to 12 V step by step. If the DN pin signal has time period T5V_HS , output voltage will be reduced to 5 V. Output Voltage Control Signal Period TSTART Figure 14. Period FCP-Single Communication Protocol Control Signal Waveform 5. PCB Layout Guidelines Printed Circuit Board (PCB) layout and design are very important for the adaptive charger. Good PCB layout enhances CC/CV regulation accuracy, surge/ESD immunity and ensures proper protocol communication. The following guidelines are recommended for layout designs. As indicated by 1, the GND of COMR, VREF, QP and QN should be connected to the SGND first, then to other circuitry. As indicated by 2, the GND of VDD should be connected to the PGND and CVDD should be placed close to the controller for good decoupling and low switching noise. As indicated by 3, the Y-capacitor should be connected directly to the ground of the USB connector to discharge the ESD energy to the AC line through the primary-side main ground. Because ESD energy is delivered from the secondary-side to the primary-side through the transformer stray capacitor or the Y capacitor, the controller circuit should not be placed on the discharge path. Connect ground in 1 →2 → 3 sequence. This helps avoid common impedance interference for the sense signal. Secondary-side sensing resistor (RCS_SEC) should be put between output capacitor and USB port with short traces; it will enhance CC regulation accuracy. VO D+ D- AC IN RCS_SEC GND 8 7 U1 FAN501A 6 4 5 10 1 SGND 9 2 11 10 9 2 1 3 3 12 18 13 U2 FAN6100M 19 VDD PGND 2 15 17 14 16 6 5 4 8 20 COMR QP QN VREF 7 SGND 1 3 Figure 15. © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 Recommended Layout www.fairchildsemi.com 12 AN-8209 APPLICATION NOTE 6. Final Schematic of Design Example R33 7.32kΩ C18 6.8nF R32 30.1kΩ VO D+ D- GND Figure 16shows the final schematic of 15 W adaptive charger design example. EPC1716 core is used for the transformer. Figure 17shows the transformer winding structure. Figure 18 and Figure 19 show the PCB pattern. C22,220nF R17,27Ω 20 8 R35 C19 470nF 7.5kΩ R8 47kΩ C9 3.3nF CY,100pF U3 FOD817B D4 MMSZ5244B R25 10KΩ C4 22F Q2 MMBT2222A 5 C7 20pF R11 8.25kΩ R9 62KΩ 10 3 2 9 7 4 C6, 470pF R27 15kΩ AC IN F1 2A/250V TH1 SCK053 BR1 MDB10SV U3 FOD817B C1,22F/400V L2 10H L1 330H C2,22F/400V 6 5 8 1 R13 47Ω R7,49.9kΩ D1 MMSD3070 4 R14/1.6Ω, R15/1.6Ω R16 100Ω Q1 FCU900N60Z 2 R3 0Ω R2 300kΩ D6 FFM107 C3, 1nF/1kV 1 R1,49.9kΩ U1 FAN501A C23 10F EPC1716 6 7 R29 1kΩ C8 1nF D7, TSP20U60S C15,330F D2 1N4148WS C20,1nF ZD1,6.2V C16,330F TX1 C13 47nF R30 1kΩ 16 17 5 4 R31,91kΩ C10,1F 19 18 C11,1F 3 R21 1kΩ C17 1nF 11 10 R22 1kΩ 9 R19/100mΩ, R20/100mΩ 2 U2 FAN6100M R24,51kΩ R18 18Ω C14 470nF 1 7 6 14 15 12 13 ZD2,5.1V Figure 16. © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 Final Schematic of 15 W Adaptive Charger Design Example www.fairchildsemi.com 13 AN-8209 APPLICATION NOTE 1 3 1 3 S E Shielding (Φ 0.025x1) GND 5 7 6 7 2 4 GND 5 4 GND 5 6 3 Drain 2 5 ½ Primary Winding (Φ 0.2x1) S S1 S2 E Secondary Winding (Φ 0.7x1) E1 E2 Auxiliary Winding + Shielding (Φ 0.15) Primary Winding (Φ 0.2x1) S BOBBIN Figure 17. Transformer Specifications & Construction Table 14. Core: EPC1716, Bobbin: EPC1716 (7 Pins) Terminal Isolation Layer Winding Wire Turns Start Pin End Pin Np-2 3 1 0.2 mm*1 26 2 Copper shielding 5 Open Copper foil 0.025 mm 1 2 Ns 7 6 0.7 mm*1 6 2 Naux 4 5 0.15 mm*1 11 2 Na-shield 5 Open 0.15 mm*1 11 2 Np-1 2 3 0.2 mm*1 34 2 Table 15. Turns Transformer Specifications Pin Specification Inductance 2-1 600 µH ±5% 100 kHz Effective Leakage 2-1 30 µH Max. Short other pin Figure 18. Figure 19. Printed Circuit Board - Top View © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 Remark Printed Circuit Board - Bottom View www.fairchildsemi.com 14 AN-8209 APPLICATION NOTE 7. Test Results of Design Example To show the validity of the design procedure presented in this application note, the adaptive charger of the design example was built and tested. All the circuit components are used as designed in the design example. Figure 20, Figure 21 and Figure 22 show the measured efficiency for four different load conditions (25%, 50%, 75% and 100% of nominal power) at 5 V, 9 V and 12 V mode, respectively. The four point average efficiencies at 115 VAC and 230 VAC condition for each output are: Figure 22. 12 V Efficiency Curve (4 Point Average: 100%, 75%, 50%, 25%) 5 V Mode: 87.35% (115 VAC) and 88.47% (230 VAC) 9 V Mode: 85.61% (115 VAC) and 85.36% (230 VAC) 12 V Mode: 85.59% (115 VAC) and 85.53% (230 VAC) Figure 23 shows the no-load power consumption for 5 V output at different line voltages. Even for 264 Vrms AC line, the no-load standby power consumption is less than 20 mW, meeting the five-star level of new power consumption regulation for charger. Figure 24, Figure 25 and Figure 26 show the measured output voltage and output current regulation profile for different output voltage mode. For 5 V output voltage mode, the output current is regulated between 2.3 A and 2.4 A while the output voltage drops from 5 V down to 3 V. For 9 V mode, the output current is regulated between 1.8 A and 1.9 A while the output voltage drops down to 7.65 V. For 12 V output mode, the output current is regulated between 1.3 A and 1.4 A while the output voltage drops down to 10.2 V. Figure 23. 5 V Standby Power Consumption Figure 24. 5 V CV/CC Deviation Curve Figure 25. 9 V CV/CC Deviation Curve Figure 26. 12 V CV/CC Deviation Curve Figure 20. 5 V Efficiency Curve (4 Point Average: 100%, 75%, 50%, 25%) Figure 21. 9 V Efficiency Curve (4 Point Average: 100%, 75%, 50%, 25%) © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 www.fairchildsemi.com 15 AN-8209 APPLICATION NOTE 8. Related Resources AN-4137 — Design guideline for Offline Flyback Converters Using Fairchild Power Switch (FPS™) FAN501A — Product Information FAN6100M — Product Information FAN6100Q — Product Information FAN6100HM — Product Information © 2015 Fairchild Semiconductor Corporation Rev. 1.0 • 4/1/15 www.fairchildsemi.com 16