Revised August 2001 74LCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs General Description Features These 36-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. ■ 5V tolerant inputs and outputs Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The LCX32500 is designed for low voltage (2.5V or 3.3V) VCC applications with the capability of interfacing to a 5V signal environment. The LCX32500 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power. ■ 2.3V–3.6V VCC specifications provided ■ 6.0 ns tPD max (VCC = 3.3V), 20 µA ICC max ■ Power down high impedance inputs and outputs ■ Supports live insertion/withdrawal (Note 1) ■ ±24 mA output drive (VCC = 3.0V) ■ Uses patented noise/EMI reduction circuitry ■ Latch-up performance exceeds 500 mA ■ ESD performance: Human body model > 2000V Machine model > 200V ■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Note 1: To ensure the high-impedance state during power up or down, OE should be tied to VCC and OE tied to GND through a resistor: the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number 74LCX32500GX (Note 2) Package Number BGA114A Package Description 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide [TAPE and REEL] Note 2: BGA package available in Tape and Reel only. © 2001 Fairchild Semiconductor Corporation DS500406 www.fairchildsemi.com 74LCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs April 2001 74LCX32500 Connection Diagram Pin Descriptions Pin Names Description 1A1 - 1A18 Data Register A Inputs/3-STATE Outputs 2A1 - 2A18 1B1 - 1B18 Data Register B Inputs/3-STATE Outputs 2B1 - 2B18 CLKAB1, CLKBA1 Clock Pulse Inputs CLKAB2, CLKBA2 LEAB1, LEBA1 Latch Enable Inputs LEAB2, LEBA2 OEAB1, OEBA1 Output Enable Inputs OEAB2, OEBA2 FBGA Pin Assignments (Top Thru View) Truth Table (Note 3) Inputs OEABn LEABn CLKABn An 1 2 5 6 A 1A2 1A1 LEAB1 CLKAB1 3 4 1B1 1B2 B 1A4 1A3 OEAB1 GND 1B3 1B4 C 1A6 1A5 GND GND 1B5 1B6 D 1A8 1A7 VCC VCC 1B7 1B8 E 1A10 1A9 GND GND 1B9 1B10 Output F 1A12 1A11 GND GND 1B11 1B12 Bn G 1A14 1A13 VCC VCC 1B13 1B14 1A15 1A16 GND GND 1B16 1B15 1A17 1A18 1B18 1B17 L X X X Z H H H X L L J H H X H H K NC GND NC L ↓ CLKAB2 H L L L 2A2 2A1 OEAB2 GND 2B1 2B2 OEBA1 CLKBA1 LEAB2 LEBA1 H L ↓ H H M 2A4 2A3 GND GND 2B3 2B4 H L H X B0 (Note 4) N 2A6 2A5 VCC VCC 2B5 2B6 H L L X B0 (Note 5) P 2A8 2A7 GND GND 2B7 2B8 R 2A10 2A9 GND GND 2B9 2B10 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance Note 3: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Note 4: Output level before the indicated steady-state input conditions were established. T 2A12 2A11 VCC VCC 2B11 2B12 U 2A14 2A13 GND GND 2B13 2B14 V 2A15 2A16 OEBA2 CLKBA2 2B16 2B15 W 2A17 2A18 LEBA2 2B18 2B17 GND Note 5: Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW. Functional Description HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high impedance state. For A-to-B data flow, the LCX32500 operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CLKAB. Output-enable OEAB is active-HIGH. When OEAB is www.fairchildsemi.com Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active HIGH and OEBA is active LOW). 2 74LCX32500 Logic Diagrams 3 www.fairchildsemi.com 74LCX32500 Absolute Maximum Ratings(Note 6) Symbol Parameter Value Conditions VCC Supply Voltage −0.5 to +7.0 VI DC Input Voltage −0.5 to +7.0 VO DC Output Voltage −0.5 to +7.0 Units V V Output in 3-STATE −0.5 to VCC + 0.5 V Output in HIGH or LOW State (Note 7) IIK DC Input Diode Current −50 VI < GND IOK DC Output Diode Current −50 VO < GND +50 VO > VCC mA mA IO DC Output Source/Sink Current ±50 mA ICC DC Supply Current per Supply Pin ±100 mA IGND DC Ground Current per Ground Pin ±100 mA TSTG Storage Temperature −65 to +150 °C Recommended Operating Conditions (Note 8) Symbol VCC Parameter Supply Voltage VI Input Voltage VO Output Voltage IOH/IOL Output Current TA Free-Air Operating Temperature ∆t/∆V Input Edge Rate, VIN = 0.8V–2.0V, VCC = 3.0V Min Max Operating 2.0 3.6 Data Retention 1.5 3.6 0 5.5 HIGH or LOW State 0 VCC 3-STATE 0 5.5 VCC = 3.0V − 3.6V ±24 VCC = 2.7V − 3.0V ±12 VCC = 2.3V − 2.7V ±8 Units V V V mA −40 85 °C 0 10 ns/V Note 6: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 7: IO Absolute Maximum Rating must be observed. Note 8: Unused (inputs or I/O's) must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol VIH VIL VOH VOL Parameter Conditions HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Voltage LOW Level Output Voltage IOH = −100 µA VCC TA = −40°C to +85°C (V) Min 2.3 − 2.7 1.7 2.7 − 3.6 2.0 Max V 2.3 − 2.7 0.7 2.7 − 3.6 0.8 2.3 − 3.6 VCC − 0.2 IOH = −8 mA 2.3 1.8 IOH = −12 mA 2.7 2.2 IOH = −18 mA 3.0 2.4 IOH = −24 mA 3.0 2.2 IOL = 100 µA 2.3 − 3.6 Units V V 0.2 IOL = 8 mA 2.3 0.6 IOL = 12 mA 2.7 0.4 IOL = 16 mA 3.0 0.4 V IOL = 24 mA 3.0 0.55 II Input Leakage Current 0 ≤ VI ≤ 5.5V 2.3 − 3.6 ±5.0 µA IOZ 3-STATE I/O Leakage 0 ≤ VO ≤ 5.5V 2.3 − 3.6 ±5.0 µA 0 10 µA VI = VIH or VIL IOFF Power-Off Leakage Current www.fairchildsemi.com VI or VO = 5.5V 4 Symbol (Continued) Parameter VCC Conditions TA = −40°C to +85°C (V) ICC ∆ICC Quiescent Supply Current Increase in ICC per Input Min Units Max VI = VCC or GND 2.3 − 3.6 20 3.6V ≤ VI, VO ≤ 5.5V (Note 9) 2.3 − 3.6 ±20 VIH = VCC −0.6V 2.3 − 3.6 500 µA µA Note 9: Outputs disabled or 3-STATE only. AC Electrical Characteristics TA = −40°C to +85°C, RL = 500 Ω Symbol Parameter VCC = 3.3V ± 0.3V VCC = 2.7V VCC = 2.5V ± 0.2V CL = 50 pF CL = 50 pF CL = 30 pF Min Max Min Max Min Max 1.5 6.0 1.5 7.0 1.5 7.2 Bus to Bus 1.5 6.0 1.5 7.0 1.5 7.2 tPHL Propagation Delay 1.5 6.7 1.5 8.0 1.5 8.4 tPLH Clock to Bus 1.5 6.7 1.5 8.0 1.5 8.4 tPHL Propagation Delay 1.5 7.0 1.5 8.0 1.5 8.4 tPLH LE to Bus 1.5 7.0 1.5 8.0 1.5 8.4 tPZL Output Enable Time 1.5 7.2 1.5 8.2 1.5 9.4 1.5 7.2 1.5 8.2 1.5 9.4 fMAX Maximum Clock Frequency 170 tPHL Propagation Delay tPLH tPZH tPLZ Output Disable Time tPHZ Units MHz 1.5 7.0 1.5 8.0 1.5 8.4 1.5 7.0 1.5 8.0 1.5 8.4 ns ns ns ns ns tS Setup Time 2.5 2.5 3.0 ns tH Hold Time 1.5 1.5 2.0 ns tW Pulse Width 3.0 3.0 3.5 ns Dynamic Switching Characteristics Symbol VCC TA = 25°C (V) Typical CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 0.8 CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 0.6 CL = 50 pF, VIH = 3.3V, VIL = 0V 3.3 −0.8 CL = 30 pF, VIH = 2.5V, VIL = 0V 2.5 −0.6 Parameter VOLP Quiet Output Dynamic Peak VOL VOLV Quiet Output Dynamic Valley VOL Conditions Units V V Capacitance Typical Units CIN Symbol Input Capacitance Parameter VCC = Open, VI = 0V or VCC Conditions 7 pF CI/O Input/Output Capacitance VCC = 3.3V, VI = 0V or VCC 8 pF CPD Power Dissipation Capacitance VCC = 3.3V, VI = 0V or VCC, f = 10 MHz 20 pF 5 www.fairchildsemi.com 74LCX32500 DC Electrical Characteristics 74LCX32500 AC LOADING and WAVEFORMS Generic for LCX Family FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance) Test Switch tPLH, tPHL Open tPZL, tPLZ 6V at VCC = 3.3 ± 0.3V, and 2.7V VCC x 2 at VCC = 2.5 ± 0.2V tPZH,tPHZ GND Waveform for Inverting and Non-Inverting Functions 3-STATE Output High Enable and Disable Times for Logic Propagation Delay. Pulse Width and trec Waveforms Setup Time, Hold Time and Recovery Time for Logic trise and tfall 3-STATE Output Low Enable and Disable Times for Logic FIGURE 2. Waveforms (Input Characteristics; f =1MHz, tr = tf = 3ns) Symbol www.fairchildsemi.com VCC 3.3V ± 0.3V 2.7V 2.5V ± 0.2V Vmi 1.5V 1.5V VCC/2 Vmo 1.5V 1.5V VCC/2 Vx VOL + 0.3V VOL + 0.3V VOL + 0.15V Vy VOH − 0.3V VOH − 0.3V VOH − 0.15V 6 74LCX32500 Schematic Diagram Generic for LCX Family 7 www.fairchildsemi.com 74LCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs Physical Dimensions inches (millimeters) unless otherwise noted 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA114A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 8