Revised June 2001 74LVQ14 Low Voltage Hex Inverter with Schmitt Trigger Input General Description Features The LVQ14 contains six inverter gates each with a Schmitt trigger input. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. In addition, they have a greater noise margin than conventional inverters. ■ Ideal for low power/low noise 3.3V applications The LVQ14 has hysteresis between the positive-going and negative-going input thresholds (typically 1.0V) which is determined internally by transistor ratios and is essentially insensitive to temperature and supply voltage variations. ■ Guaranteed simultaneous switching noise level and dynamic threshold performance ■ Guaranteed pin-to-pin skew AC performance ■ Guaranteed incident wave switching into 75Ω Ordering Code: Order Number Package Number Package Description 74LVQ14SC M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74LVQ14SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram IEEE/IEC Pin Descriptions Truth Table Pin Names Description Input Output In Inputs I O On Outputs L H H L H = HIGH Voltage Level L = LOW Voltage Level © 2001 Fairchild Semiconductor Corporation DS011345 www.fairchildsemi.com 74LVQ14 Low Voltage Hex Inverter with Schmitt Trigger Input February 1992 74LVQ14 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC ) Recommended Operating Conditions (Note 2) −0.5V to +7.0V DC Input Diode Current (IIK) Supply Voltage (VCC) VI = −0.5V −20 mA VI = VCC + 0.5V +20 mA DC Input Voltage (VI) LVQ −0.5V to VCC + 0.5V DC Output Diode Current (IOK) −20 mA VO = VCC + 0.5V 0V to VCC −40°C to +85°C Minimum Input Edge Rate (∆V/∆t) +20 mA VIN from 0.8V to 2.0V −0.5V to VCC + 0.5V VCC @ 3.0V DC Output Source ±50 mA or Sink Current (IO) ±200 mA (ICC or IGND) 125 mV/ns Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. DC VCC or Ground Current Storage Temperature (TSTG) 0V to VCC Output Voltage (VO) Operating Temperature (TA) VO = −0.5V DC Output Voltage (VO) 2.0V to 3.6V Input Voltage (VI) −65°C to +150°C Note 2: Unused inputs must be held HIGH or LOW. They may not float. DC Latch-Up Source or ±100 mA Sink Current DC Electrical Characteristics Symbol VOH Parameter Minimum High Level Output Voltage VOL Maximum Low Level Output Voltage TA = +25°C VCC (V) Typ 3.0 2.99 3.0 TA = −40°C to +85°C Units 2.9 2.9 V 2.58 2.48 V 0.1 0.1 V 3.0 0.36 0.44 V 3.0 Conditions Guaranteed Limits 0.002 IOUT = −50 µA VIN = VIL or VIH (Note 3) IOH = −12 mA IOUT = 50 µA VIN = VIL or VIH (Note 3) IOL = 12 mA IIN Maximum Input Leakage Current 3.6 ±0.1 ±1.0 µA Vt+ Maximum Positive Threshold 3.0 2.2 2.2 V Vt− Minimum Negative Threshold 3.0 0.5 0.5 V TA = Worst Case Vh(max) Maximum Hysteresis 3.0 1.2 1.2 V TA = Worst Case Vh(min) Minimum Hysteresis 3.0 0.3 0.3 V IOLD Minimum Dynamic 3.6 36 mA VOLD = 0.8V Max (Note 5) IOHD Output Current (Note 4) 3.6 −25 mA VOHD = 2.0V Min (Note 5) ICC Maximum Quiescent 20.0 µA VIN = VCC or GND Supply Current VOLP Quiet Output Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL VIHD Maximum High Level Dynamic Input Voltage VILD Maximum Low Level Dynamic Input Voltage 3.6 2.0 VI = VCC, GND TA = Worst Case TA = Worst Case 3.3 0.9 1.1 V (Note 6)(Note 7) 3.3 −0.8 −1.1 V (Note 6)(Note 7) 3.3 1.9 2.0 V (Note 6)(Note 8) 3.3 1.3 2.0 V (Note 6)(Note 8) Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: Incident wave switching on transmission lines with impedances as low as 75Ω for commercial temperature range is guaranteed for 74LVQ. Note 6: Worst case package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V; one output at GND. Note 8: Max number of Data Inputs (n) switching. (n − 1) inputs switching 0V to 3.3V. Input-under-test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. www.fairchildsemi.com 2 TA = +25°C Symbol tPLH tPHL Parameter Propagation Delay Propagation Delay TA = −40°C to +85°C CL = 50 pF VCC CL = 50 pF (V) Min Typ Max Min Max 2.7 1.5 11.4 19.0 1.5 21.0 3.3 ± 0.3 1.5 9.5 13.5 1.5 15.0 2.7 1.5 9.0 16.2 1.5 19.0 3.3 ± 0.3 1.5 7.5 11.5 1.5 13.0 tOSHL, Output to Output Skew 2.7 1.0 1.5 1.5 tOSLH Data to Output (Note 9) 3.3 ± 0.3 1.0 1.5 1.5 Units ns ns ns Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH). Parameter guaranteed by design. Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = Open Conditions CPD (Note 10) Power Dissipation Capacitance 20 pF VCC = 3.3V Note 10: CPD is measured at 10 MHz. 3 www.fairchildsemi.com 74LVQ14 AC Electrical Characteristics 74LVQ14 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M14A www.fairchildsemi.com 4 74LVQ14 Low Voltage Hex Inverter with Schmitt Trigger Input Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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