MCP201 LIN Transceiver with Voltage Regulator Package Types PDIP, SOIC, DFN • Supports baud rates up to 20 Kbaud • 40V load dump protected • Wide supply voltage, 6.0 – 18.0V, continuous - Maximum input voltage of 30V • Extended Temperature Range: -40°C to +125°C • Interface to standard USARTs • Compatible with LIN Spec 1.3 • Local Interconnect Network (LIN) Line pin: - Internal pull-up resistor and diode - Protected against ground shorts (LIN pin to ground) - Protected against LIN pin loss of ground - High current drive, 40 mA ≤ IOL ≤ 200 mA • Automatic thermal shutdown • On-board Voltage Regulator: - Output voltage of 5V with ±5% tolerances over temperature range - Maximum output current of 50 mA - Able to drive an external series-pass transistor for increased current supply capability - Internal thermal overload protection - Internal short-circuit current limit - External components limited to filter capacitor only and load capacitor RXD 1 CS/WAKE 2 VREG 3 TXD 4 MCP201 Features 8 FAULT/SLPS 7 VBAT 6 LIN 5 VSS Block Diagram Voltage Regulator VREG Internal Circuits Wake-Up Logic VBAT Ratiometric Reference RXD CS/WAKE approx. 30 kΩ OC TXD LIN FAULT/SLPS POR © 2007 Microchip Technology Inc. Slope Control Thermal Protection Vss DS21730F-page 1 MCP201 NOTES: DS21730F-page 2 © 2007 Microchip Technology Inc. MCP201 1.0 DEVICE OVERVIEW 1.2 Internal Protection The MCP201 provides a physical interface between a microcontroller and a LIN half-duplex bus. It is intended for automotive and industrial applications with serial bus speeds up to 20 Kbaud. 1.2.1 The MCP201 provides a half-duplex, bidirectional communications interface between a microcontroller and the serial network bus. This device will translate the CMOS/TTL logic levels to LIN level logic, and vice versa. 1.2.2 The LIN specification 1.3 requires that the transceiver of all nodes in the system be connected via the LIN pin, referenced to ground and with a maximum external termination resistance of 510Ω from LIN bus to battery supply. The 510Ω corresponds to 1 Master and 16 Slave nodes. The MCP201 provides a +5V 50 mA regulated power output. The regulator uses a LDO design, is shortcircuit-protected and will turn the regulator output off if it falls below 3.5V. The MCP201 also includes thermal shutdown protection. The regulator has been specifically designed to operate in the automotive environment and will survive reverse battery connections, +40V load dump transients and double-battery jumps (see Section 1.6 “Internal Voltage Regulator”). 1.1 Optional External Protection 1.1.1 TRANSIENT VOLTAGE PROTECTION (LOAD DUMP) An external 27V transient suppressor (TVS) diode, between VBAT and ground, with a 50Ω resistor in series with the battery supply and the VBAT pin, serves to protect the device from power transients (see Figure 1-2) and ESD events. While this protection is optional, it should be considered as good engineering practice. 1.1.2 ESD PROTECTION For component-level ESD ratings, please refer to the maximum operation specifications. GROUND LOSS PROTECTION The LIN bus specification states that the LIN pin must transition to the recessive state when ground is disconnected. Therefore, a loss of ground effectively forces the LIN line to a hi-impedance level. 1.2.3 THERMAL PROTECTION The thermal protection circuit monitors the die temperature and is able to shut down the LIN transmitter and voltage regulator. Refer to Table 1-1 for details. There are three causes for a thermal overload. A thermal shut down can be triggered by any one, or a combination of, the following thermal overload conditions. • Voltage regulator overload • LIN bus output overload • Increase in die temperature due to increase in environment temperature Driving the TXD and checking the RXD pin makes it possible to determine whether there is a bus contention (Rx = low, Tx = high) or a thermal overload condition (Rx = high, Tx = low). Note: After recovering from a thermal, bus or voltage regulator overload condition, the device will be in the Ready1 mode. In order to go into Operational mode, the CS/ WAKE pin has to be toggled. REVERSE BATTERY PROTECTION An external reverse-battery-blocking diode can be used to provide polarity protection (see Figure 1-2). This protection is optional, but should be considered as good engineering practice. TABLE 1-1: SOURCES OF THERMAL OVERLOAD(1,2) TXD RXD L H LIN transmitter shutdown, receiver and voltage regulator active, thermal overload condition. Comments H L Regulator shutdown, receiver active, bus contention. Legend: x = Don’t care, L = Low, H = High Note 1: LIN transceiver overload current on the LIN pin is 200 mA. 2: Voltage regulator overload current on voltage regulator greater than 50 mA. © 2007 Microchip Technology Inc. DS21730F-page 3 MCP201 Modes of Operation For an overview of all operational modes, please refer to Table 1-2. 1.3.1 POWER-DOWN MODE In the Power-down mode, the transmitter and the voltage regulator are both off. Only the receiver section and the CS/WAKE pin wake-up circuits are in operation. This is the lowest power mode. 1.3.3 In this mode, all internal modules are operational. The MCP201 will go into Power-down mode on the falling edge of CS/WAKE. FIGURE 1-1: CS/WAKE = true If any bus activity (e.g., a BREAK character) should occur during Power-down mode, the device will immediately enable the voltage regulator. Once the output has stabilized, the device will enter Ready mode. OPERATIONAL MODES STATE DIAGRAMS Power-down Mode Bus Activity FLT CS/WAKE = false Operation Mode The part will enter the Operation mode, if the CS/WAKE pin should become active-high (‘1’). 1.3.2 OPERATION MODE FLT Ready Mode READY AND READY1 MODES CS/WAKE = true There are two states for the Ready mode. The only difference between these states is the transition during start-up. The state Ready1 mode ensures that the transition from Ready to Operation mode (once a rising edge of CS/WAKE) occurs without disrupting bus traffic. Immediately upon entering either Ready1 or Ready mode, the voltage regulator will turn on and provide power. The transmitter portion of the circuit is off, with all other circuits (including the receiver) of the MCP201 being fully operational. The LIN pin is kept in a recessive state. If a microcontroller is being driven by the voltage regulator output, it will go through a power-on reset and initialization sequence. All other circuits, other than the transmitter, are fully operational. The LIN pin is held in the recessive state. The device will stay in Ready mode until the CS/WAKE pin transitions high (‘1’). After CS/WAKE is active, the transmitter is enabled and the device enters Operation mode. The device may only enter Power-down mode after going through the Operation mode step. At power-on of the VBAT supply pin, the component is in either Ready or Ready1 mode, waiting for a CS/WAKE rising edge. The MCP201 will stay in either mode for 600 µs as the regulator powers its internal circuitry and waits until the CS/WAKE pin transitions high. During the 600 µs delay, the MCP201 will not recognize a CS/WAKE event. The CS/WAKE transition from low to high should not occur until after this delay. • The CS input is edge, not level, sensitive. • The CS pin is not monitored until approximately 600 µs after VREG has stabized. • The transistion from Ready1 to Ready is made on the falling edge of CS. • The transition from Ready mode to Operational mode is on the rising edge of CS. DS21730F-page 4 CS/WAKE = false 1.3 POR CS/WAKE = false Ready1 Mode Start CS/WAKE = true Note: After power-on, CS will not be sampled until VREG has stabized and an additional 600 µs has elapsed. The microcontroller should toggle CS approximately 1mS after RESET to ensure that CS will be recognized. Note: While the MCP201 is in shutdown, TXD should not be actively driven high. If TXD is driven high actively, it may power internal logic. 1.3.4 DESCRIPTION OF BROWNOUT CONDITIONS As VBAT decreases VREG is regulated to 5.0 VDC (see VREG in Section 2.2 “DC Specifications”) while VBAT is greater than 5.5 - 6.0 VDC. As VBAT decreases further VREG tracks VBAT (VREG = VBAT - (0.5 to 1.0) VDC. The MCP201 monitors VREG and as long as VREG does not fall below VSD (see VSD in Section 2.2 “DC Specifications”), VREG will remain powered. As VBAT increases VREG will continue to track VBAT until VREG reaches 5.0 VDC. If VREG falls below VSD, VREG is turned off and the MCP201 powers itself down. The MCP201 will remain powered down until VBAT increases above VON (see VON in Section 2.2 “DC Specifications”. © 2007 Microchip Technology Inc. MCP201 TABLE 1-2: State OVERVIEW OF OPERATIONAL MODES Transmitter Voltage Regulator POR OFF OFF Read CS/WAKE. If low, then READY. If high, READY1 mode. Ready OFF ON If CS/WAKE rising edge, then Bus Off state Operation mode. Ready1 OFF ON If CS/WAKE falling edge, then READY mode. Bus Off state Operation ON ON If CS/WAKE falling edge, then Power down. Normal Operation mode Power-down OFF OFF On LIN bus falling, go to Low-Power mode READY mode. On CS/WAKE rising edge, go to Operational mode Note: Operation Comments Sample FAULT/SLPS and select slope After power-on, CS will not be sampled until VREG has stabized and an additional 600 µs has elapsed. The microcontroller should toggle CS approximately 1mS after RESET to ensure that CS will be recognized. © 2007 Microchip Technology Inc. DS21730F-page 5 MCP201 1.4 Typical Applications TYPICAL MCP201 APPLICATION(1,2) FIGURE 1-2: +12V +12V Optional components(5) 10 kΩ WAKE-UP +5V VDD CF Master Node Only 10 uF +12V 27V CG VBAT VREG TXD TXD 1 kΩ MCP201 PIC® MCU RXD I/O (4) D2 24V CS/WAKE D1(3) FAULT/SLPS I/O VSS LIN bus LIN RXD Optional components VSS VREG or VSS 100 kΩ Note 1: The load capacitor, CG, should be a ceramic or tantalum rated for extended temperatures and be in the range of 1.0 - 22 µF with an ESR 0.4Ω - 5Ω.. 2: CF if the filter capacitor for the external voltage supply. 3: This diode is only needed if CS/WAKE is connected to 12V supply. 4: Transient suppressor diode. Vclamp L = 40V. 5: These components are for load dump protection. FIGURE 1-3: TYPICAL LIN NETWORK CONFIGURATION 40m + Return LIN bus 1 kΩ VBAT LIN bus MCP201 LIN bus MCP201 LIN bus MCP201 Slave 1 µC Slave 2 µC LIN bus MCP201 Slave n <16 µC Master µC DS21730F-page 6 © 2007 Microchip Technology Inc. MCP201 1.5 1.5.3 Pin Descriptions TABLE 1-3: MCP201 PINOUT OVERVIEW Devices Function 8-Pin PDIP/ SOIC/DFN Bond Pad Name Normal Operation 1 RXD Receive Data Output (CMOS output) 2 CS/WAKE Chip Select (TTL-HV input) 3 VREG Power Output 4 TXD Transmit Data Input (TTL) 5 VSS Ground 6 LIN LIN bus (bidirectionalHV) 7 VBAT Battery 8 FAULT/SLPS Fault Detect Output, Slope Select Input Legend: TTL = TTL input buffer, HV = High Voltage (VBAT) 1.5.1 RECEIVE DATA OUTPUT (RXD) The Receive Data Output pin is a standard CMOS output and follows the state of the LIN pin. The LIN receiver monitors the state of the LIN pin and generates the output signal RXD. 1.5.2 CS/WAKE Chip Select Input pin. This pin controls whether the part goes into READY1 or READY mode at power-up. The internal pull-down resistor will keep the CS/WAKE pin low. This is done to ensure that no disruptive data will be present on the bus while the microcontroller is executing a Power-on Reset and I/O initialization sequence. The pin must see a low-to-high transition to activate the transmitter. After CS/WAKE transitions to ‘1’, the transmitter is enabled. If CS/WAKE = ‘0’, the device is in Ready1 mode on power-up or in Low-Power mode. In LowPower mode, the voltage regulator is shut down, the transmitter driver is disabled and the receiver logic is enabled. An external switch (see Figure 1-2) can then wake up both the transceiver and the microcontroller. An external-blocking diode and current-limiting resistor are necessary to protect the microcontroller I/O pin. Note: On POR, the MCP201 enters Ready or Ready1 mode (see Figure 1-1). In order to enter Operational mode, the MCP201 has to see one rising edge on CS/WAKE 600 µs after the voltage regulator reaches 5V. © 2007 Microchip Technology Inc. POWER OUTPUT (VREG) Positive Supply Voltage Regulator Output pin. 1.5.4 TRANSMIT DATA INPUT (TXD) The Transmit Data Input pin has an internal pull-up to VREG. The LIN pin is low (dominant) when TXD is low, and high (recessive) when TXD is high. In case the thermal protection detects an over-temperature condition while the signal TXD is low, the transmitter is shutdown. The recovery from the thermal shutdown is equal to adequate cooling time. 1.5.5 GROUND (VSS) Ground pin. 1.5.6 LIN The bidirectional LIN bus Interface pin is the driver unit for the LIN pin and is controlled by the signal TXD. LIN has an open collector output with a current limitation. To reduce EMI, the edges during the signal changes are slope-controlled. 1.5.7 BATTERY (VBAT) Battery Positive Supply Voltage pin. This pin is also the input for the internal voltage regulator. 1.5.8 FAULT/SLPS FAULT Detect Output, Slope Select Input. This pin is usually in Output mode. Its state is defined as shown in Table 1-5. The state of this pin is internally sampled during poweron of VBAT. Once VBAT has reached a stable level, (approximately 6 VDC) and VREG is stable at 4.75 to 5.25 VDC, the state of this pin selects which slew rate profile to apply to the LIN output. It is only during this time that the pin is used as an input (the output driver is off during this time). The slope will stay selected until the next VBAT power-off/power-on sequence, regardless of any power-down, wake-up or SLEEP events. Only a VBAT rising state will cause a sampling of the FAULT/SLPS pin. The Slope selection will be made irrespective of the state of any other pin. The FAULT/SLPS pin is connected to either VREG or VSS through a resistor (approximately 100 kΩ) to make the slope selection. This large resistance allows the FAULT indication function to overdrive the resistor in normal operation mode. If the FAULT/SLPS is high (‘1’), the normal slope shaping is selected (dv/dt = 2 V/µs). If FAULT/SLPS is low (‘0’) during this time, the alternate slope-shaping is selected (dv/dt = 4 V/µs). This mode can be used if a user desires to run at a faster slope. This mode is not LIN compliant. DS21730F-page 7 MCP201 TABLE 1-4: FAULT / SLPS SLOPE SELECTION DURING POR FAULT/SLPS Slope Shaping H Normal L Alternate(1) Note 1: This pin is ‘0’ whenever the internal circuits have detected a short or thermal excursion and have disabled the LIN output driver. Note: Every time TX is toggled, a Fault condition will occur for the length of time, depending on the bus load. The Fault time is equal to the propagation delay. This mode does not conform to LIN bus specification version 1.3, but might be used for K-line applications. TABLE 1-5: TXD In Note: FAULT / SLPS TRUTH TABLE RXD Out LIN Bus I/O Thermal Override FAULT / SLPS Out Comments L H VBAT OFF L Bus shorted to battery H H VBAT OFF H Bus recessive L L GND OFF H Bus dominant H L GND OFF L Bus shorted to ground x x VBAT ON L Thermal excursion Legend: x = don’t care 1.6 Internal Voltage Regulator The MCP201 has a low drop-out voltage, positive regulator capable of supplying 5.00 VDC ±5% at up to 50 mA of load current over the entire operating temperature range. With a load current of 50 mA, the minimum input-to-output voltage differential required for the output to remain in regulation is typically +0.5V (+1V maximum over the full operating temperature range). Quiescent current is less than 1.0 mA, with a full 50 mA load current, when the input-to-output voltage differential is greater than +2V. The regulator requires an external output bypass capacitor for stability. The capacitor should be either a ceramic or tantalum for stable operation over the extended temperature range. The compensation capacitor should range from 1.0 µf – 22 µf and have a ESR or CSR of 0.4Ω – 5.0Ω. The input capacitor, CF, in Figure 1.4 should be on the order of 8 to 10 times larger than the output capacitor, CG. Designed for automotive applications, the regulator will protect itself from reverse battery connections, doublebattery jumps and up to +40V load dump transients. The voltage regulator has both short-circuit and thermal shutdown protection built-in. 6.0V. The device will come up in either READY1 or READY mode and will have to be transitioned to Operational mode to re-enable data transmission. In the start phase, VBAT must be at least 6.0V (Figure 1-4) to initiate operation during power-up. In Power-down mode, the VBAT monitor will be turned off. The regulator has a thermal shutdown. If the thermal protection circuit detects an overtemperature condition caused by an overcurrent condition (Figure 1-6) of the regulator, it will shut down. The regulator has an overload current limiting. During a short-circuit, VREG is monitored. If VREG is lower than 3.5V, the regulator will turn off. After a thermal recovery time, the VREG will be checked again. If there is no short-circuit (VREG > 3.5V), the regulator will be switched back on. The MCP201 will come up in either READY1 or READY mode and will have to be transitioned to Operational mode to re-enable data transmission. The accuracy of the voltage regulator, when using a pass transistor, will degrade due to the extra external components needed. All performance characteristics should be evaluated on every design. Regarding the correlation between VBAT, VREG and IDD, please refer to Figure 1-4 through 1-6. When the input voltage (VBAT) drops below the differential needed to provide stable regulation, the output VREG will track the input down to approximately 3.5V, at which point the regulator will turn off. This will allow microcontrollers with internal POR circuits to generate a clean arming of the Power-on Reset trip point. The MCP201 will then monitor VBAT and turn on the regulator when VBAT is DS21730F-page 8 © 2007 Microchip Technology Inc. MCP201 FIGURE 1-4: VOLTAGE REGULATOR OUTPUT ON POWER-ON RESET V BAT -------------V 8 6 4 2 0 t V REG --------------V 5.5 3.5 3 0 t (1) Note 1: 2: 3: © 2007 Microchip Technology Inc. (2) (3) Start-up, VBAT < 6.0V, regulator off. VBAT > 6.0V, regulator on. VBAT ≤ 5.5V, regulator tracks VBAT, regulator will turn off when VREG < 3.5V. DS21730F-page 9 MCP201 FIGURE 1-5: VOLTAGE REGULATOR OUTPUT ON POWER DIP V BAT -------------V 12 8 6 4 3.5 2 0 t V REG --------------V 5 4 3.5 3 0 t (1) Note 1: 2: 3: 4: DS21730F-page 10 (2) (3) (4) Voltage regulator on. VREG ≤ 5.5V, regulator tracks VBAT until VREG < 3.5V. VREG < 3.5V, regulator is off. If the voltage regulator should shut off due to VREG falling below 3.5V, the VBAT must rise to 6.0V to turn VREG back on. VREG > 4.0V, voltage regulator tracks VDD, when VREG > 4.0V. © 2007 Microchip Technology Inc. MCP201 FIGURE 1-6: VOLTAGE REGULATOR OUTPUT ON OVERCURRENT SITUATION I REG ------------mA 50 0 6 t V REG --------------V 5 3.5 3 0 t (1) Note 1: 2: 1.7 (2) IREG less than 50 mA, regulator on. After IREG exceeds IREGmax, voltage regulator output will be reduced until VREGoff is reached. ICSP™ Considerations The following should be considered when the MCP201 is connected to pins supporting in-circuit programming: • Power used for programming the microcontroller should be supplied from the programmer, not from the MCP201 • The MCP201 should be left unpowered • The voltage on VREG should not exceed the maximum output voltage of VREG • The TXD pin should not be brought high during programming © 2007 Microchip Technology Inc. DS21730F-page 11 MCP201 NOTES: DS21730F-page 12 © 2007 Microchip Technology Inc. MCP201 2.0 ELECTRICAL CHARACTERISTICS 2.1 Absolute Maximum Ratings† VIN DC Voltage on Logic pins except CS/WAKE ................................................................................. -0.3 to VREG+0.3V VIN DC Voltage on CS/WAKE ...............................................................................................................-0.3 to VBAT+0.3V VBAT Battery Voltage, non-operating (LIN bus recessive, no regulator load, t < 60s)....................................-0.3 to +40V VBAT Battery Voltage, transient (Note 1)........................................................................................................-0.3 to +40V VBAT Battery Voltage, continuous ..................................................................................................................-0.3 to +30V VLBUS Bus Voltage, continuous.......................................................................................................................-18 to +30V VLBUS Bus Voltage, transient (Note 1)............................................................................................................-27 to +40V ILBUS Bus Short Circuit Current Limit ....................................................................................................................200 mA ESD protection on LIN, VBAT (Human Body Model) (Note 2) .................................................................................. >4 kV ESD protection on all other pins (Human Body Model) (Note 2) ............................................................................. >2 kV Maximum Junction Temperature ............................................................................................................................. 150°C Storage Temperature .................................................................................................................................. -55 to +150°C Note 1: ISO 7637/1 load dump compliant (t < 500 ms). 2: According to JESD22-A114-B. † NOTICE: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2007 Microchip Technology Inc. DS21730F-page 13 MCP201 2.2 DC Specifications Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBAT = 6.0V to 18.0V TAMB = -40°C to +125°C CLOADREG = 10 µF DC Specifications Sym. Parameter Min. Typ. Max. Units Conditions VBAT Quiescent Operating Current (voltage regulator without load and transceiver) — 0.45 1.0 mA IVREG = 0 mA, LIN bus pin recessive, (Note 3) IBAT VBAT Power-down Current transceiver only — 23 50 µA CS/WAKE = High, voltage regulator disabled IDDQ VREG Quiescent Operating Current — 500 — µA (Note 2) IVREG VREG maximum output current — — 50 mA (Note 4) Power IBATQ Microcontroller Interface VIH High-level Input Voltage (TXD, FAULT/SLPS) 2.0 — VREG + 0.3 V VIL Low-level Input Voltage (TXD, FAULT/SLPS) -0.3 — 0.15 x VREG V IIHTXD High-level Output Current (TXD) -90 — +30 µA Input voltage = 4V IILTXD Low-level Output Current (TXD) -150 — -10 µA Input voltage = 1V (though > 50 kΩ internal pull-up) VIHCS/ High-level Input Voltage (CS/WAKE) 3.0 — VBAT V Through an external currentlimiting resistor (10 kΩ) Low-level Input Voltage (CS/WAKE) -0.3 — 1.0 V High-level Input Current (CS/WAKE) -10 — +80 µA Input voltage = 4V (though >100 kΩ internal pull-down) Low-level Input Current (CS/WAKE) 5 — 30 µA Input voltage = 1V WAKE VILCS/ WAKE IIHCS/ WAKE IILCS/ WAKE VOHRXD High-level Output Voltage (RXD) 0.8 VREG — — IOH = -4 mA VOLRXD Low-level Output Voltage (RXD) — — 0.2 VREG IOL = 4 mA Note 1: 2: 3: 4: Internal current limited. 2.0 ms typical recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBAT, TAMB = 25C. Recovery time highly dependent on ambient temperature, package and thermal resistance). For design guidance only, not tested. This current is at the VBAT pin. The maximum power dissipation is a function of TJMAX, ΘJA and ambient temperature TA. The maximum allowable power dissipation at an ambient temperature is PD = (TJMAX - TA)ΘJA. If this dissipation is exceeded, the die temperature will rise above 150°C and the MCP201 will go into thermal shutdown. DS21730F-page 14 © 2007 Microchip Technology Inc. MCP201 2.2 DC Specifications (Continued) Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBAT = 6.0V to 18.0V TAMB = -40°C to +125°C CLOADREG = 10 µF DC Specifications Sym. Parameter Min. Typ. Max. Units Conditions Bus Interface VIHLBUS High-level Input Voltage (LBUS) 0.6 VBAT — 18 V Recessive state VILLBUS Low-level Input Voltage (LBUS) -8 — 0.4 VBAT V Dominant state 0.05 VBAT — 0.1 VBAT V VIH - VIL VHYS Input Hysteresis IOL Low-level Output Current (LBUS) 40 — 200 mA Output voltage = 0.1 VBAT, VBAT = 12V IO High-level Output Current (LBUS) -20 — 20 µA VBUS ≥ VBAT, VLBUS < 40V IP Pull-up Current on Input (LBUS) -180 — -60 µA Approx. 30 kΩ internal pull-up @ VIH = 0.7 VBAT ISC Short-circuit Current-Limit 50 — 200 mA (Note 1) VOH High-level Output Voltage (LBUS) 0.8 VBAT — — V VOL Low-level Output Voltage (LBUS) — — 0.2 VBAT V Voltage Regulator VREG Output Voltage 4.75 — 5.25 V 0 mA > IOUT > 50 mA, 7.0V < VBAT < 18V VREG1 Output Voltage 4.4 — 5.25 V 0 mA > IOUT > 50 mA, 6.0V < VBAT < 7.0V ΔVREG1 Line Regulation — 10 50 mV IOUT = 1 mA, 7.0V < VBAT < 18V ΔVREG2 Load Regulation — 10 50 mV 5 mA < IOUT < 50 mA, VBAT = Constant VN Output Noise Voltage — — 400 VSD Shutdown Voltage (monitoring VREG) 3.5 — 4.0 V VON Input Voltage to Turn On Output (monitoring VBAT) 5.5 — 6.0 V Note 1: 2: 3: 4: µVRMS 1 VRMS @ 10 Hz - 100 kHz See Figure 1-4 Internal current limited. 2.0 ms typical recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBAT, TAMB = 25C. Recovery time highly dependent on ambient temperature, package and thermal resistance). For design guidance only, not tested. This current is at the VBAT pin. The maximum power dissipation is a function of TJMAX, ΘJA and ambient temperature TA. The maximum allowable power dissipation at an ambient temperature is PD = (TJMAX - TA)ΘJA. If this dissipation is exceeded, the die temperature will rise above 150°C and the MCP201 will go into thermal shutdown. © 2007 Microchip Technology Inc. DS21730F-page 15 MCP201 2.3 AC Specifications Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VBAT = 6.0V to 18.0V TAMB = -40°C to +125°C AC Specifications Symbol Parameter Min Typical Max Units Conditions Bus Interface |dV/dt| Slope Rising and Falling Edges 1.0 2.0 3.0 V/µ s (40% to 60%), No Load |dV/dt| Slope Rising and Falling edges ALTERNATE 2.0 4.0 6.0 V/µ s (Note 1), No Load Propagation Delay of Transmitter — — 6.0 µs tRECPD = max tTRANSPD tRECPD — — 6.0 µs (tRECPDR or tRECPDF) tRECSYM Propagation Delay of Receiver Symmetry of Propagation Delay of Receiver Rising Edge with Respect to Falling Edge -2.0 — 2.0 µs tRECSYM = max tTRANSSYM Symmetry of Propagation Delay of Transmitter Rising Edge with Respect to Falling Edge -2.0 — 2.0 µs tTRANSSYM = max (tTRANSPDF - tRANSPDR) Bus Activity to Voltage Regulator Enabled 10 — 40 µs Bus debounce time tVEVR Voltage Regulator Enabled to Ready — 50 200 µs (Note 2) tVREGPOR Voltage Regulator Enabled to Ready after POR — — 2.5 ms (Note 2) CLOAD = 25 nF tCSOR Chip Select to Operation Ready 0 50 200 µs (Note 2) tCSPD Chip Select to Power-down 0 — 40 µs (Note 2) No CLOAD Short-Circuit to Shutdown — 450 — µs Characterized but not tested Short-Circuit Recovery Time — 2.0 — ms Characterized but not tested (Note 3) Voltage Regulator tBACTVE tSHUTDOWN tSCREC Note 1: 2: 3: The mode does not conform to LIN Bus specification version 1.3. Time depends on external capacitance and load. Internal current limited. 2.0 ms typical recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBAT, TAMB = 25C. Recovery time highly dependent on ambient temperature, package, and thermal resistance). TABLE 2-1: MCP201 THERMAL SPECIFICATIONS Sym Min Typical Max Units θRECOVERY Recovery Temperature (junction temperature) — +135 — °C Characterized but not tested θSHUTDOWN Shutdown Temperature (junction temperature) — +155 — °C Characterized but not tested — 2.0 — ms Characterized but not tested (Note 1) tTHERM Note 1: Parameter Thermal Recovery Time (after Fault condition removed) Test Conditions Internal current limited. 2.0 ms typical recovery time (RLBUS = 0Ω, TX = 0.4 VREG, VLBUS = VBAT, TAMB = 25C. Recovery time highly dependent on ambient temperature, package, and thermal resistance). DS21730F-page 16 © 2007 Microchip Technology Inc. MCP201 2.4 Timing Diagrams and Specifications FIGURE 2-1: BUS TIMING DIAGRAM TXD LBUS .6 VBAT .4 VBAT TTRANSPDR TTRANSPDF TRECPDF TRECPDR RXD FIGURE 2-2: REGULATOR TIMING DIAGRAM ON CS/WAKE SIGNAL CS/WAKE TCSOR Regulator Stable VREG TCSPD © 2007 Microchip Technology Inc. DS21730F-page 17 MCP201 FIGURE 2-3: REGULATOR TIMING DIAGRAM ON BUS ACTIVITY Regulator Stable VREG TVEVR TBACTVE LBUS .4 VBAT FIGURE 2-4: POR DIAGRAM 6V VBAT VREG 5.0V tVREGPOR DS21730F-page 18 © 2007 Microchip Technology Inc. MCP201 3.0 CHARACTERIZATION GRAPHS FIGURE 3-1: IDD(mA) vs. VBAT tCSPD (µs) vs. VBAT(V) 700 tCSPD (µs) -40(C) tCSPD (µs) 25(C) 600 tCSPD (µs) 125(C) tCSPD (µs) 500 400 300 200 100 dap/jx 3/5/03 30 parts Y1004 B2 0 4 6 8 10 12 14 16 18 20 VBAT(v) © 2007 Microchip Technology Inc. DS21730F-page 19 MCP201 FIGURE 3-2: REGULATOR VOLTAGE (V) VS. REGULATOR CURRENT Regulator Voltage (V) vs. Regulator Current (A) 5.25 VREGOUT (V) VBAT 18(V) -40(C) VREGOUT (V) VBAT 14.4(V) -40(C) VREGOUT (V) VBAT 8(V) -40(C) VREGOUT (V) VBAT 6(V) -40(C) VREGOUT (V) VBAT 18(V) 25(C) VREGOUT (V) VBAT 14.4(V) 25(C) VREGOUT (V) VBAT 8(V) 25(C) VREGOUT (V) VBAT 6(V) 25(C) VREGOUT (V) VBAT 18(V) 125(C) VREGOUT (V) VBAT 14.4(V) 125(C) VREGOUT (V) VBAT 8(V) 125(C) VREGOUT (V) VBAT 6(V) 125(C) 5.15 Regulator Voltage (V) 5.05 4.95 4.85 4.75 4.65 4.55 4.45 dap/jx 2/28/03 30 parts Y1004 B2 4.35 4.25 0 10 20 30 40 50 60 Regulator Current (mA) DS21730F-page 20 © 2007 Microchip Technology Inc. MCP201 FIGURE 3-3: REGULATOR CHANGE (V) VS. LINE VOLTAGE CHANGE Line Regulation Regulator Change (V) vs Line Voltage Change (mV) 5 Regulator Change (mV) -40(C) Load = 50(mA) 0 Regulator Change (mV) -40(C) Load = 25(mA) Regulator Change (mV) Regulator Change (mV) -40(C) Load = 5(mA) -5 Regulator Change (mV) -40(C) Load = 1(mA) Regulator Change (mV) 25(C) Load = 50(mA) -10 Regulator Change (mV) 25(C) Load = 25(mA) Regulator Change (mV) 25(C) Load = 5(mA) -15 Regulator Change (mV) 25(C) Load = 1(mA) Regulator Change (mV) 125(C) Load = 50(mA) -20 Regulator Change (mV) 125(C) Load = 25(mA) Regulator Change (mV) 125(C) Load = 5(mA) -25 Regulator Change (mV) 125(C) Load = 1(mA) -30 dap/jx 3/3/03 30 parts Y1004 B2 -35 -40 0 2 4 6 8 10 12 14 Line Voltage Change (V) © 2007 Microchip Technology Inc. DS21730F-page 21 MCP201 FIGURE 3-4: LOAD REGULATION REGULATOR CHANGE VS. REGULATOR LOAD CHANGE Load Regulation Regulator Change (mV) vs. Regulator Load Change (mA) 70 Regulator Change (mV) -40C VBAT = 18V Regulator Change (mV) -40C VBAT = 14.4V 60 Regular Charge (mV) Regulator Change (mV) -40C VBAT = 8.0V Regulator Change (mV) -40C VBAT = 6.0V 50 Regulator Change (mV) 25C VBAT = 18V Regulator Change (mV) 25C VBAT = 14.4V 40 Regulator Change (mV) 25C VBAT = 8.0V Regulator Change (mV) 25C VBAT = 6.0V 30 Regulator Change (mV) 125C VBAT = 18V Regulator Change (mV) 125C VBAT = 14.4V Regulator Change (mV) 125C VBAT = 8.0V 20 Regulator Change (mV) 125C VBAT = 6.0V 10 dap/jx 3/3/03 30 parts Y1004 B2 0 0 10 20 30 40 50 60 Regular Load Current Change (mA) DS21730F-page 22 © 2007 Microchip Technology Inc. MCP201 FIGURE 3-5: FALLING EDGE NORMAL DV/DT VS. VBAT Falling Edge Normal dVdT (V/µs) vs. VBAT(v) 2.40 Falling Edge Normal dVdT (V/µs) -40(C) Falling Edge Normal dVdT (V/µs) 2.35 Falling Edge Normal dVdT (V/µs) 25(C) Falling Edge Normal dVdT (V/µs) 125(C) 2.30 2.25 2.20 2.15 2.10 2.05 2.00 dap/jx 3/6/03 30 parts Y1004 B2 1.95 1.90 4 6 8 10 12 14 16 18 20 VBAT(v) © 2007 Microchip Technology Inc. DS21730F-page 23 MCP201 FIGURE 3-6: RISING EDGE NORMAL DV/DT VS. VBAT Rising Edge Normal dV/dT (V/µs) vs. VBAT(V) 2.2 Rising Edge Normal dVdT (V/µs) -40(C) Rising Edge Normal dVdT (V/µs) 25(C) Rising Edge Normal dVdT (V/µs) 125(C) Rising Edge Normal dV/dT (V/µs) 2.1 2.0 1.9 1.8 dap/jx 3/6/03 30 parts Y1004 B2 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 4 6 8 10 12 14 16 18 20 VBAT(V) DS21730F-page 24 © 2007 Microchip Technology Inc. MCP201 FIGURE 3-7: BUS ACTIVE VS. VBAT tBACTIVE (µs) vs. VBAT(V) 55 tBACTIVE (µs) -40(C) tBACTIVE (µs) 25(C) tBACTIVE (µs) 125(C) tBACTIVE (µs) 50 45 40 35 dap/jx 3/6/03 30 parts Y1004 B2 30 4 6 8 10 12 14 16 18 20 VBAT(V) © 2007 Microchip Technology Inc. DS21730F-page 25 MCP201 FIGURE 3-8: VOLTAGE REGULATOR ACTIVE TIME VS. VBAT tVEVR (µs) vs. VBAT(V) 10000 tVEVR (µs) -40(C) tVEVR (µs) 25(C) tVEVR (µs) 125(C) tVEVR (µs) 1000 100 dap/jx 3/6/03 30 parts Y1004 B2 10 10 4 6 8 10 12 14 16 18 20 VBAT(v) DS21730F-page 26 © 2007 Microchip Technology Inc. MCP201 FIGURE 3-9: CHIP SELECT TO OPERATION READY tCSOR (µs) vs. VBAT(V) 14 tCSOR (µs) -40(C) tCSOR (µs) 25(C) 13 tCSOR (µs) 125(C) 12 tCSOR (µs) 11 10 9 8 7 6 5 dap/jx 3/5/03 30 parts Y1004 B2 4 4 6 8 10 12 14 16 18 20 VBAT(v) © 2007 Microchip Technology Inc. DS21730F-page 27 MCP201 FIGURE 3-10: CHIP SELECT TO POWER DOWN tCSPD (µs) vs. VBAT(V) 700 tCSPD (µs) -40(C) tCSPD (µs) 25(C) 600 tCSPD (µs) 125(C) tCSPD (µs) 500 400 300 200 100 dap/jx 3/5/03 30 parts Y1004 B2 0 4 6 8 10 12 14 16 18 20 VBAT(v) DS21730F-page 28 © 2007 Microchip Technology Inc. MCP201 FIGURE 3-11: PROPAGATION DELAY OF TRANSMITTER tTRANSPD (µs) Rising Edge Normal vs. VBAT(V) 2.5 tTRANSPD (µs) Rising Edge Normal -40(C) 2.4 tTRANSPD (µs) Rising Edge Normal 25(C) tTRANSPD (µs) Rising Edge Normal 2.3 tTRANSPD (µs) Rising Edge Normal 125(C) 2.2 2.1 2 1.9 1.8 1.7 1.6 dap/jx 3/6/03 30 parts Y1004 B2 1.5 4 6 8 10 12 14 16 18 20 VBAT(v) © 2007 Microchip Technology Inc. DS21730F-page 29 MCP201 FIGURE 3-12: PROPAGATION DELAY OF RECEIVER tRECPD (µs) Falling Edge Normal vs. VBAT(V) tRECPD (µs) Falling Edge Normal 3.3 tRECPD (µs) Falling Edge Normal -40(C) 3.1 tRECPD (µs) Falling Edge Normal 25(C) 2.9 tRECPD (µs) Falling Edge Normal 125(C) 2.7 dap/jx 3/6/03 30 parts Y1004 B2 2.5 2.3 2.1 1.9 1.7 1.5 4 6 8 10 12 14 16 18 20 VBAT(v) DS21730F-page 30 © 2007 Microchip Technology Inc. MCP201 4.0 PACKAGING INFORMATION 4.1 Package Marking Information 8-Lead DFN-S Example: XXXXXXXX XXXXXXXX YYWW NNN MCP201 E/MF e3 0715 256 8-Lead PDIP (300 mil) MCP201 e3 E/P256 0715 XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Legend: XX...X Y YY WW NNN e3 * Note: Example: Example: MCP201 e3 E/SN0715 256 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2007 Microchip Technology Inc. DS21730F-page 31 MCP201 8-Lead Plastic Dual Flat, No Lead Package (MF) – 6x5 mm Body [DFN-S] PUNCH SINGULATED Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e D1 L b N N K E E2 E1 EXPOSED PAD NOTE 1 2 2 1 1 NOTE 1 D2 TOP VIEW BOTTOM VIEW φ A2 A A1 A3 NOTE 2 Units Dimension Limits Number of Pins MILLIMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 1.27 BSC 0.85 1.00 Molded Package Thickness A2 – 0.65 0.80 Standoff A1 0.00 0.01 0.05 Base Thickness A3 0.20 REF Overall Length D 4.92 BSC Molded Package Length D1 Exposed Pad Length D2 Overall Width E Molded Package Width E1 Exposed Pad Width E2 2.16 2.31 Contact Width b 0.35 0.40 0.47 Contact Length L 0.50 0.60 0.75 Contact-to-Exposed Pad K 0.20 – – Model Draft Angle Top φ – – 12° 4.67 BSC 3.85 4.00 4.15 5.99 BSC 5.74 BSC 2.46 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-113B DS21730F-page 32 © 2007 Microchip Technology Inc. MCP201 8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 3 2 D E A2 A L A1 c e eB b1 b Units Dimension Limits Number of Pins INCHES MIN N NOM MAX 8 Pitch e Top to Seating Plane A – – .210 Molded Package Thickness A2 .115 .130 .195 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .325 Molded Package Width E1 .240 .250 .280 Overall Length D .348 .365 .400 Tip to Seating Plane L .115 .130 .150 Lead Thickness c .008 .010 .015 Upper Lead Width b1 .040 .060 .070 b .014 .018 .022 eB – – Lower Lead Width Overall Row Spacing § .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located with the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. © 2007 Microchip Technology Inc. DS21730F-page 33 MCP201 8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e N E E1 NOTE 1 1 2 3 α h b h A2 A c φ L A1 β L1 Units Dimension Limits Number of Pins MILLMETERS MIN N NOM MAX 8 Pitch e Overall Height A – 1.27 BSC – Molded Package Thickness A2 1.25 – – Standoff § A1 0.10 – 0.25 Overall Width E Molded Package Width E1 3.90 BSC Overall Length D 4.90 BSC 1.75 6.00 BSC Chamfer (optional) h 0.25 – 0.50 Foot Length L 0.40 – 1.27 Footprint L1 1.04 REF Foot Angle φ 0° – 8° Lead Thickness c 0.17 – 0.25 Lead Width b 0.31 – 0.51 Mold Draft Angle Top α 5° – 15° Mold Draft Angle Bottom β 5° – 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-057B DS21730F-page 34 © 2007 Microchip Technology Inc. MCP201 APPENDIX A: REVISION HISTORY Revision F (January 2007) This revision includes updates to the packaging diagrams. © 2007 Microchip Technology Inc. DS21730F-page 35 MCP201 NOTES: DS21730F-page 36 © 2007 Microchip Technology Inc. MCP201 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. X /XX Device Temperature Range Package Device: MCP201: MCP201T: LIN Transceiver with Voltage Regulator LIN Transceiver with Voltage Regulator (Tape and Reel) Temperature Range: I E = -40°C to +85°C = -40°C to +125°C Package: MF = Dual Flatpack, No-Lead (6x5 mm Body), 8-lead P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead © 2007 Microchip Technology Inc. Examples: a) MCP201-E/SN: Extended Temperature, SOIC package. b) MCP201-E/P: Extended Temperature, PDIP package. c) MCP201-I/SN: Industrial Temperature, SOIC package. d) MCP201-I/P: Industrial Temperature, PDIP package. e) MCP201T-I/SN: Tape and Reel, Industrial Temperature, SOIC package. f) MCP201T-E/SN: Tape and Reel, Extended Temperature, SOIC package. g) MCP201-E/MF: h) MCP201T-E/MF: Tape and Reel, Extended Temperature, DFN package. Extended Temperature, DFN package. DS21730F-page 37 MCP201 NOTES: DS21730F-page 38 © 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2007 Microchip Technology Inc. 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